1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author: Jacob Chen <jacob-chen@iotwrt.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/fs.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/timer.h> 19 20 #include <linux/platform_device.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-event.h> 23 #include <media/v4l2-ioctl.h> 24 #include <media/v4l2-mem2mem.h> 25 #include <media/videobuf2-dma-sg.h> 26 #include <media/videobuf2-v4l2.h> 27 28 #include "rga-hw.h" 29 #include "rga.h" 30 31 static int debug; 32 module_param(debug, int, 0644); 33 34 static void device_run(void *prv) 35 { 36 struct rga_ctx *ctx = prv; 37 struct rockchip_rga *rga = ctx->rga; 38 struct vb2_v4l2_buffer *src, *dst; 39 unsigned long flags; 40 41 spin_lock_irqsave(&rga->ctrl_lock, flags); 42 43 rga->curr = ctx; 44 45 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 46 src->sequence = ctx->osequence++; 47 48 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 49 50 rga_hw_start(rga, vb_to_rga(src), vb_to_rga(dst)); 51 52 spin_unlock_irqrestore(&rga->ctrl_lock, flags); 53 } 54 55 static irqreturn_t rga_isr(int irq, void *prv) 56 { 57 struct rockchip_rga *rga = prv; 58 int intr; 59 60 intr = rga_read(rga, RGA_INT) & 0xf; 61 62 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4); 63 64 if (intr & 0x04) { 65 struct vb2_v4l2_buffer *src, *dst; 66 struct rga_ctx *ctx = rga->curr; 67 68 WARN_ON(!ctx); 69 70 rga->curr = NULL; 71 72 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 73 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 74 75 WARN_ON(!src); 76 WARN_ON(!dst); 77 78 v4l2_m2m_buf_copy_metadata(src, dst, true); 79 80 dst->sequence = ctx->csequence++; 81 82 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE); 83 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); 84 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx); 85 } 86 87 return IRQ_HANDLED; 88 } 89 90 static const struct v4l2_m2m_ops rga_m2m_ops = { 91 .device_run = device_run, 92 }; 93 94 static int 95 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 96 { 97 struct rga_ctx *ctx = priv; 98 int ret; 99 100 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 101 src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 102 src_vq->drv_priv = ctx; 103 src_vq->ops = &rga_qops; 104 src_vq->mem_ops = &vb2_dma_sg_memops; 105 src_vq->gfp_flags = __GFP_DMA32; 106 src_vq->buf_struct_size = sizeof(struct rga_vb_buffer); 107 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 108 src_vq->lock = &ctx->rga->mutex; 109 src_vq->dev = ctx->rga->v4l2_dev.dev; 110 111 ret = vb2_queue_init(src_vq); 112 if (ret) 113 return ret; 114 115 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 116 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 117 dst_vq->drv_priv = ctx; 118 dst_vq->ops = &rga_qops; 119 dst_vq->mem_ops = &vb2_dma_sg_memops; 120 dst_vq->gfp_flags = __GFP_DMA32; 121 dst_vq->buf_struct_size = sizeof(struct rga_vb_buffer); 122 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 123 dst_vq->lock = &ctx->rga->mutex; 124 dst_vq->dev = ctx->rga->v4l2_dev.dev; 125 126 return vb2_queue_init(dst_vq); 127 } 128 129 static int rga_s_ctrl(struct v4l2_ctrl *ctrl) 130 { 131 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx, 132 ctrl_handler); 133 unsigned long flags; 134 135 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags); 136 switch (ctrl->id) { 137 case V4L2_CID_HFLIP: 138 ctx->hflip = ctrl->val; 139 break; 140 case V4L2_CID_VFLIP: 141 ctx->vflip = ctrl->val; 142 break; 143 case V4L2_CID_ROTATE: 144 ctx->rotate = ctrl->val; 145 break; 146 case V4L2_CID_BG_COLOR: 147 ctx->fill_color = ctrl->val; 148 break; 149 } 150 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags); 151 return 0; 152 } 153 154 static const struct v4l2_ctrl_ops rga_ctrl_ops = { 155 .s_ctrl = rga_s_ctrl, 156 }; 157 158 static int rga_setup_ctrls(struct rga_ctx *ctx) 159 { 160 struct rockchip_rga *rga = ctx->rga; 161 162 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4); 163 164 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 165 V4L2_CID_HFLIP, 0, 1, 1, 0); 166 167 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 168 V4L2_CID_VFLIP, 0, 1, 1, 0); 169 170 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 171 V4L2_CID_ROTATE, 0, 270, 90, 0); 172 173 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 174 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0); 175 176 if (ctx->ctrl_handler.error) { 177 int err = ctx->ctrl_handler.error; 178 179 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__); 180 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 181 return err; 182 } 183 184 return 0; 185 } 186 187 static struct rga_fmt formats[] = { 188 { 189 .fourcc = V4L2_PIX_FMT_ARGB32, 190 .color_swap = RGA_COLOR_ALPHA_SWAP, 191 .hw_format = RGA_COLOR_FMT_ABGR8888, 192 .depth = 32, 193 .uv_factor = 1, 194 .y_div = 1, 195 .x_div = 1, 196 }, 197 { 198 .fourcc = V4L2_PIX_FMT_ABGR32, 199 .color_swap = RGA_COLOR_RB_SWAP, 200 .hw_format = RGA_COLOR_FMT_ABGR8888, 201 .depth = 32, 202 .uv_factor = 1, 203 .y_div = 1, 204 .x_div = 1, 205 }, 206 { 207 .fourcc = V4L2_PIX_FMT_XBGR32, 208 .color_swap = RGA_COLOR_RB_SWAP, 209 .hw_format = RGA_COLOR_FMT_XBGR8888, 210 .depth = 32, 211 .uv_factor = 1, 212 .y_div = 1, 213 .x_div = 1, 214 }, 215 { 216 .fourcc = V4L2_PIX_FMT_RGB24, 217 .color_swap = RGA_COLOR_NONE_SWAP, 218 .hw_format = RGA_COLOR_FMT_RGB888, 219 .depth = 24, 220 .uv_factor = 1, 221 .y_div = 1, 222 .x_div = 1, 223 }, 224 { 225 .fourcc = V4L2_PIX_FMT_BGR24, 226 .color_swap = RGA_COLOR_RB_SWAP, 227 .hw_format = RGA_COLOR_FMT_RGB888, 228 .depth = 24, 229 .uv_factor = 1, 230 .y_div = 1, 231 .x_div = 1, 232 }, 233 { 234 .fourcc = V4L2_PIX_FMT_ARGB444, 235 .color_swap = RGA_COLOR_RB_SWAP, 236 .hw_format = RGA_COLOR_FMT_ABGR4444, 237 .depth = 16, 238 .uv_factor = 1, 239 .y_div = 1, 240 .x_div = 1, 241 }, 242 { 243 .fourcc = V4L2_PIX_FMT_ARGB555, 244 .color_swap = RGA_COLOR_RB_SWAP, 245 .hw_format = RGA_COLOR_FMT_ABGR1555, 246 .depth = 16, 247 .uv_factor = 1, 248 .y_div = 1, 249 .x_div = 1, 250 }, 251 { 252 .fourcc = V4L2_PIX_FMT_RGB565, 253 .color_swap = RGA_COLOR_RB_SWAP, 254 .hw_format = RGA_COLOR_FMT_BGR565, 255 .depth = 16, 256 .uv_factor = 1, 257 .y_div = 1, 258 .x_div = 1, 259 }, 260 { 261 .fourcc = V4L2_PIX_FMT_NV21, 262 .color_swap = RGA_COLOR_UV_SWAP, 263 .hw_format = RGA_COLOR_FMT_YUV420SP, 264 .depth = 12, 265 .uv_factor = 4, 266 .y_div = 2, 267 .x_div = 1, 268 }, 269 { 270 .fourcc = V4L2_PIX_FMT_NV61, 271 .color_swap = RGA_COLOR_UV_SWAP, 272 .hw_format = RGA_COLOR_FMT_YUV422SP, 273 .depth = 16, 274 .uv_factor = 2, 275 .y_div = 1, 276 .x_div = 1, 277 }, 278 { 279 .fourcc = V4L2_PIX_FMT_NV12, 280 .color_swap = RGA_COLOR_NONE_SWAP, 281 .hw_format = RGA_COLOR_FMT_YUV420SP, 282 .depth = 12, 283 .uv_factor = 4, 284 .y_div = 2, 285 .x_div = 1, 286 }, 287 { 288 .fourcc = V4L2_PIX_FMT_NV12M, 289 .color_swap = RGA_COLOR_NONE_SWAP, 290 .hw_format = RGA_COLOR_FMT_YUV420SP, 291 .depth = 12, 292 .uv_factor = 4, 293 .y_div = 2, 294 .x_div = 1, 295 }, 296 { 297 .fourcc = V4L2_PIX_FMT_NV16, 298 .color_swap = RGA_COLOR_NONE_SWAP, 299 .hw_format = RGA_COLOR_FMT_YUV422SP, 300 .depth = 16, 301 .uv_factor = 2, 302 .y_div = 1, 303 .x_div = 1, 304 }, 305 { 306 .fourcc = V4L2_PIX_FMT_YUV420, 307 .color_swap = RGA_COLOR_NONE_SWAP, 308 .hw_format = RGA_COLOR_FMT_YUV420P, 309 .depth = 12, 310 .uv_factor = 4, 311 .y_div = 2, 312 .x_div = 2, 313 }, 314 { 315 .fourcc = V4L2_PIX_FMT_YUV422P, 316 .color_swap = RGA_COLOR_NONE_SWAP, 317 .hw_format = RGA_COLOR_FMT_YUV422P, 318 .depth = 16, 319 .uv_factor = 2, 320 .y_div = 1, 321 .x_div = 2, 322 }, 323 { 324 .fourcc = V4L2_PIX_FMT_YVU420, 325 .color_swap = RGA_COLOR_UV_SWAP, 326 .hw_format = RGA_COLOR_FMT_YUV420P, 327 .depth = 12, 328 .uv_factor = 4, 329 .y_div = 2, 330 .x_div = 2, 331 }, 332 }; 333 334 #define NUM_FORMATS ARRAY_SIZE(formats) 335 336 static struct rga_fmt *rga_fmt_find(u32 pixelformat) 337 { 338 unsigned int i; 339 340 for (i = 0; i < NUM_FORMATS; i++) { 341 if (formats[i].fourcc == pixelformat) 342 return &formats[i]; 343 } 344 return NULL; 345 } 346 347 static struct rga_frame def_frame = { 348 .width = DEFAULT_WIDTH, 349 .height = DEFAULT_HEIGHT, 350 .colorspace = V4L2_COLORSPACE_DEFAULT, 351 .crop.left = 0, 352 .crop.top = 0, 353 .crop.width = DEFAULT_WIDTH, 354 .crop.height = DEFAULT_HEIGHT, 355 .fmt = &formats[0], 356 }; 357 358 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type) 359 { 360 if (V4L2_TYPE_IS_OUTPUT(type)) 361 return &ctx->in; 362 if (V4L2_TYPE_IS_CAPTURE(type)) 363 return &ctx->out; 364 return ERR_PTR(-EINVAL); 365 } 366 367 static int rga_open(struct file *file) 368 { 369 struct rockchip_rga *rga = video_drvdata(file); 370 struct rga_ctx *ctx = NULL; 371 int ret = 0; 372 373 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 374 if (!ctx) 375 return -ENOMEM; 376 ctx->rga = rga; 377 /* Set default formats */ 378 ctx->in = def_frame; 379 ctx->out = def_frame; 380 381 v4l2_fill_pixfmt_mp(&ctx->in.pix, 382 ctx->in.fmt->fourcc, ctx->out.width, ctx->out.height); 383 v4l2_fill_pixfmt_mp(&ctx->out.pix, 384 ctx->out.fmt->fourcc, ctx->out.width, ctx->out.height); 385 386 if (mutex_lock_interruptible(&rga->mutex)) { 387 kfree(ctx); 388 return -ERESTARTSYS; 389 } 390 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init); 391 if (IS_ERR(ctx->fh.m2m_ctx)) { 392 ret = PTR_ERR(ctx->fh.m2m_ctx); 393 mutex_unlock(&rga->mutex); 394 kfree(ctx); 395 return ret; 396 } 397 v4l2_fh_init(&ctx->fh, video_devdata(file)); 398 v4l2_fh_add(&ctx->fh, file); 399 400 rga_setup_ctrls(ctx); 401 402 /* Write the default values to the ctx struct */ 403 v4l2_ctrl_handler_setup(&ctx->ctrl_handler); 404 405 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 406 mutex_unlock(&rga->mutex); 407 408 return 0; 409 } 410 411 static int rga_release(struct file *file) 412 { 413 struct rga_ctx *ctx = file_to_rga_ctx(file); 414 struct rockchip_rga *rga = ctx->rga; 415 416 mutex_lock(&rga->mutex); 417 418 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 419 420 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 421 v4l2_fh_del(&ctx->fh, file); 422 v4l2_fh_exit(&ctx->fh); 423 kfree(ctx); 424 425 mutex_unlock(&rga->mutex); 426 427 return 0; 428 } 429 430 static const struct v4l2_file_operations rga_fops = { 431 .owner = THIS_MODULE, 432 .open = rga_open, 433 .release = rga_release, 434 .poll = v4l2_m2m_fop_poll, 435 .unlocked_ioctl = video_ioctl2, 436 .mmap = v4l2_m2m_fop_mmap, 437 }; 438 439 static int 440 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 441 { 442 strscpy(cap->driver, RGA_NAME, sizeof(cap->driver)); 443 strscpy(cap->card, "rockchip-rga", sizeof(cap->card)); 444 strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info)); 445 446 return 0; 447 } 448 449 static int vidioc_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f) 450 { 451 struct rga_fmt *fmt; 452 453 if (f->index >= NUM_FORMATS) 454 return -EINVAL; 455 456 fmt = &formats[f->index]; 457 f->pixelformat = fmt->fourcc; 458 459 return 0; 460 } 461 462 static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) 463 { 464 struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp; 465 struct rga_ctx *ctx = file_to_rga_ctx(file); 466 struct vb2_queue *vq; 467 struct rga_frame *frm; 468 469 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 470 if (!vq) 471 return -EINVAL; 472 frm = rga_get_frame(ctx, f->type); 473 if (IS_ERR(frm)) 474 return PTR_ERR(frm); 475 476 v4l2_fill_pixfmt_mp(pix_fmt, frm->fmt->fourcc, frm->width, frm->height); 477 478 pix_fmt->field = V4L2_FIELD_NONE; 479 pix_fmt->colorspace = frm->colorspace; 480 481 return 0; 482 } 483 484 static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) 485 { 486 struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp; 487 struct rga_fmt *fmt; 488 489 fmt = rga_fmt_find(pix_fmt->pixelformat); 490 if (!fmt) 491 fmt = &formats[0]; 492 493 pix_fmt->width = clamp(pix_fmt->width, 494 (u32)MIN_WIDTH, (u32)MAX_WIDTH); 495 pix_fmt->height = clamp(pix_fmt->height, 496 (u32)MIN_HEIGHT, (u32)MAX_HEIGHT); 497 498 v4l2_fill_pixfmt_mp(pix_fmt, fmt->fourcc, pix_fmt->width, pix_fmt->height); 499 pix_fmt->field = V4L2_FIELD_NONE; 500 501 return 0; 502 } 503 504 static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f) 505 { 506 struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp; 507 struct rga_ctx *ctx = file_to_rga_ctx(file); 508 struct rockchip_rga *rga = ctx->rga; 509 struct vb2_queue *vq; 510 struct rga_frame *frm; 511 int ret = 0; 512 int i; 513 514 /* Adjust all values accordingly to the hardware capabilities 515 * and chosen format. 516 */ 517 ret = vidioc_try_fmt(file, priv, f); 518 if (ret) 519 return ret; 520 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 521 if (vb2_is_busy(vq)) { 522 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type); 523 return -EBUSY; 524 } 525 frm = rga_get_frame(ctx, f->type); 526 if (IS_ERR(frm)) 527 return PTR_ERR(frm); 528 frm->width = pix_fmt->width; 529 frm->height = pix_fmt->height; 530 frm->size = 0; 531 for (i = 0; i < pix_fmt->num_planes; i++) 532 frm->size += pix_fmt->plane_fmt[i].sizeimage; 533 frm->fmt = rga_fmt_find(pix_fmt->pixelformat); 534 frm->stride = pix_fmt->plane_fmt[0].bytesperline; 535 frm->colorspace = pix_fmt->colorspace; 536 537 /* Reset crop settings */ 538 frm->crop.left = 0; 539 frm->crop.top = 0; 540 frm->crop.width = frm->width; 541 frm->crop.height = frm->height; 542 543 frm->pix = *pix_fmt; 544 545 v4l2_dbg(debug, 1, &rga->v4l2_dev, 546 "[%s] fmt - %p4cc %dx%d (stride %d, sizeimage %d)\n", 547 V4L2_TYPE_IS_OUTPUT(f->type) ? "OUTPUT" : "CAPTURE", 548 &frm->fmt->fourcc, frm->width, frm->height, 549 frm->stride, frm->size); 550 551 for (i = 0; i < pix_fmt->num_planes; i++) { 552 v4l2_dbg(debug, 1, &rga->v4l2_dev, 553 "plane[%d]: size %d, bytesperline %d\n", 554 i, pix_fmt->plane_fmt[i].sizeimage, 555 pix_fmt->plane_fmt[i].bytesperline); 556 } 557 558 return 0; 559 } 560 561 static int vidioc_g_selection(struct file *file, void *priv, 562 struct v4l2_selection *s) 563 { 564 struct rga_ctx *ctx = file_to_rga_ctx(file); 565 struct rga_frame *f; 566 bool use_frame = false; 567 568 f = rga_get_frame(ctx, s->type); 569 if (IS_ERR(f)) 570 return PTR_ERR(f); 571 572 switch (s->target) { 573 case V4L2_SEL_TGT_COMPOSE_DEFAULT: 574 case V4L2_SEL_TGT_COMPOSE_BOUNDS: 575 if (!V4L2_TYPE_IS_CAPTURE(s->type)) 576 return -EINVAL; 577 break; 578 case V4L2_SEL_TGT_CROP_DEFAULT: 579 case V4L2_SEL_TGT_CROP_BOUNDS: 580 if (!V4L2_TYPE_IS_OUTPUT(s->type)) 581 return -EINVAL; 582 break; 583 case V4L2_SEL_TGT_COMPOSE: 584 if (!V4L2_TYPE_IS_CAPTURE(s->type)) 585 return -EINVAL; 586 use_frame = true; 587 break; 588 case V4L2_SEL_TGT_CROP: 589 if (!V4L2_TYPE_IS_OUTPUT(s->type)) 590 return -EINVAL; 591 use_frame = true; 592 break; 593 default: 594 return -EINVAL; 595 } 596 597 if (use_frame) { 598 s->r = f->crop; 599 } else { 600 s->r.left = 0; 601 s->r.top = 0; 602 s->r.width = f->width; 603 s->r.height = f->height; 604 } 605 606 return 0; 607 } 608 609 static int vidioc_s_selection(struct file *file, void *priv, 610 struct v4l2_selection *s) 611 { 612 struct rga_ctx *ctx = file_to_rga_ctx(file); 613 struct rockchip_rga *rga = ctx->rga; 614 struct rga_frame *f; 615 int ret = 0; 616 617 f = rga_get_frame(ctx, s->type); 618 if (IS_ERR(f)) 619 return PTR_ERR(f); 620 621 switch (s->target) { 622 case V4L2_SEL_TGT_COMPOSE: 623 /* 624 * COMPOSE target is only valid for capture buffer type, return 625 * error for output buffer type 626 */ 627 if (!V4L2_TYPE_IS_CAPTURE(s->type)) 628 return -EINVAL; 629 break; 630 case V4L2_SEL_TGT_CROP: 631 /* 632 * CROP target is only valid for output buffer type, return 633 * error for capture buffer type 634 */ 635 if (!V4L2_TYPE_IS_OUTPUT(s->type)) 636 return -EINVAL; 637 break; 638 /* 639 * bound and default crop/compose targets are invalid targets to 640 * try/set 641 */ 642 default: 643 return -EINVAL; 644 } 645 646 if (s->r.top < 0 || s->r.left < 0) { 647 v4l2_dbg(debug, 1, &rga->v4l2_dev, 648 "doesn't support negative values for top & left.\n"); 649 return -EINVAL; 650 } 651 652 if (s->r.left + s->r.width > f->width || 653 s->r.top + s->r.height > f->height || 654 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) { 655 v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n"); 656 return -EINVAL; 657 } 658 659 f->crop = s->r; 660 661 return ret; 662 } 663 664 static const struct v4l2_ioctl_ops rga_ioctl_ops = { 665 .vidioc_querycap = vidioc_querycap, 666 667 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt, 668 .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt, 669 .vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt, 670 .vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt, 671 672 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt, 673 .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt, 674 .vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt, 675 .vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt, 676 677 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 678 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 679 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 680 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 681 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 682 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 683 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 684 685 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 686 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 687 688 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 689 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 690 691 .vidioc_g_selection = vidioc_g_selection, 692 .vidioc_s_selection = vidioc_s_selection, 693 }; 694 695 static const struct video_device rga_videodev = { 696 .name = "rockchip-rga", 697 .fops = &rga_fops, 698 .ioctl_ops = &rga_ioctl_ops, 699 .minor = -1, 700 .release = video_device_release, 701 .vfl_dir = VFL_DIR_M2M, 702 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING, 703 }; 704 705 static int rga_enable_clocks(struct rockchip_rga *rga) 706 { 707 int ret; 708 709 ret = clk_prepare_enable(rga->sclk); 710 if (ret) { 711 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret); 712 return ret; 713 } 714 715 ret = clk_prepare_enable(rga->aclk); 716 if (ret) { 717 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret); 718 goto err_disable_sclk; 719 } 720 721 ret = clk_prepare_enable(rga->hclk); 722 if (ret) { 723 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret); 724 goto err_disable_aclk; 725 } 726 727 return 0; 728 729 err_disable_aclk: 730 clk_disable_unprepare(rga->aclk); 731 err_disable_sclk: 732 clk_disable_unprepare(rga->sclk); 733 734 return ret; 735 } 736 737 static void rga_disable_clocks(struct rockchip_rga *rga) 738 { 739 clk_disable_unprepare(rga->sclk); 740 clk_disable_unprepare(rga->hclk); 741 clk_disable_unprepare(rga->aclk); 742 } 743 744 static int rga_parse_dt(struct rockchip_rga *rga) 745 { 746 struct reset_control *core_rst, *axi_rst, *ahb_rst; 747 748 core_rst = devm_reset_control_get(rga->dev, "core"); 749 if (IS_ERR(core_rst)) { 750 dev_err(rga->dev, "failed to get core reset controller\n"); 751 return PTR_ERR(core_rst); 752 } 753 754 axi_rst = devm_reset_control_get(rga->dev, "axi"); 755 if (IS_ERR(axi_rst)) { 756 dev_err(rga->dev, "failed to get axi reset controller\n"); 757 return PTR_ERR(axi_rst); 758 } 759 760 ahb_rst = devm_reset_control_get(rga->dev, "ahb"); 761 if (IS_ERR(ahb_rst)) { 762 dev_err(rga->dev, "failed to get ahb reset controller\n"); 763 return PTR_ERR(ahb_rst); 764 } 765 766 reset_control_assert(core_rst); 767 udelay(1); 768 reset_control_deassert(core_rst); 769 770 reset_control_assert(axi_rst); 771 udelay(1); 772 reset_control_deassert(axi_rst); 773 774 reset_control_assert(ahb_rst); 775 udelay(1); 776 reset_control_deassert(ahb_rst); 777 778 rga->sclk = devm_clk_get(rga->dev, "sclk"); 779 if (IS_ERR(rga->sclk)) { 780 dev_err(rga->dev, "failed to get sclk clock\n"); 781 return PTR_ERR(rga->sclk); 782 } 783 784 rga->aclk = devm_clk_get(rga->dev, "aclk"); 785 if (IS_ERR(rga->aclk)) { 786 dev_err(rga->dev, "failed to get aclk clock\n"); 787 return PTR_ERR(rga->aclk); 788 } 789 790 rga->hclk = devm_clk_get(rga->dev, "hclk"); 791 if (IS_ERR(rga->hclk)) { 792 dev_err(rga->dev, "failed to get hclk clock\n"); 793 return PTR_ERR(rga->hclk); 794 } 795 796 return 0; 797 } 798 799 static int rga_probe(struct platform_device *pdev) 800 { 801 struct rockchip_rga *rga; 802 struct video_device *vfd; 803 int ret = 0; 804 int irq; 805 806 if (!pdev->dev.of_node) 807 return -ENODEV; 808 809 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL); 810 if (!rga) 811 return -ENOMEM; 812 813 rga->dev = &pdev->dev; 814 spin_lock_init(&rga->ctrl_lock); 815 mutex_init(&rga->mutex); 816 817 ret = rga_parse_dt(rga); 818 if (ret) 819 return dev_err_probe(&pdev->dev, ret, "Unable to parse OF data\n"); 820 821 pm_runtime_enable(rga->dev); 822 823 rga->regs = devm_platform_ioremap_resource(pdev, 0); 824 if (IS_ERR(rga->regs)) { 825 ret = PTR_ERR(rga->regs); 826 goto err_put_clk; 827 } 828 829 irq = platform_get_irq(pdev, 0); 830 if (irq < 0) { 831 ret = irq; 832 goto err_put_clk; 833 } 834 835 ret = devm_request_irq(rga->dev, irq, rga_isr, 0, 836 dev_name(rga->dev), rga); 837 if (ret < 0) { 838 dev_err(rga->dev, "failed to request irq\n"); 839 goto err_put_clk; 840 } 841 842 ret = dma_set_mask_and_coherent(rga->dev, DMA_BIT_MASK(32)); 843 if (ret) { 844 dev_err(rga->dev, "32-bit DMA not supported"); 845 goto err_put_clk; 846 } 847 848 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev); 849 if (ret) 850 goto err_put_clk; 851 vfd = video_device_alloc(); 852 if (!vfd) { 853 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n"); 854 ret = -ENOMEM; 855 goto unreg_v4l2_dev; 856 } 857 *vfd = rga_videodev; 858 vfd->lock = &rga->mutex; 859 vfd->v4l2_dev = &rga->v4l2_dev; 860 861 video_set_drvdata(vfd, rga); 862 rga->vfd = vfd; 863 864 platform_set_drvdata(pdev, rga); 865 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops); 866 if (IS_ERR(rga->m2m_dev)) { 867 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n"); 868 ret = PTR_ERR(rga->m2m_dev); 869 goto rel_vdev; 870 } 871 872 ret = pm_runtime_resume_and_get(rga->dev); 873 if (ret < 0) 874 goto rel_m2m; 875 876 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF; 877 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F; 878 879 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n", 880 rga->version.major, rga->version.minor); 881 882 pm_runtime_put(rga->dev); 883 884 /* Create CMD buffer */ 885 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE, 886 &rga->cmdbuf_phy, GFP_KERNEL, 887 DMA_ATTR_WRITE_COMBINE); 888 if (!rga->cmdbuf_virt) { 889 ret = -ENOMEM; 890 goto rel_m2m; 891 } 892 893 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3; 894 def_frame.size = def_frame.stride * def_frame.height; 895 896 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); 897 if (ret) { 898 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n"); 899 goto free_dma; 900 } 901 902 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n", 903 vfd->name, video_device_node_name(vfd)); 904 905 return 0; 906 907 free_dma: 908 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt, 909 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE); 910 rel_m2m: 911 v4l2_m2m_release(rga->m2m_dev); 912 rel_vdev: 913 video_device_release(vfd); 914 unreg_v4l2_dev: 915 v4l2_device_unregister(&rga->v4l2_dev); 916 err_put_clk: 917 pm_runtime_disable(rga->dev); 918 919 return ret; 920 } 921 922 static void rga_remove(struct platform_device *pdev) 923 { 924 struct rockchip_rga *rga = platform_get_drvdata(pdev); 925 926 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt, 927 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE); 928 929 v4l2_info(&rga->v4l2_dev, "Removing\n"); 930 931 v4l2_m2m_release(rga->m2m_dev); 932 video_unregister_device(rga->vfd); 933 v4l2_device_unregister(&rga->v4l2_dev); 934 935 pm_runtime_disable(rga->dev); 936 } 937 938 static int __maybe_unused rga_runtime_suspend(struct device *dev) 939 { 940 struct rockchip_rga *rga = dev_get_drvdata(dev); 941 942 rga_disable_clocks(rga); 943 944 return 0; 945 } 946 947 static int __maybe_unused rga_runtime_resume(struct device *dev) 948 { 949 struct rockchip_rga *rga = dev_get_drvdata(dev); 950 951 return rga_enable_clocks(rga); 952 } 953 954 static const struct dev_pm_ops rga_pm = { 955 SET_RUNTIME_PM_OPS(rga_runtime_suspend, 956 rga_runtime_resume, NULL) 957 }; 958 959 static const struct of_device_id rockchip_rga_match[] = { 960 { 961 .compatible = "rockchip,rk3288-rga", 962 }, 963 { 964 .compatible = "rockchip,rk3399-rga", 965 }, 966 {}, 967 }; 968 969 MODULE_DEVICE_TABLE(of, rockchip_rga_match); 970 971 static struct platform_driver rga_pdrv = { 972 .probe = rga_probe, 973 .remove = rga_remove, 974 .driver = { 975 .name = RGA_NAME, 976 .pm = &rga_pm, 977 .of_match_table = rockchip_rga_match, 978 }, 979 }; 980 981 module_platform_driver(rga_pdrv); 982 983 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>"); 984 MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit"); 985 MODULE_LICENSE("GPL"); 986