1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * vsp1_pipe.c -- R-Car VSP1 Pipeline 4 * 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 6 * 7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/list.h> 12 #include <linux/sched.h> 13 #include <linux/wait.h> 14 15 #include <media/media-entity.h> 16 #include <media/v4l2-subdev.h> 17 18 #include "vsp1.h" 19 #include "vsp1_brx.h" 20 #include "vsp1_dl.h" 21 #include "vsp1_entity.h" 22 #include "vsp1_hgo.h" 23 #include "vsp1_hgt.h" 24 #include "vsp1_pipe.h" 25 #include "vsp1_rwpf.h" 26 #include "vsp1_uds.h" 27 28 /* ----------------------------------------------------------------------------- 29 * Helper Functions 30 */ 31 32 static const struct vsp1_format_info vsp1_video_formats[] = { 33 { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32, 34 VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 35 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 36 1, { 8, 0, 0 }, false, false, 1, 1, false }, 37 { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32, 38 VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 39 VI6_RPF_DSWAP_P_WDS, 40 1, { 16, 0, 0 }, false, false, 1, 1, true }, 41 { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32, 42 VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 43 VI6_RPF_DSWAP_P_WDS, 44 1, { 16, 0, 0 }, false, false, 1, 1, false }, 45 { V4L2_PIX_FMT_RGBA444, MEDIA_BUS_FMT_ARGB8888_1X32, 46 VI6_FMT_RGBA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 47 VI6_RPF_DSWAP_P_WDS, 48 1, { 16, 0, 0 }, false, false, 1, 1, true }, 49 { V4L2_PIX_FMT_RGBX444, MEDIA_BUS_FMT_ARGB8888_1X32, 50 VI6_FMT_RGBX_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 51 VI6_RPF_DSWAP_P_WDS, 52 1, { 16, 0, 0 }, false, false, 1, 1, false }, 53 { V4L2_PIX_FMT_ABGR444, MEDIA_BUS_FMT_ARGB8888_1X32, 54 VI6_FMT_ABGR_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 55 VI6_RPF_DSWAP_P_WDS, 56 1, { 16, 0, 0 }, false, false, 1, 1, true }, 57 { V4L2_PIX_FMT_XBGR444, MEDIA_BUS_FMT_ARGB8888_1X32, 58 VI6_FMT_ABGR_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 59 VI6_RPF_DSWAP_P_WDS, 60 1, { 16, 0, 0 }, false, false, 1, 1, false }, 61 { V4L2_PIX_FMT_BGRA444, MEDIA_BUS_FMT_ARGB8888_1X32, 62 VI6_FMT_BGRA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 63 VI6_RPF_DSWAP_P_WDS, 64 1, { 16, 0, 0 }, false, false, 1, 1, true }, 65 { V4L2_PIX_FMT_BGRX444, MEDIA_BUS_FMT_ARGB8888_1X32, 66 VI6_FMT_BGRA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 67 VI6_RPF_DSWAP_P_WDS, 68 1, { 16, 0, 0 }, false, false, 1, 1, false }, 69 { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32, 70 VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 71 VI6_RPF_DSWAP_P_WDS, 72 1, { 16, 0, 0 }, false, false, 1, 1, true }, 73 { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32, 74 VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 75 VI6_RPF_DSWAP_P_WDS, 76 1, { 16, 0, 0 }, false, false, 1, 1, false }, 77 { V4L2_PIX_FMT_RGBA555, MEDIA_BUS_FMT_ARGB8888_1X32, 78 VI6_FMT_RGBA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 79 VI6_RPF_DSWAP_P_WDS, 80 1, { 16, 0, 0 }, false, false, 1, 1, true }, 81 { V4L2_PIX_FMT_RGBX555, MEDIA_BUS_FMT_ARGB8888_1X32, 82 VI6_FMT_RGBX_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 83 VI6_RPF_DSWAP_P_WDS, 84 1, { 16, 0, 0 }, false, false, 1, 1, false }, 85 { V4L2_PIX_FMT_ABGR555, MEDIA_BUS_FMT_ARGB8888_1X32, 86 VI6_FMT_ABGR_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 87 VI6_RPF_DSWAP_P_WDS, 88 1, { 16, 0, 0 }, false, false, 1, 1, true }, 89 { V4L2_PIX_FMT_XBGR555, MEDIA_BUS_FMT_ARGB8888_1X32, 90 VI6_FMT_ABGR_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 91 VI6_RPF_DSWAP_P_WDS, 92 1, { 16, 0, 0 }, false, false, 1, 1, false }, 93 { V4L2_PIX_FMT_BGRA555, MEDIA_BUS_FMT_ARGB8888_1X32, 94 VI6_FMT_BGRA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 95 VI6_RPF_DSWAP_P_WDS, 96 1, { 16, 0, 0 }, false, false, 1, 1, true }, 97 { V4L2_PIX_FMT_BGRX555, MEDIA_BUS_FMT_ARGB8888_1X32, 98 VI6_FMT_BGRA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 99 VI6_RPF_DSWAP_P_WDS, 100 1, { 16, 0, 0 }, false, false, 1, 1, false }, 101 { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32, 102 VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 103 VI6_RPF_DSWAP_P_WDS, 104 1, { 16, 0, 0 }, false, false, 1, 1, false }, 105 { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32, 106 VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 107 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 108 1, { 24, 0, 0 }, false, false, 1, 1, false }, 109 { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32, 110 VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 111 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 112 1, { 24, 0, 0 }, false, false, 1, 1, false }, 113 { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32, 114 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 115 1, { 32, 0, 0 }, false, false, 1, 1, true }, 116 { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32, 117 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 118 1, { 32, 0, 0 }, false, false, 1, 1, false }, 119 { V4L2_PIX_FMT_BGRA32, MEDIA_BUS_FMT_ARGB8888_1X32, 120 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 121 1, { 32, 0, 0 }, false, false, 1, 1, true }, 122 { V4L2_PIX_FMT_BGRX32, MEDIA_BUS_FMT_ARGB8888_1X32, 123 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 124 1, { 32, 0, 0 }, false, false, 1, 1, false }, 125 { V4L2_PIX_FMT_RGBA32, MEDIA_BUS_FMT_ARGB8888_1X32, 126 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 127 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 128 1, { 32, 0, 0 }, false, false, 1, 1, true }, 129 { V4L2_PIX_FMT_RGBX32, MEDIA_BUS_FMT_ARGB8888_1X32, 130 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 131 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 132 1, { 32, 0, 0 }, false, false, 1, 1, false }, 133 { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32, 134 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 135 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 136 1, { 32, 0, 0 }, false, false, 1, 1, true }, 137 { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32, 138 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 139 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 140 1, { 32, 0, 0 }, false, false, 1, 1, false }, 141 { V4L2_PIX_FMT_RGBX1010102, MEDIA_BUS_FMT_ARGB8888_1X32, 142 VI6_FMT_RGB10_RGB10A2_A2RGB10, 143 VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 144 1, { 32, 0, 0 }, false, false, 1, 1, false }, 145 { V4L2_PIX_FMT_RGBA1010102, MEDIA_BUS_FMT_ARGB8888_1X32, 146 VI6_FMT_RGB10_RGB10A2_A2RGB10, 147 VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 148 1, { 32, 0, 0 }, false, false, 1, 1, false }, 149 { V4L2_PIX_FMT_ARGB2101010, MEDIA_BUS_FMT_ARGB8888_1X32, 150 VI6_FMT_RGB10_RGB10A2_A2RGB10, 151 VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 152 1, { 32, 0, 0 }, false, false, 1, 1, false }, 153 { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32, 154 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 155 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 156 1, { 16, 0, 0 }, false, false, 2, 1, false }, 157 { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32, 158 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 159 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 160 1, { 16, 0, 0 }, true, false, 2, 1, false }, 161 { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32, 162 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 163 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 164 1, { 16, 0, 0 }, true, true, 2, 1, false }, 165 { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32, 166 VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 167 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 168 2, { 8, 16, 0 }, false, false, 2, 2, false }, 169 { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32, 170 VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 171 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 172 2, { 8, 16, 0 }, false, true, 2, 2, false }, 173 { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32, 174 VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 175 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 176 2, { 8, 16, 0 }, false, false, 2, 1, false }, 177 { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32, 178 VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 179 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 180 2, { 8, 16, 0 }, false, true, 2, 1, false }, 181 { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32, 182 VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 183 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 184 3, { 8, 8, 8 }, false, false, 2, 2, false }, 185 { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32, 186 VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 187 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 188 3, { 8, 8, 8 }, false, true, 2, 2, false }, 189 { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32, 190 VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 191 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 192 3, { 8, 8, 8 }, false, false, 2, 1, false }, 193 { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32, 194 VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 195 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 196 3, { 8, 8, 8 }, false, true, 2, 1, false }, 197 { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32, 198 VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 199 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 200 3, { 8, 8, 8 }, false, false, 1, 1, false }, 201 { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32, 202 VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 203 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 204 3, { 8, 8, 8 }, false, true, 1, 1, false }, 205 { V4L2_PIX_FMT_Y210, MEDIA_BUS_FMT_AYUV8_1X32, 206 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 207 1, { 32, 0, 0 }, false, false, 2, 1, false }, 208 { V4L2_PIX_FMT_Y212, MEDIA_BUS_FMT_AYUV8_1X32, 209 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 210 1, { 32, 0, 0 }, false, false, 2, 1, false }, 211 }; 212 213 static const struct vsp1_format_info vsp1_video_gen2_formats[] = { 214 { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32, 215 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 216 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 217 1, { 16, 0, 0 }, false, true, 2, 1, false }, 218 }; 219 220 static const struct vsp1_format_info vsp1_video_hsit_formats[] = { 221 { V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32, 222 VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 223 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 224 1, { 24, 0, 0 }, false, false, 1, 1, false }, 225 { V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32, 226 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 227 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 228 1, { 32, 0, 0 }, false, false, 1, 1, false }, 229 }; 230 231 /** 232 * vsp1_get_format_info - Retrieve format information for a 4CC 233 * @vsp1: the VSP1 device 234 * @fourcc: the format 4CC 235 * 236 * Return a pointer to the format information structure corresponding to the 237 * given V4L2 format 4CC, or NULL if no corresponding format can be found. 238 */ 239 const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1, 240 u32 fourcc) 241 { 242 unsigned int i; 243 244 for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) { 245 const struct vsp1_format_info *info = &vsp1_video_formats[i]; 246 247 if (info->fourcc == fourcc) 248 return info; 249 } 250 251 if (vsp1->info->gen == 2) { 252 for (i = 0; i < ARRAY_SIZE(vsp1_video_gen2_formats); ++i) { 253 const struct vsp1_format_info *info = 254 &vsp1_video_gen2_formats[i]; 255 256 if (info->fourcc == fourcc) 257 return info; 258 } 259 } 260 261 if (vsp1_feature(vsp1, VSP1_HAS_HSIT)) { 262 for (i = 0; i < ARRAY_SIZE(vsp1_video_hsit_formats); ++i) { 263 const struct vsp1_format_info *info = 264 &vsp1_video_hsit_formats[i]; 265 266 if (info->fourcc == fourcc) 267 return info; 268 } 269 } 270 271 return NULL; 272 } 273 274 /** 275 * vsp1_get_format_info_by_index - Enumerate format information 276 * @vsp1: the VSP1 device 277 * @index: the format index 278 * @code: media bus code to limit enumeration 279 * 280 * Return a pointer to the format information structure corresponding to the 281 * given index, or NULL if the index exceeds the supported formats list. If the 282 * @code parameter is not zero, only formats compatible with the media bus code 283 * will be enumerated. 284 */ 285 const struct vsp1_format_info * 286 vsp1_get_format_info_by_index(struct vsp1_device *vsp1, unsigned int index, 287 u32 code) 288 { 289 unsigned int i; 290 291 if (!code) { 292 if (index < ARRAY_SIZE(vsp1_video_formats)) 293 return &vsp1_video_formats[index]; 294 295 if (vsp1->info->gen == 2) { 296 index -= ARRAY_SIZE(vsp1_video_formats); 297 if (index < ARRAY_SIZE(vsp1_video_gen2_formats)) 298 return &vsp1_video_gen2_formats[index]; 299 } 300 301 if (vsp1_feature(vsp1, VSP1_HAS_HSIT)) { 302 index -= ARRAY_SIZE(vsp1_video_gen2_formats); 303 if (index < ARRAY_SIZE(vsp1_video_hsit_formats)) 304 return &vsp1_video_hsit_formats[index]; 305 } 306 307 return NULL; 308 } 309 310 for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) { 311 const struct vsp1_format_info *info = &vsp1_video_formats[i]; 312 313 if (info->mbus == code) { 314 if (!index) 315 return info; 316 index--; 317 } 318 } 319 320 if (vsp1->info->gen == 2) { 321 for (i = 0; i < ARRAY_SIZE(vsp1_video_gen2_formats); ++i) { 322 const struct vsp1_format_info *info = 323 &vsp1_video_gen2_formats[i]; 324 325 if (info->mbus == code) { 326 if (!index) 327 return info; 328 index--; 329 } 330 } 331 } 332 333 if (vsp1_feature(vsp1, VSP1_HAS_HSIT)) { 334 for (i = 0; i < ARRAY_SIZE(vsp1_video_hsit_formats); ++i) { 335 const struct vsp1_format_info *info = 336 &vsp1_video_hsit_formats[i]; 337 338 if (info->mbus == code) { 339 if (!index) 340 return info; 341 index--; 342 } 343 } 344 } 345 346 return NULL; 347 } 348 349 /** 350 * vsp1_adjust_color_space - Adjust color space fields in a format 351 * @code: the media bus code 352 * @colorspace: the colorspace 353 * @xfer_func: the transfer function 354 * @encoding: the encoding 355 * @quantization: the quantization 356 * 357 * This function adjusts all color space fields of a video device of subdev 358 * format structure, taking into account the requested format, requested color 359 * space and limitations of the VSP1. It should be used in the video device and 360 * subdev set format handlers. 361 * 362 * The colorspace and xfer_func fields are freely configurable, as they are out 363 * of scope for VSP processing. The encoding and quantization is hardcoded for 364 * non-YUV formats, and can be configured for YUV formats. 365 */ 366 void vsp1_adjust_color_space(u32 code, u32 *colorspace, u8 *xfer_func, 367 u8 *encoding, u8 *quantization) 368 { 369 if (*colorspace == V4L2_COLORSPACE_DEFAULT || 370 *colorspace >= V4L2_COLORSPACE_LAST) 371 *colorspace = code == MEDIA_BUS_FMT_AYUV8_1X32 372 ? V4L2_COLORSPACE_SMPTE170M 373 : V4L2_COLORSPACE_SRGB; 374 375 if (*xfer_func == V4L2_XFER_FUNC_DEFAULT || 376 *xfer_func >= V4L2_XFER_FUNC_LAST) 377 *xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(*colorspace); 378 379 switch (code) { 380 case MEDIA_BUS_FMT_ARGB8888_1X32: 381 default: 382 *encoding = V4L2_YCBCR_ENC_601; 383 *quantization = V4L2_QUANTIZATION_FULL_RANGE; 384 break; 385 386 case MEDIA_BUS_FMT_AHSV8888_1X32: 387 *encoding = V4L2_HSV_ENC_256; 388 *quantization = V4L2_QUANTIZATION_FULL_RANGE; 389 break; 390 391 case MEDIA_BUS_FMT_AYUV8_1X32: 392 if (*encoding != V4L2_YCBCR_ENC_601 && 393 *encoding != V4L2_YCBCR_ENC_709) 394 *encoding = V4L2_YCBCR_ENC_601; 395 if (*quantization != V4L2_QUANTIZATION_FULL_RANGE && 396 *quantization != V4L2_QUANTIZATION_LIM_RANGE) 397 *quantization = V4L2_QUANTIZATION_LIM_RANGE; 398 break; 399 } 400 } 401 402 /* ----------------------------------------------------------------------------- 403 * Pipeline Management 404 */ 405 406 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) 407 { 408 struct vsp1_entity *entity; 409 unsigned int i; 410 411 if (pipe->brx) { 412 struct vsp1_brx *brx = to_brx(&pipe->brx->subdev); 413 414 for (i = 0; i < ARRAY_SIZE(brx->inputs); ++i) 415 brx->inputs[i].rpf = NULL; 416 } 417 418 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) 419 pipe->inputs[i] = NULL; 420 421 pipe->output = NULL; 422 423 list_for_each_entry(entity, &pipe->entities, list_pipe) 424 entity->pipe = NULL; 425 426 INIT_LIST_HEAD(&pipe->entities); 427 pipe->state = VSP1_PIPELINE_STOPPED; 428 pipe->buffers_ready = 0; 429 pipe->num_inputs = 0; 430 pipe->brx = NULL; 431 pipe->hgo = NULL; 432 pipe->hgt = NULL; 433 pipe->iif = NULL; 434 pipe->lif = NULL; 435 pipe->uds = NULL; 436 } 437 438 void vsp1_pipeline_init(struct vsp1_pipeline *pipe) 439 { 440 mutex_init(&pipe->lock); 441 spin_lock_init(&pipe->irqlock); 442 init_waitqueue_head(&pipe->wq); 443 kref_init(&pipe->kref); 444 445 INIT_LIST_HEAD(&pipe->entities); 446 pipe->state = VSP1_PIPELINE_STOPPED; 447 } 448 449 void __vsp1_pipeline_dump(struct _ddebug *dbg, struct vsp1_pipeline *pipe, 450 const char *msg) 451 { 452 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; 453 struct vsp1_entity *entity; 454 bool first = true; 455 456 printk(KERN_DEBUG "%s: %s: pipe: ", dev_name(vsp1->dev), msg); 457 458 list_for_each_entry(entity, &pipe->entities, list_pipe) { 459 const char *name; 460 461 name = strchrnul(entity->subdev.name, ' '); 462 name = name ? name + 1 : entity->subdev.name; 463 464 pr_cont("%s%s", first ? "" : ", ", name); 465 first = false; 466 } 467 468 pr_cont("\n"); 469 } 470 471 /* Must be called with the pipe irqlock held. */ 472 void vsp1_pipeline_run(struct vsp1_pipeline *pipe) 473 { 474 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; 475 476 if (pipe->state == VSP1_PIPELINE_STOPPED) { 477 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index), 478 VI6_CMD_STRCMD); 479 pipe->state = VSP1_PIPELINE_RUNNING; 480 } 481 482 pipe->buffers_ready = 0; 483 } 484 485 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) 486 { 487 unsigned long flags; 488 bool stopped; 489 490 spin_lock_irqsave(&pipe->irqlock, flags); 491 stopped = pipe->state == VSP1_PIPELINE_STOPPED; 492 spin_unlock_irqrestore(&pipe->irqlock, flags); 493 494 return stopped; 495 } 496 497 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) 498 { 499 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; 500 struct vsp1_entity *entity; 501 unsigned long flags; 502 int ret; 503 504 if (pipe->lif) { 505 /* 506 * When using display lists in continuous frame mode the only 507 * way to stop the pipeline is to reset the hardware. 508 */ 509 ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index); 510 if (ret == 0) { 511 spin_lock_irqsave(&pipe->irqlock, flags); 512 pipe->state = VSP1_PIPELINE_STOPPED; 513 spin_unlock_irqrestore(&pipe->irqlock, flags); 514 } 515 } else { 516 /* Otherwise just request a stop and wait. */ 517 spin_lock_irqsave(&pipe->irqlock, flags); 518 if (pipe->state == VSP1_PIPELINE_RUNNING) 519 pipe->state = VSP1_PIPELINE_STOPPING; 520 spin_unlock_irqrestore(&pipe->irqlock, flags); 521 522 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), 523 msecs_to_jiffies(500)); 524 ret = ret == 0 ? -ETIMEDOUT : 0; 525 } 526 527 list_for_each_entry(entity, &pipe->entities, list_pipe) { 528 if (entity->route && entity->route->reg) 529 vsp1_write(vsp1, entity->route->reg, 530 VI6_DPR_NODE_UNUSED); 531 } 532 533 if (pipe->hgo) 534 vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, 535 (7 << VI6_DPR_SMPPT_TGW_SHIFT) | 536 (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); 537 538 if (pipe->hgt) 539 vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, 540 (7 << VI6_DPR_SMPPT_TGW_SHIFT) | 541 (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); 542 543 vsp1_wpf_stop(pipe->output); 544 545 return ret; 546 } 547 548 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe) 549 { 550 unsigned int mask; 551 552 mask = ((1 << pipe->num_inputs) - 1) << 1; 553 if (!pipe->lif) 554 mask |= 1 << 0; 555 556 return pipe->buffers_ready == mask; 557 } 558 559 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe) 560 { 561 unsigned int flags; 562 563 if (pipe == NULL) 564 return; 565 566 /* 567 * If the DL commit raced with the frame end interrupt, the commit ends 568 * up being postponed by one frame. The returned flags tell whether the 569 * active frame was finished or postponed. 570 */ 571 flags = vsp1_dlm_irq_frame_end(pipe->output->dlm); 572 573 if (pipe->hgo) 574 vsp1_hgo_frame_end(pipe->hgo); 575 576 if (pipe->hgt) 577 vsp1_hgt_frame_end(pipe->hgt); 578 579 /* 580 * Regardless of frame completion we still need to notify the pipe 581 * frame_end to account for vblank events. 582 */ 583 if (pipe->frame_end) 584 pipe->frame_end(pipe, flags); 585 586 pipe->sequence++; 587 } 588 589 /* 590 * Propagate the alpha value through the pipeline. 591 * 592 * As the UDS has restricted scaling capabilities when the alpha component needs 593 * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha 594 * value. The UDS then outputs a fixed alpha value which needs to be programmed 595 * from the input RPF alpha. 596 */ 597 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, 598 struct vsp1_dl_body *dlb, unsigned int alpha) 599 { 600 if (!pipe->uds) 601 return; 602 603 /* 604 * The BRU and BRS background color has a fixed alpha value set to 255, 605 * the output alpha value is thus always equal to 255. 606 */ 607 if (pipe->uds_input->type == VSP1_ENTITY_BRU || 608 pipe->uds_input->type == VSP1_ENTITY_BRS) 609 alpha = 255; 610 611 vsp1_uds_set_alpha(pipe->uds, dlb, alpha); 612 } 613 614 /* ----------------------------------------------------------------------------- 615 * VSP1 Partition Algorithm support 616 */ 617 618 /* 619 * Propagate the partition calculations through the pipeline 620 * 621 * Work backwards through the pipe, allowing each entity to update the partition 622 * parameters based on its configuration, and the entity connected to its 623 * source. Each entity must produce the partition required for the previous 624 * entity in the pipeline. 625 */ 626 static void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe, 627 struct vsp1_partition *partition, 628 unsigned int index, 629 struct v4l2_rect *window) 630 { 631 struct vsp1_entity *entity; 632 633 list_for_each_entry_reverse(entity, &pipe->entities, list_pipe) { 634 if (entity->ops->partition) 635 entity->ops->partition(entity, entity->state, pipe, 636 partition, index, window); 637 } 638 } 639 640 /* 641 * vsp1_pipeline_calculate_partition - Calculate pipeline configuration for a 642 * partition 643 * 644 * @pipe: the pipeline 645 * @partition: partition that will hold the calculated values 646 * @div_size: pre-determined maximum partition division size 647 * @index: partition index 648 */ 649 void vsp1_pipeline_calculate_partition(struct vsp1_pipeline *pipe, 650 struct vsp1_partition *partition, 651 unsigned int div_size, 652 unsigned int index) 653 { 654 const struct v4l2_mbus_framefmt *format; 655 struct v4l2_rect window; 656 unsigned int modulus; 657 658 /* 659 * Partitions are computed on the size before rotation, use the format 660 * at the WPF sink. 661 */ 662 format = v4l2_subdev_state_get_format(pipe->output->entity.state, 663 RWPF_PAD_SINK); 664 665 /* Initialise the partition with sane starting conditions. */ 666 window.left = index * div_size; 667 window.width = div_size; 668 window.top = 0; 669 window.height = format->height; 670 671 modulus = format->width % div_size; 672 673 /* 674 * We need to prevent the last partition from being smaller than the 675 * *minimum* width of the hardware capabilities. 676 * 677 * If the modulus is less than half of the partition size, 678 * the penultimate partition is reduced to half, which is added 679 * to the final partition: |1234|1234|1234|12|341| 680 * to prevent this: |1234|1234|1234|1234|1|. 681 */ 682 if (modulus) { 683 /* 684 * pipe->partitions is 1 based, whilst index is a 0 based index. 685 * Normalise this locally. 686 */ 687 unsigned int partitions = pipe->partitions - 1; 688 689 if (modulus < div_size / 2) { 690 if (index == partitions - 1) { 691 /* Halve the penultimate partition. */ 692 window.width = div_size / 2; 693 } else if (index == partitions) { 694 /* Increase the final partition. */ 695 window.width = (div_size / 2) + modulus; 696 window.left -= div_size / 2; 697 } 698 } else if (index == partitions) { 699 window.width = modulus; 700 } 701 } 702 703 vsp1_pipeline_propagate_partition(pipe, partition, index, &window); 704 } 705