1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * vsp1_pipe.c -- R-Car VSP1 Pipeline 4 * 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 6 * 7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/list.h> 12 #include <linux/sched.h> 13 #include <linux/wait.h> 14 15 #include <media/media-entity.h> 16 #include <media/v4l2-subdev.h> 17 18 #include "vsp1.h" 19 #include "vsp1_brx.h" 20 #include "vsp1_dl.h" 21 #include "vsp1_entity.h" 22 #include "vsp1_hgo.h" 23 #include "vsp1_hgt.h" 24 #include "vsp1_pipe.h" 25 #include "vsp1_rwpf.h" 26 #include "vsp1_uds.h" 27 28 /* ----------------------------------------------------------------------------- 29 * Helper Functions 30 */ 31 32 static const struct vsp1_format_info vsp1_video_formats[] = { 33 { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32, 34 VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 35 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 36 1, { 8, 0, 0 }, false, false, 1, 1, false }, 37 { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32, 38 VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 39 VI6_RPF_DSWAP_P_WDS, 40 1, { 16, 0, 0 }, false, false, 1, 1, true }, 41 { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32, 42 VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 43 VI6_RPF_DSWAP_P_WDS, 44 1, { 16, 0, 0 }, false, false, 1, 1, false }, 45 { V4L2_PIX_FMT_RGBA444, MEDIA_BUS_FMT_ARGB8888_1X32, 46 VI6_FMT_RGBA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 47 VI6_RPF_DSWAP_P_WDS, 48 1, { 16, 0, 0 }, false, false, 1, 1, true }, 49 { V4L2_PIX_FMT_RGBX444, MEDIA_BUS_FMT_ARGB8888_1X32, 50 VI6_FMT_RGBX_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 51 VI6_RPF_DSWAP_P_WDS, 52 1, { 16, 0, 0 }, false, false, 1, 1, false }, 53 { V4L2_PIX_FMT_ABGR444, MEDIA_BUS_FMT_ARGB8888_1X32, 54 VI6_FMT_ABGR_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 55 VI6_RPF_DSWAP_P_WDS, 56 1, { 16, 0, 0 }, false, false, 1, 1, true }, 57 { V4L2_PIX_FMT_XBGR444, MEDIA_BUS_FMT_ARGB8888_1X32, 58 VI6_FMT_ABGR_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 59 VI6_RPF_DSWAP_P_WDS, 60 1, { 16, 0, 0 }, false, false, 1, 1, false }, 61 { V4L2_PIX_FMT_BGRA444, MEDIA_BUS_FMT_ARGB8888_1X32, 62 VI6_FMT_BGRA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 63 VI6_RPF_DSWAP_P_WDS, 64 1, { 16, 0, 0 }, false, false, 1, 1, true }, 65 { V4L2_PIX_FMT_BGRX444, MEDIA_BUS_FMT_ARGB8888_1X32, 66 VI6_FMT_BGRA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 67 VI6_RPF_DSWAP_P_WDS, 68 1, { 16, 0, 0 }, false, false, 1, 1, false }, 69 { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32, 70 VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 71 VI6_RPF_DSWAP_P_WDS, 72 1, { 16, 0, 0 }, false, false, 1, 1, true }, 73 { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32, 74 VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 75 VI6_RPF_DSWAP_P_WDS, 76 1, { 16, 0, 0 }, false, false, 1, 1, false }, 77 { V4L2_PIX_FMT_RGBA555, MEDIA_BUS_FMT_ARGB8888_1X32, 78 VI6_FMT_RGBA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 79 VI6_RPF_DSWAP_P_WDS, 80 1, { 16, 0, 0 }, false, false, 1, 1, true }, 81 { V4L2_PIX_FMT_RGBX555, MEDIA_BUS_FMT_ARGB8888_1X32, 82 VI6_FMT_RGBX_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 83 VI6_RPF_DSWAP_P_WDS, 84 1, { 16, 0, 0 }, false, false, 1, 1, false }, 85 { V4L2_PIX_FMT_ABGR555, MEDIA_BUS_FMT_ARGB8888_1X32, 86 VI6_FMT_ABGR_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 87 VI6_RPF_DSWAP_P_WDS, 88 1, { 16, 0, 0 }, false, false, 1, 1, true }, 89 { V4L2_PIX_FMT_XBGR555, MEDIA_BUS_FMT_ARGB8888_1X32, 90 VI6_FMT_ABGR_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 91 VI6_RPF_DSWAP_P_WDS, 92 1, { 16, 0, 0 }, false, false, 1, 1, false }, 93 { V4L2_PIX_FMT_BGRA555, MEDIA_BUS_FMT_ARGB8888_1X32, 94 VI6_FMT_BGRA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 95 VI6_RPF_DSWAP_P_WDS, 96 1, { 16, 0, 0 }, false, false, 1, 1, true }, 97 { V4L2_PIX_FMT_BGRX555, MEDIA_BUS_FMT_ARGB8888_1X32, 98 VI6_FMT_BGRA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 99 VI6_RPF_DSWAP_P_WDS, 100 1, { 16, 0, 0 }, false, false, 1, 1, false }, 101 { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32, 102 VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 103 VI6_RPF_DSWAP_P_WDS, 104 1, { 16, 0, 0 }, false, false, 1, 1, false }, 105 { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32, 106 VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 107 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 108 1, { 24, 0, 0 }, false, false, 1, 1, false }, 109 { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32, 110 VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 111 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 112 1, { 24, 0, 0 }, false, false, 1, 1, false }, 113 { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32, 114 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 115 1, { 32, 0, 0 }, false, false, 1, 1, true }, 116 { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32, 117 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 118 1, { 32, 0, 0 }, false, false, 1, 1, false }, 119 { V4L2_PIX_FMT_BGRA32, MEDIA_BUS_FMT_ARGB8888_1X32, 120 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 121 1, { 32, 0, 0 }, false, false, 1, 1, true }, 122 { V4L2_PIX_FMT_BGRX32, MEDIA_BUS_FMT_ARGB8888_1X32, 123 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 124 1, { 32, 0, 0 }, false, false, 1, 1, false }, 125 { V4L2_PIX_FMT_RGBA32, MEDIA_BUS_FMT_ARGB8888_1X32, 126 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 127 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 128 1, { 32, 0, 0 }, false, false, 1, 1, true }, 129 { V4L2_PIX_FMT_RGBX32, MEDIA_BUS_FMT_ARGB8888_1X32, 130 VI6_FMT_RGBA_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 131 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 132 1, { 32, 0, 0 }, false, false, 1, 1, false }, 133 { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32, 134 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 135 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 136 1, { 32, 0, 0 }, false, false, 1, 1, true }, 137 { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32, 138 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 139 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 140 1, { 32, 0, 0 }, false, false, 1, 1, false }, 141 { V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32, 142 VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 143 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 144 1, { 24, 0, 0 }, false, false, 1, 1, false }, 145 { V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32, 146 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 147 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 148 1, { 32, 0, 0 }, false, false, 1, 1, false }, 149 { V4L2_PIX_FMT_RGBX1010102, MEDIA_BUS_FMT_ARGB8888_1X32, 150 VI6_FMT_RGB10_RGB10A2_A2RGB10, 151 VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 152 1, { 32, 0, 0 }, false, false, 1, 1, false }, 153 { V4L2_PIX_FMT_RGBA1010102, MEDIA_BUS_FMT_ARGB8888_1X32, 154 VI6_FMT_RGB10_RGB10A2_A2RGB10, 155 VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 156 1, { 32, 0, 0 }, false, false, 1, 1, false }, 157 { V4L2_PIX_FMT_ARGB2101010, MEDIA_BUS_FMT_ARGB8888_1X32, 158 VI6_FMT_RGB10_RGB10A2_A2RGB10, 159 VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 160 1, { 32, 0, 0 }, false, false, 1, 1, false }, 161 { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32, 162 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 163 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 164 1, { 16, 0, 0 }, false, false, 2, 1, false }, 165 { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32, 166 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 167 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 168 1, { 16, 0, 0 }, false, true, 2, 1, false }, 169 { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32, 170 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 171 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 172 1, { 16, 0, 0 }, true, false, 2, 1, false }, 173 { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32, 174 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 175 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 176 1, { 16, 0, 0 }, true, true, 2, 1, false }, 177 { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32, 178 VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 179 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 180 2, { 8, 16, 0 }, false, false, 2, 2, false }, 181 { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32, 182 VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 183 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 184 2, { 8, 16, 0 }, false, true, 2, 2, false }, 185 { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32, 186 VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 187 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 188 2, { 8, 16, 0 }, false, false, 2, 1, false }, 189 { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32, 190 VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 191 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 192 2, { 8, 16, 0 }, false, true, 2, 1, false }, 193 { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32, 194 VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 195 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 196 3, { 8, 8, 8 }, false, false, 2, 2, false }, 197 { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32, 198 VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 199 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 200 3, { 8, 8, 8 }, false, true, 2, 2, false }, 201 { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32, 202 VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 203 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 204 3, { 8, 8, 8 }, false, false, 2, 1, false }, 205 { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32, 206 VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 207 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 208 3, { 8, 8, 8 }, false, true, 2, 1, false }, 209 { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32, 210 VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 211 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 212 3, { 8, 8, 8 }, false, false, 1, 1, false }, 213 { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32, 214 VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | 215 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, 216 3, { 8, 8, 8 }, false, true, 1, 1, false }, 217 { V4L2_PIX_FMT_Y210, MEDIA_BUS_FMT_AYUV8_1X32, 218 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 219 1, { 32, 0, 0 }, false, false, 2, 1, false }, 220 { V4L2_PIX_FMT_Y212, MEDIA_BUS_FMT_AYUV8_1X32, 221 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, 222 1, { 32, 0, 0 }, false, false, 2, 1, false }, 223 }; 224 225 /** 226 * vsp1_get_format_info - Retrieve format information for a 4CC 227 * @vsp1: the VSP1 device 228 * @fourcc: the format 4CC 229 * 230 * Return a pointer to the format information structure corresponding to the 231 * given V4L2 format 4CC, or NULL if no corresponding format can be found. 232 */ 233 const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1, 234 u32 fourcc) 235 { 236 unsigned int i; 237 238 /* Special case, the VYUY and HSV formats are supported on Gen2 only. */ 239 if (vsp1->info->gen != 2) { 240 switch (fourcc) { 241 case V4L2_PIX_FMT_VYUY: 242 case V4L2_PIX_FMT_HSV24: 243 case V4L2_PIX_FMT_HSV32: 244 return NULL; 245 } 246 } 247 248 for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) { 249 const struct vsp1_format_info *info = &vsp1_video_formats[i]; 250 251 if (info->fourcc == fourcc) 252 return info; 253 } 254 255 return NULL; 256 } 257 258 /* ----------------------------------------------------------------------------- 259 * Pipeline Management 260 */ 261 262 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) 263 { 264 struct vsp1_entity *entity; 265 unsigned int i; 266 267 if (pipe->brx) { 268 struct vsp1_brx *brx = to_brx(&pipe->brx->subdev); 269 270 for (i = 0; i < ARRAY_SIZE(brx->inputs); ++i) 271 brx->inputs[i].rpf = NULL; 272 } 273 274 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) 275 pipe->inputs[i] = NULL; 276 277 pipe->output = NULL; 278 279 list_for_each_entry(entity, &pipe->entities, list_pipe) 280 entity->pipe = NULL; 281 282 INIT_LIST_HEAD(&pipe->entities); 283 pipe->state = VSP1_PIPELINE_STOPPED; 284 pipe->buffers_ready = 0; 285 pipe->num_inputs = 0; 286 pipe->brx = NULL; 287 pipe->hgo = NULL; 288 pipe->hgt = NULL; 289 pipe->lif = NULL; 290 pipe->uds = NULL; 291 } 292 293 void vsp1_pipeline_init(struct vsp1_pipeline *pipe) 294 { 295 mutex_init(&pipe->lock); 296 spin_lock_init(&pipe->irqlock); 297 init_waitqueue_head(&pipe->wq); 298 kref_init(&pipe->kref); 299 300 INIT_LIST_HEAD(&pipe->entities); 301 pipe->state = VSP1_PIPELINE_STOPPED; 302 } 303 304 void __vsp1_pipeline_dump(struct _ddebug *dbg, struct vsp1_pipeline *pipe, 305 const char *msg) 306 { 307 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; 308 struct vsp1_entity *entity; 309 bool first = true; 310 311 printk(KERN_DEBUG "%s: %s: pipe: ", dev_name(vsp1->dev), msg); 312 313 list_for_each_entry(entity, &pipe->entities, list_pipe) { 314 const char *name; 315 316 name = strchrnul(entity->subdev.name, ' '); 317 name = name ? name + 1 : entity->subdev.name; 318 319 pr_cont("%s%s", first ? "" : ", ", name); 320 first = false; 321 } 322 323 pr_cont("\n"); 324 } 325 326 /* Must be called with the pipe irqlock held. */ 327 void vsp1_pipeline_run(struct vsp1_pipeline *pipe) 328 { 329 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; 330 331 if (pipe->state == VSP1_PIPELINE_STOPPED) { 332 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index), 333 VI6_CMD_STRCMD); 334 pipe->state = VSP1_PIPELINE_RUNNING; 335 } 336 337 pipe->buffers_ready = 0; 338 } 339 340 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) 341 { 342 unsigned long flags; 343 bool stopped; 344 345 spin_lock_irqsave(&pipe->irqlock, flags); 346 stopped = pipe->state == VSP1_PIPELINE_STOPPED; 347 spin_unlock_irqrestore(&pipe->irqlock, flags); 348 349 return stopped; 350 } 351 352 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) 353 { 354 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; 355 struct vsp1_entity *entity; 356 unsigned long flags; 357 int ret; 358 359 if (pipe->lif) { 360 /* 361 * When using display lists in continuous frame mode the only 362 * way to stop the pipeline is to reset the hardware. 363 */ 364 ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index); 365 if (ret == 0) { 366 spin_lock_irqsave(&pipe->irqlock, flags); 367 pipe->state = VSP1_PIPELINE_STOPPED; 368 spin_unlock_irqrestore(&pipe->irqlock, flags); 369 } 370 } else { 371 /* Otherwise just request a stop and wait. */ 372 spin_lock_irqsave(&pipe->irqlock, flags); 373 if (pipe->state == VSP1_PIPELINE_RUNNING) 374 pipe->state = VSP1_PIPELINE_STOPPING; 375 spin_unlock_irqrestore(&pipe->irqlock, flags); 376 377 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), 378 msecs_to_jiffies(500)); 379 ret = ret == 0 ? -ETIMEDOUT : 0; 380 } 381 382 list_for_each_entry(entity, &pipe->entities, list_pipe) { 383 if (entity->route && entity->route->reg) 384 vsp1_write(vsp1, entity->route->reg, 385 VI6_DPR_NODE_UNUSED); 386 } 387 388 if (pipe->hgo) 389 vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, 390 (7 << VI6_DPR_SMPPT_TGW_SHIFT) | 391 (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); 392 393 if (pipe->hgt) 394 vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, 395 (7 << VI6_DPR_SMPPT_TGW_SHIFT) | 396 (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); 397 398 vsp1_wpf_stop(pipe->output); 399 400 return ret; 401 } 402 403 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe) 404 { 405 unsigned int mask; 406 407 mask = ((1 << pipe->num_inputs) - 1) << 1; 408 if (!pipe->lif) 409 mask |= 1 << 0; 410 411 return pipe->buffers_ready == mask; 412 } 413 414 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe) 415 { 416 unsigned int flags; 417 418 if (pipe == NULL) 419 return; 420 421 /* 422 * If the DL commit raced with the frame end interrupt, the commit ends 423 * up being postponed by one frame. The returned flags tell whether the 424 * active frame was finished or postponed. 425 */ 426 flags = vsp1_dlm_irq_frame_end(pipe->output->dlm); 427 428 if (pipe->hgo) 429 vsp1_hgo_frame_end(pipe->hgo); 430 431 if (pipe->hgt) 432 vsp1_hgt_frame_end(pipe->hgt); 433 434 /* 435 * Regardless of frame completion we still need to notify the pipe 436 * frame_end to account for vblank events. 437 */ 438 if (pipe->frame_end) 439 pipe->frame_end(pipe, flags); 440 441 pipe->sequence++; 442 } 443 444 /* 445 * Propagate the alpha value through the pipeline. 446 * 447 * As the UDS has restricted scaling capabilities when the alpha component needs 448 * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha 449 * value. The UDS then outputs a fixed alpha value which needs to be programmed 450 * from the input RPF alpha. 451 */ 452 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, 453 struct vsp1_dl_body *dlb, unsigned int alpha) 454 { 455 if (!pipe->uds) 456 return; 457 458 /* 459 * The BRU and BRS background color has a fixed alpha value set to 255, 460 * the output alpha value is thus always equal to 255. 461 */ 462 if (pipe->uds_input->type == VSP1_ENTITY_BRU || 463 pipe->uds_input->type == VSP1_ENTITY_BRS) 464 alpha = 255; 465 466 vsp1_uds_set_alpha(pipe->uds, dlb, alpha); 467 } 468 469 /* ----------------------------------------------------------------------------- 470 * VSP1 Partition Algorithm support 471 */ 472 473 /* 474 * Propagate the partition calculations through the pipeline 475 * 476 * Work backwards through the pipe, allowing each entity to update the partition 477 * parameters based on its configuration, and the entity connected to its 478 * source. Each entity must produce the partition required for the previous 479 * entity in the pipeline. 480 */ 481 static void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe, 482 struct vsp1_partition *partition, 483 unsigned int index, 484 struct v4l2_rect *window) 485 { 486 struct vsp1_entity *entity; 487 488 list_for_each_entry_reverse(entity, &pipe->entities, list_pipe) { 489 if (entity->ops->partition) 490 entity->ops->partition(entity, entity->state, pipe, 491 partition, index, window); 492 } 493 } 494 495 /* 496 * vsp1_pipeline_calculate_partition - Calculate pipeline configuration for a 497 * partition 498 * 499 * @pipe: the pipeline 500 * @partition: partition that will hold the calculated values 501 * @div_size: pre-determined maximum partition division size 502 * @index: partition index 503 */ 504 void vsp1_pipeline_calculate_partition(struct vsp1_pipeline *pipe, 505 struct vsp1_partition *partition, 506 unsigned int div_size, 507 unsigned int index) 508 { 509 const struct v4l2_mbus_framefmt *format; 510 struct v4l2_rect window; 511 unsigned int modulus; 512 513 /* 514 * Partitions are computed on the size before rotation, use the format 515 * at the WPF sink. 516 */ 517 format = v4l2_subdev_state_get_format(pipe->output->entity.state, 518 RWPF_PAD_SINK); 519 520 /* Initialise the partition with sane starting conditions. */ 521 window.left = index * div_size; 522 window.width = div_size; 523 window.top = 0; 524 window.height = format->height; 525 526 modulus = format->width % div_size; 527 528 /* 529 * We need to prevent the last partition from being smaller than the 530 * *minimum* width of the hardware capabilities. 531 * 532 * If the modulus is less than half of the partition size, 533 * the penultimate partition is reduced to half, which is added 534 * to the final partition: |1234|1234|1234|12|341| 535 * to prevent this: |1234|1234|1234|1234|1|. 536 */ 537 if (modulus) { 538 /* 539 * pipe->partitions is 1 based, whilst index is a 0 based index. 540 * Normalise this locally. 541 */ 542 unsigned int partitions = pipe->partitions - 1; 543 544 if (modulus < div_size / 2) { 545 if (index == partitions - 1) { 546 /* Halve the penultimate partition. */ 547 window.width = div_size / 2; 548 } else if (index == partitions) { 549 /* Increase the final partition. */ 550 window.width = (div_size / 2) + modulus; 551 window.left -= div_size / 2; 552 } 553 } else if (index == partitions) { 554 window.width = modulus; 555 } 556 } 557 558 vsp1_pipeline_propagate_partition(pipe, partition, index, &window); 559 } 560