1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Renesas RZ/G2L CRU 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 * 7 * Based on Renesas R-Car VIN 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 * Copyright (C) 2011-2013 Renesas Solutions Corp. 10 * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com> 11 * Copyright (C) 2008 Magnus Damm 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/pm_runtime.h> 17 18 #include <media/mipi-csi2.h> 19 #include <media/v4l2-ioctl.h> 20 #include <media/videobuf2-dma-contig.h> 21 22 #include "rzg2l-cru.h" 23 #include "rzg2l-cru-regs.h" 24 25 #define RZG2L_TIMEOUT_MS 100 26 #define RZG2L_RETRIES 10 27 28 #define RZG2L_CRU_DEFAULT_FORMAT V4L2_PIX_FMT_UYVY 29 #define RZG2L_CRU_DEFAULT_WIDTH RZG2L_CRU_MIN_INPUT_WIDTH 30 #define RZG2L_CRU_DEFAULT_HEIGHT RZG2L_CRU_MIN_INPUT_HEIGHT 31 #define RZG2L_CRU_DEFAULT_FIELD V4L2_FIELD_NONE 32 #define RZG2L_CRU_DEFAULT_COLORSPACE V4L2_COLORSPACE_SRGB 33 34 struct rzg2l_cru_buffer { 35 struct vb2_v4l2_buffer vb; 36 struct list_head list; 37 }; 38 39 #define to_buf_list(vb2_buffer) \ 40 (&container_of(vb2_buffer, struct rzg2l_cru_buffer, vb)->list) 41 42 /* ----------------------------------------------------------------------------- 43 * DMA operations 44 */ 45 static void rzg2l_cru_write(struct rzg2l_cru_dev *cru, u32 offset, u32 value) 46 { 47 iowrite32(value, cru->base + offset); 48 } 49 50 static u32 rzg2l_cru_read(struct rzg2l_cru_dev *cru, u32 offset) 51 { 52 return ioread32(cru->base + offset); 53 } 54 55 /* Need to hold qlock before calling */ 56 static void return_unused_buffers(struct rzg2l_cru_dev *cru, 57 enum vb2_buffer_state state) 58 { 59 struct rzg2l_cru_buffer *buf, *node; 60 unsigned long flags; 61 unsigned int i; 62 63 spin_lock_irqsave(&cru->qlock, flags); 64 for (i = 0; i < cru->num_buf; i++) { 65 if (cru->queue_buf[i]) { 66 vb2_buffer_done(&cru->queue_buf[i]->vb2_buf, 67 state); 68 cru->queue_buf[i] = NULL; 69 } 70 } 71 72 list_for_each_entry_safe(buf, node, &cru->buf_list, list) { 73 vb2_buffer_done(&buf->vb.vb2_buf, state); 74 list_del(&buf->list); 75 } 76 spin_unlock_irqrestore(&cru->qlock, flags); 77 } 78 79 static int rzg2l_cru_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, 80 unsigned int *nplanes, unsigned int sizes[], 81 struct device *alloc_devs[]) 82 { 83 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); 84 85 /* Make sure the image size is large enough. */ 86 if (*nplanes) 87 return sizes[0] < cru->format.sizeimage ? -EINVAL : 0; 88 89 *nplanes = 1; 90 sizes[0] = cru->format.sizeimage; 91 92 return 0; 93 }; 94 95 static int rzg2l_cru_buffer_prepare(struct vb2_buffer *vb) 96 { 97 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vb->vb2_queue); 98 unsigned long size = cru->format.sizeimage; 99 100 if (vb2_plane_size(vb, 0) < size) { 101 dev_err(cru->dev, "buffer too small (%lu < %lu)\n", 102 vb2_plane_size(vb, 0), size); 103 return -EINVAL; 104 } 105 106 vb2_set_plane_payload(vb, 0, size); 107 108 return 0; 109 } 110 111 static void rzg2l_cru_buffer_queue(struct vb2_buffer *vb) 112 { 113 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 114 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vb->vb2_queue); 115 unsigned long flags; 116 117 spin_lock_irqsave(&cru->qlock, flags); 118 119 list_add_tail(to_buf_list(vbuf), &cru->buf_list); 120 121 spin_unlock_irqrestore(&cru->qlock, flags); 122 } 123 124 static void rzg2l_cru_set_slot_addr(struct rzg2l_cru_dev *cru, 125 int slot, dma_addr_t addr) 126 { 127 /* 128 * The address needs to be 512 bytes aligned. Driver should never accept 129 * settings that do not satisfy this in the first place... 130 */ 131 if (WARN_ON((addr) & RZG2L_CRU_HW_BUFFER_MASK)) 132 return; 133 134 /* Currently, we just use the buffer in 32 bits address */ 135 rzg2l_cru_write(cru, AMnMBxADDRL(slot), addr); 136 rzg2l_cru_write(cru, AMnMBxADDRH(slot), 0); 137 } 138 139 /* 140 * Moves a buffer from the queue to the HW slot. If no buffer is 141 * available use the scratch buffer. The scratch buffer is never 142 * returned to userspace, its only function is to enable the capture 143 * loop to keep running. 144 */ 145 static void rzg2l_cru_fill_hw_slot(struct rzg2l_cru_dev *cru, int slot) 146 { 147 struct vb2_v4l2_buffer *vbuf; 148 struct rzg2l_cru_buffer *buf; 149 dma_addr_t phys_addr; 150 151 /* A already populated slot shall never be overwritten. */ 152 if (WARN_ON(cru->queue_buf[slot])) 153 return; 154 155 dev_dbg(cru->dev, "Filling HW slot: %d\n", slot); 156 157 if (list_empty(&cru->buf_list)) { 158 cru->queue_buf[slot] = NULL; 159 phys_addr = cru->scratch_phys; 160 } else { 161 /* Keep track of buffer we give to HW */ 162 buf = list_entry(cru->buf_list.next, 163 struct rzg2l_cru_buffer, list); 164 vbuf = &buf->vb; 165 list_del_init(to_buf_list(vbuf)); 166 cru->queue_buf[slot] = vbuf; 167 168 /* Setup DMA */ 169 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); 170 } 171 172 rzg2l_cru_set_slot_addr(cru, slot, phys_addr); 173 } 174 175 static void rzg2l_cru_initialize_axi(struct rzg2l_cru_dev *cru) 176 { 177 unsigned int slot; 178 u32 amnaxiattr; 179 180 /* 181 * Set image data memory banks. 182 * Currently, we will use maximum address. 183 */ 184 rzg2l_cru_write(cru, AMnMBVALID, AMnMBVALID_MBVALID(cru->num_buf - 1)); 185 186 for (slot = 0; slot < cru->num_buf; slot++) 187 rzg2l_cru_fill_hw_slot(cru, slot); 188 189 /* Set AXI burst max length to recommended setting */ 190 amnaxiattr = rzg2l_cru_read(cru, AMnAXIATTR) & ~AMnAXIATTR_AXILEN_MASK; 191 amnaxiattr |= AMnAXIATTR_AXILEN; 192 rzg2l_cru_write(cru, AMnAXIATTR, amnaxiattr); 193 } 194 195 static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, 196 const struct rzg2l_cru_ip_format *ip_fmt, 197 u8 csi_vc) 198 { 199 u32 icnmc = ICnMC_INF(ip_fmt->datatype); 200 201 icnmc |= (rzg2l_cru_read(cru, ICnMC) & ~ICnMC_INF_MASK); 202 203 /* Set virtual channel CSI2 */ 204 icnmc |= ICnMC_VCSEL(csi_vc); 205 206 rzg2l_cru_write(cru, ICnMC, icnmc); 207 } 208 209 static int rzg2l_cru_initialize_image_conv(struct rzg2l_cru_dev *cru, 210 struct v4l2_mbus_framefmt *ip_sd_fmt, 211 u8 csi_vc) 212 { 213 const struct rzg2l_cru_ip_format *cru_video_fmt; 214 const struct rzg2l_cru_ip_format *cru_ip_fmt; 215 216 cru_ip_fmt = rzg2l_cru_ip_code_to_fmt(ip_sd_fmt->code); 217 rzg2l_cru_csi2_setup(cru, cru_ip_fmt, csi_vc); 218 219 /* Output format */ 220 cru_video_fmt = rzg2l_cru_ip_format_to_fmt(cru->format.pixelformat); 221 if (!cru_video_fmt) { 222 dev_err(cru->dev, "Invalid pixelformat (0x%x)\n", 223 cru->format.pixelformat); 224 return -EINVAL; 225 } 226 227 /* If input and output use same colorspace, do bypass mode */ 228 if (cru_ip_fmt->yuv == cru_video_fmt->yuv) 229 rzg2l_cru_write(cru, ICnMC, 230 rzg2l_cru_read(cru, ICnMC) | ICnMC_CSCTHR); 231 else 232 rzg2l_cru_write(cru, ICnMC, 233 rzg2l_cru_read(cru, ICnMC) & (~ICnMC_CSCTHR)); 234 235 /* Set output data format */ 236 rzg2l_cru_write(cru, ICnDMR, cru_video_fmt->icndmr); 237 238 return 0; 239 } 240 241 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru) 242 { 243 u32 amnfifopntr, amnfifopntr_w, amnfifopntr_r_y; 244 unsigned int retries = 0; 245 unsigned long flags; 246 u32 icnms; 247 248 spin_lock_irqsave(&cru->qlock, flags); 249 250 /* Disable and clear the interrupt */ 251 rzg2l_cru_write(cru, CRUnIE, 0); 252 rzg2l_cru_write(cru, CRUnINTS, 0x001F0F0F); 253 254 /* Stop the operation of image conversion */ 255 rzg2l_cru_write(cru, ICnEN, 0); 256 257 /* Wait for streaming to stop */ 258 while ((rzg2l_cru_read(cru, ICnMS) & ICnMS_IA) && retries++ < RZG2L_RETRIES) { 259 spin_unlock_irqrestore(&cru->qlock, flags); 260 msleep(RZG2L_TIMEOUT_MS); 261 spin_lock_irqsave(&cru->qlock, flags); 262 } 263 264 icnms = rzg2l_cru_read(cru, ICnMS) & ICnMS_IA; 265 if (icnms) 266 dev_err(cru->dev, "Failed stop HW, something is seriously broken\n"); 267 268 cru->state = RZG2L_CRU_DMA_STOPPED; 269 270 /* Wait until the FIFO becomes empty */ 271 for (retries = 5; retries > 0; retries--) { 272 amnfifopntr = rzg2l_cru_read(cru, AMnFIFOPNTR); 273 274 amnfifopntr_w = amnfifopntr & AMnFIFOPNTR_FIFOWPNTR; 275 amnfifopntr_r_y = 276 (amnfifopntr & AMnFIFOPNTR_FIFORPNTR_Y) >> 16; 277 if (amnfifopntr_w == amnfifopntr_r_y) 278 break; 279 280 usleep_range(10, 20); 281 } 282 283 /* Notify that FIFO is not empty here */ 284 if (!retries) 285 dev_err(cru->dev, "Failed to empty FIFO\n"); 286 287 /* Stop AXI bus */ 288 rzg2l_cru_write(cru, AMnAXISTP, AMnAXISTP_AXI_STOP); 289 290 /* Wait until the AXI bus stop */ 291 for (retries = 5; retries > 0; retries--) { 292 if (rzg2l_cru_read(cru, AMnAXISTPACK) & 293 AMnAXISTPACK_AXI_STOP_ACK) 294 break; 295 296 usleep_range(10, 20); 297 } 298 299 /* Notify that AXI bus can not stop here */ 300 if (!retries) 301 dev_err(cru->dev, "Failed to stop AXI bus\n"); 302 303 /* Cancel the AXI bus stop request */ 304 rzg2l_cru_write(cru, AMnAXISTP, 0); 305 306 /* Reset the CRU (AXI-master) */ 307 reset_control_assert(cru->aresetn); 308 309 /* Resets the image processing module */ 310 rzg2l_cru_write(cru, CRUnRST, 0); 311 312 spin_unlock_irqrestore(&cru->qlock, flags); 313 } 314 315 static int rzg2l_cru_get_virtual_channel(struct rzg2l_cru_dev *cru) 316 { 317 struct v4l2_mbus_frame_desc fd = { }; 318 struct media_pad *remote_pad; 319 int ret; 320 321 remote_pad = media_pad_remote_pad_unique(&cru->ip.pads[RZG2L_CRU_IP_SINK]); 322 ret = v4l2_subdev_call(cru->ip.remote, pad, get_frame_desc, remote_pad->index, &fd); 323 if (ret < 0 && ret != -ENOIOCTLCMD) { 324 dev_err(cru->dev, "get_frame_desc failed on IP remote subdev\n"); 325 return ret; 326 } 327 /* If remote subdev does not implement .get_frame_desc default to VC0. */ 328 if (ret == -ENOIOCTLCMD) 329 return 0; 330 331 if (fd.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { 332 dev_err(cru->dev, "get_frame_desc returned invalid bus type %d\n", fd.type); 333 return -EINVAL; 334 } 335 336 if (!fd.num_entries) { 337 dev_err(cru->dev, "get_frame_desc returned zero entries\n"); 338 return -EINVAL; 339 } 340 341 return fd.entry[0].bus.csi2.vc; 342 } 343 344 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru) 345 { 346 struct v4l2_mbus_framefmt *fmt = rzg2l_cru_ip_get_src_fmt(cru); 347 unsigned long flags; 348 u8 csi_vc; 349 int ret; 350 351 ret = rzg2l_cru_get_virtual_channel(cru); 352 if (ret < 0) 353 return ret; 354 csi_vc = ret; 355 356 spin_lock_irqsave(&cru->qlock, flags); 357 358 /* Select a video input */ 359 rzg2l_cru_write(cru, CRUnCTRL, CRUnCTRL_VINSEL(0)); 360 361 /* Cancel the software reset for image processing block */ 362 rzg2l_cru_write(cru, CRUnRST, CRUnRST_VRESETN); 363 364 /* Disable and clear the interrupt before using */ 365 rzg2l_cru_write(cru, CRUnIE, 0); 366 rzg2l_cru_write(cru, CRUnINTS, 0x001f000f); 367 368 /* Initialize the AXI master */ 369 rzg2l_cru_initialize_axi(cru); 370 371 /* Initialize image convert */ 372 ret = rzg2l_cru_initialize_image_conv(cru, fmt, csi_vc); 373 if (ret) { 374 spin_unlock_irqrestore(&cru->qlock, flags); 375 return ret; 376 } 377 378 /* Enable interrupt */ 379 rzg2l_cru_write(cru, CRUnIE, CRUnIE_EFE); 380 381 /* Enable image processing reception */ 382 rzg2l_cru_write(cru, ICnEN, ICnEN_ICEN); 383 384 spin_unlock_irqrestore(&cru->qlock, flags); 385 386 return 0; 387 } 388 389 static int rzg2l_cru_set_stream(struct rzg2l_cru_dev *cru, int on) 390 { 391 struct media_pipeline *pipe; 392 struct v4l2_subdev *sd; 393 struct media_pad *pad; 394 int ret; 395 396 pad = media_pad_remote_pad_first(&cru->pad); 397 if (!pad) 398 return -EPIPE; 399 400 sd = media_entity_to_v4l2_subdev(pad->entity); 401 402 if (!on) { 403 int stream_off_ret = 0; 404 405 ret = v4l2_subdev_call(sd, video, s_stream, 0); 406 if (ret) 407 stream_off_ret = ret; 408 409 ret = v4l2_subdev_call(sd, video, post_streamoff); 410 if (ret == -ENOIOCTLCMD) 411 ret = 0; 412 if (ret && !stream_off_ret) 413 stream_off_ret = ret; 414 415 video_device_pipeline_stop(&cru->vdev); 416 417 return stream_off_ret; 418 } 419 420 pipe = media_entity_pipeline(&sd->entity) ? : &cru->vdev.pipe; 421 ret = video_device_pipeline_start(&cru->vdev, pipe); 422 if (ret) 423 return ret; 424 425 ret = v4l2_subdev_call(sd, video, pre_streamon, 0); 426 if (ret && ret != -ENOIOCTLCMD) 427 goto pipe_line_stop; 428 429 ret = v4l2_subdev_call(sd, video, s_stream, 1); 430 if (ret && ret != -ENOIOCTLCMD) 431 goto err_s_stream; 432 433 return 0; 434 435 err_s_stream: 436 v4l2_subdev_call(sd, video, post_streamoff); 437 438 pipe_line_stop: 439 video_device_pipeline_stop(&cru->vdev); 440 441 return ret; 442 } 443 444 static void rzg2l_cru_stop_streaming(struct rzg2l_cru_dev *cru) 445 { 446 cru->state = RZG2L_CRU_DMA_STOPPING; 447 448 rzg2l_cru_set_stream(cru, 0); 449 } 450 451 irqreturn_t rzg2l_cru_irq(int irq, void *data) 452 { 453 struct rzg2l_cru_dev *cru = data; 454 unsigned int handled = 0; 455 unsigned long flags; 456 u32 irq_status; 457 u32 amnmbs; 458 int slot; 459 460 spin_lock_irqsave(&cru->qlock, flags); 461 462 irq_status = rzg2l_cru_read(cru, CRUnINTS); 463 if (!irq_status) 464 goto done; 465 466 handled = 1; 467 468 rzg2l_cru_write(cru, CRUnINTS, rzg2l_cru_read(cru, CRUnINTS)); 469 470 /* Nothing to do if capture status is 'RZG2L_CRU_DMA_STOPPED' */ 471 if (cru->state == RZG2L_CRU_DMA_STOPPED) { 472 dev_dbg(cru->dev, "IRQ while state stopped\n"); 473 goto done; 474 } 475 476 /* Increase stop retries if capture status is 'RZG2L_CRU_DMA_STOPPING' */ 477 if (cru->state == RZG2L_CRU_DMA_STOPPING) { 478 if (irq_status & CRUnINTS_SFS) 479 dev_dbg(cru->dev, "IRQ while state stopping\n"); 480 goto done; 481 } 482 483 /* Prepare for capture and update state */ 484 amnmbs = rzg2l_cru_read(cru, AMnMBS); 485 slot = amnmbs & AMnMBS_MBSTS; 486 487 /* 488 * AMnMBS.MBSTS indicates the destination of Memory Bank (MB). 489 * Recalculate to get the current transfer complete MB. 490 */ 491 if (slot == 0) 492 slot = cru->num_buf - 1; 493 else 494 slot--; 495 496 /* 497 * To hand buffers back in a known order to userspace start 498 * to capture first from slot 0. 499 */ 500 if (cru->state == RZG2L_CRU_DMA_STARTING) { 501 if (slot != 0) { 502 dev_dbg(cru->dev, "Starting sync slot: %d\n", slot); 503 goto done; 504 } 505 506 dev_dbg(cru->dev, "Capture start synced!\n"); 507 cru->state = RZG2L_CRU_DMA_RUNNING; 508 } 509 510 /* Capture frame */ 511 if (cru->queue_buf[slot]) { 512 cru->queue_buf[slot]->field = cru->format.field; 513 cru->queue_buf[slot]->sequence = cru->sequence; 514 cru->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns(); 515 vb2_buffer_done(&cru->queue_buf[slot]->vb2_buf, 516 VB2_BUF_STATE_DONE); 517 cru->queue_buf[slot] = NULL; 518 } else { 519 /* Scratch buffer was used, dropping frame. */ 520 dev_dbg(cru->dev, "Dropping frame %u\n", cru->sequence); 521 } 522 523 cru->sequence++; 524 525 /* Prepare for next frame */ 526 rzg2l_cru_fill_hw_slot(cru, slot); 527 528 done: 529 spin_unlock_irqrestore(&cru->qlock, flags); 530 531 return IRQ_RETVAL(handled); 532 } 533 534 static int rzg2l_cru_start_streaming_vq(struct vb2_queue *vq, unsigned int count) 535 { 536 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); 537 int ret; 538 539 ret = pm_runtime_resume_and_get(cru->dev); 540 if (ret) 541 return ret; 542 543 ret = clk_prepare_enable(cru->vclk); 544 if (ret) 545 goto err_pm_put; 546 547 /* Release reset state */ 548 ret = reset_control_deassert(cru->aresetn); 549 if (ret) { 550 dev_err(cru->dev, "failed to deassert aresetn\n"); 551 goto err_vclk_disable; 552 } 553 554 ret = reset_control_deassert(cru->presetn); 555 if (ret) { 556 reset_control_assert(cru->aresetn); 557 dev_err(cru->dev, "failed to deassert presetn\n"); 558 goto assert_aresetn; 559 } 560 561 /* Allocate scratch buffer. */ 562 cru->scratch = dma_alloc_coherent(cru->dev, cru->format.sizeimage, 563 &cru->scratch_phys, GFP_KERNEL); 564 if (!cru->scratch) { 565 return_unused_buffers(cru, VB2_BUF_STATE_QUEUED); 566 dev_err(cru->dev, "Failed to allocate scratch buffer\n"); 567 ret = -ENOMEM; 568 goto assert_presetn; 569 } 570 571 cru->sequence = 0; 572 573 ret = rzg2l_cru_set_stream(cru, 1); 574 if (ret) { 575 return_unused_buffers(cru, VB2_BUF_STATE_QUEUED); 576 goto out; 577 } 578 579 cru->state = RZG2L_CRU_DMA_STARTING; 580 dev_dbg(cru->dev, "Starting to capture\n"); 581 return 0; 582 583 out: 584 if (ret) 585 dma_free_coherent(cru->dev, cru->format.sizeimage, cru->scratch, 586 cru->scratch_phys); 587 assert_presetn: 588 reset_control_assert(cru->presetn); 589 590 assert_aresetn: 591 reset_control_assert(cru->aresetn); 592 593 err_vclk_disable: 594 clk_disable_unprepare(cru->vclk); 595 596 err_pm_put: 597 pm_runtime_put_sync(cru->dev); 598 599 return ret; 600 } 601 602 static void rzg2l_cru_stop_streaming_vq(struct vb2_queue *vq) 603 { 604 struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); 605 606 rzg2l_cru_stop_streaming(cru); 607 608 /* Free scratch buffer */ 609 dma_free_coherent(cru->dev, cru->format.sizeimage, 610 cru->scratch, cru->scratch_phys); 611 612 return_unused_buffers(cru, VB2_BUF_STATE_ERROR); 613 614 reset_control_assert(cru->presetn); 615 clk_disable_unprepare(cru->vclk); 616 pm_runtime_put_sync(cru->dev); 617 } 618 619 static const struct vb2_ops rzg2l_cru_qops = { 620 .queue_setup = rzg2l_cru_queue_setup, 621 .buf_prepare = rzg2l_cru_buffer_prepare, 622 .buf_queue = rzg2l_cru_buffer_queue, 623 .start_streaming = rzg2l_cru_start_streaming_vq, 624 .stop_streaming = rzg2l_cru_stop_streaming_vq, 625 }; 626 627 void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru) 628 { 629 mutex_destroy(&cru->lock); 630 631 v4l2_device_unregister(&cru->v4l2_dev); 632 vb2_queue_release(&cru->queue); 633 } 634 635 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru) 636 { 637 struct vb2_queue *q = &cru->queue; 638 unsigned int i; 639 int ret; 640 641 /* Initialize the top-level structure */ 642 ret = v4l2_device_register(cru->dev, &cru->v4l2_dev); 643 if (ret) 644 return ret; 645 646 mutex_init(&cru->lock); 647 INIT_LIST_HEAD(&cru->buf_list); 648 649 spin_lock_init(&cru->qlock); 650 651 cru->state = RZG2L_CRU_DMA_STOPPED; 652 653 for (i = 0; i < RZG2L_CRU_HW_BUFFER_MAX; i++) 654 cru->queue_buf[i] = NULL; 655 656 /* buffer queue */ 657 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 658 q->io_modes = VB2_MMAP | VB2_DMABUF; 659 q->lock = &cru->lock; 660 q->drv_priv = cru; 661 q->buf_struct_size = sizeof(struct rzg2l_cru_buffer); 662 q->ops = &rzg2l_cru_qops; 663 q->mem_ops = &vb2_dma_contig_memops; 664 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 665 q->min_queued_buffers = 4; 666 q->dev = cru->dev; 667 668 ret = vb2_queue_init(q); 669 if (ret < 0) { 670 dev_err(cru->dev, "failed to initialize VB2 queue\n"); 671 goto error; 672 } 673 674 return 0; 675 676 error: 677 mutex_destroy(&cru->lock); 678 v4l2_device_unregister(&cru->v4l2_dev); 679 return ret; 680 } 681 682 /* ----------------------------------------------------------------------------- 683 * V4L2 stuff 684 */ 685 686 static void rzg2l_cru_format_align(struct rzg2l_cru_dev *cru, 687 struct v4l2_pix_format *pix) 688 { 689 const struct rzg2l_cru_ip_format *fmt; 690 691 fmt = rzg2l_cru_ip_format_to_fmt(pix->pixelformat); 692 if (!fmt) { 693 pix->pixelformat = RZG2L_CRU_DEFAULT_FORMAT; 694 fmt = rzg2l_cru_ip_format_to_fmt(pix->pixelformat); 695 } 696 697 switch (pix->field) { 698 case V4L2_FIELD_TOP: 699 case V4L2_FIELD_BOTTOM: 700 case V4L2_FIELD_NONE: 701 case V4L2_FIELD_INTERLACED_TB: 702 case V4L2_FIELD_INTERLACED_BT: 703 case V4L2_FIELD_INTERLACED: 704 break; 705 default: 706 pix->field = RZG2L_CRU_DEFAULT_FIELD; 707 break; 708 } 709 710 /* Limit to CRU capabilities */ 711 v4l_bound_align_image(&pix->width, 320, RZG2L_CRU_MAX_INPUT_WIDTH, 1, 712 &pix->height, 240, RZG2L_CRU_MAX_INPUT_HEIGHT, 2, 0); 713 714 pix->bytesperline = pix->width * fmt->bpp; 715 pix->sizeimage = pix->bytesperline * pix->height; 716 717 dev_dbg(cru->dev, "Format %ux%u bpl: %u size: %u\n", 718 pix->width, pix->height, pix->bytesperline, pix->sizeimage); 719 } 720 721 static void rzg2l_cru_try_format(struct rzg2l_cru_dev *cru, 722 struct v4l2_pix_format *pix) 723 { 724 /* 725 * The V4L2 specification clearly documents the colorspace fields 726 * as being set by drivers for capture devices. Using the values 727 * supplied by userspace thus wouldn't comply with the API. Until 728 * the API is updated force fixed values. 729 */ 730 pix->colorspace = RZG2L_CRU_DEFAULT_COLORSPACE; 731 pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace); 732 pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace); 733 pix->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, pix->colorspace, 734 pix->ycbcr_enc); 735 736 rzg2l_cru_format_align(cru, pix); 737 } 738 739 static int rzg2l_cru_querycap(struct file *file, void *priv, 740 struct v4l2_capability *cap) 741 { 742 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 743 strscpy(cap->card, "RZG2L_CRU", sizeof(cap->card)); 744 745 return 0; 746 } 747 748 static int rzg2l_cru_try_fmt_vid_cap(struct file *file, void *priv, 749 struct v4l2_format *f) 750 { 751 struct rzg2l_cru_dev *cru = video_drvdata(file); 752 753 rzg2l_cru_try_format(cru, &f->fmt.pix); 754 755 return 0; 756 } 757 758 static int rzg2l_cru_s_fmt_vid_cap(struct file *file, void *priv, 759 struct v4l2_format *f) 760 { 761 struct rzg2l_cru_dev *cru = video_drvdata(file); 762 763 if (vb2_is_busy(&cru->queue)) 764 return -EBUSY; 765 766 rzg2l_cru_try_format(cru, &f->fmt.pix); 767 768 cru->format = f->fmt.pix; 769 770 return 0; 771 } 772 773 static int rzg2l_cru_g_fmt_vid_cap(struct file *file, void *priv, 774 struct v4l2_format *f) 775 { 776 struct rzg2l_cru_dev *cru = video_drvdata(file); 777 778 f->fmt.pix = cru->format; 779 780 return 0; 781 } 782 783 static int rzg2l_cru_enum_fmt_vid_cap(struct file *file, void *priv, 784 struct v4l2_fmtdesc *f) 785 { 786 const struct rzg2l_cru_ip_format *fmt; 787 788 fmt = rzg2l_cru_ip_index_to_fmt(f->index); 789 if (!fmt) 790 return -EINVAL; 791 792 f->pixelformat = fmt->format; 793 794 return 0; 795 } 796 797 static const struct v4l2_ioctl_ops rzg2l_cru_ioctl_ops = { 798 .vidioc_querycap = rzg2l_cru_querycap, 799 .vidioc_try_fmt_vid_cap = rzg2l_cru_try_fmt_vid_cap, 800 .vidioc_g_fmt_vid_cap = rzg2l_cru_g_fmt_vid_cap, 801 .vidioc_s_fmt_vid_cap = rzg2l_cru_s_fmt_vid_cap, 802 .vidioc_enum_fmt_vid_cap = rzg2l_cru_enum_fmt_vid_cap, 803 804 .vidioc_reqbufs = vb2_ioctl_reqbufs, 805 .vidioc_create_bufs = vb2_ioctl_create_bufs, 806 .vidioc_querybuf = vb2_ioctl_querybuf, 807 .vidioc_qbuf = vb2_ioctl_qbuf, 808 .vidioc_dqbuf = vb2_ioctl_dqbuf, 809 .vidioc_expbuf = vb2_ioctl_expbuf, 810 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 811 .vidioc_streamon = vb2_ioctl_streamon, 812 .vidioc_streamoff = vb2_ioctl_streamoff, 813 }; 814 815 /* ----------------------------------------------------------------------------- 816 * Media controller file operations 817 */ 818 819 static int rzg2l_cru_open(struct file *file) 820 { 821 struct rzg2l_cru_dev *cru = video_drvdata(file); 822 int ret; 823 824 ret = mutex_lock_interruptible(&cru->lock); 825 if (ret) 826 return ret; 827 828 file->private_data = cru; 829 ret = v4l2_fh_open(file); 830 if (ret) 831 goto err_unlock; 832 833 mutex_unlock(&cru->lock); 834 835 return 0; 836 837 err_unlock: 838 mutex_unlock(&cru->lock); 839 840 return ret; 841 } 842 843 static int rzg2l_cru_release(struct file *file) 844 { 845 struct rzg2l_cru_dev *cru = video_drvdata(file); 846 int ret; 847 848 mutex_lock(&cru->lock); 849 850 /* the release helper will cleanup any on-going streaming. */ 851 ret = _vb2_fop_release(file, NULL); 852 853 mutex_unlock(&cru->lock); 854 855 return ret; 856 } 857 858 static const struct v4l2_file_operations rzg2l_cru_fops = { 859 .owner = THIS_MODULE, 860 .unlocked_ioctl = video_ioctl2, 861 .open = rzg2l_cru_open, 862 .release = rzg2l_cru_release, 863 .poll = vb2_fop_poll, 864 .mmap = vb2_fop_mmap, 865 .read = vb2_fop_read, 866 }; 867 868 /* ----------------------------------------------------------------------------- 869 * Media entity operations 870 */ 871 872 static int rzg2l_cru_video_link_validate(struct media_link *link) 873 { 874 struct v4l2_subdev_format fmt = { 875 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 876 }; 877 const struct rzg2l_cru_ip_format *video_fmt; 878 struct v4l2_subdev *subdev; 879 struct rzg2l_cru_dev *cru; 880 int ret; 881 882 subdev = media_entity_to_v4l2_subdev(link->source->entity); 883 fmt.pad = link->source->index; 884 ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); 885 if (ret < 0) 886 return ret == -ENOIOCTLCMD ? -EINVAL : ret; 887 888 cru = container_of(media_entity_to_video_device(link->sink->entity), 889 struct rzg2l_cru_dev, vdev); 890 video_fmt = rzg2l_cru_ip_format_to_fmt(cru->format.pixelformat); 891 892 if (fmt.format.width != cru->format.width || 893 fmt.format.height != cru->format.height || 894 fmt.format.field != cru->format.field || 895 video_fmt->code != fmt.format.code) 896 return -EPIPE; 897 898 return 0; 899 } 900 901 static const struct media_entity_operations rzg2l_cru_video_media_ops = { 902 .link_validate = rzg2l_cru_video_link_validate, 903 }; 904 905 static void rzg2l_cru_v4l2_init(struct rzg2l_cru_dev *cru) 906 { 907 struct video_device *vdev = &cru->vdev; 908 909 vdev->v4l2_dev = &cru->v4l2_dev; 910 vdev->queue = &cru->queue; 911 snprintf(vdev->name, sizeof(vdev->name), "CRU output"); 912 vdev->release = video_device_release_empty; 913 vdev->lock = &cru->lock; 914 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 915 vdev->device_caps |= V4L2_CAP_IO_MC; 916 vdev->entity.ops = &rzg2l_cru_video_media_ops; 917 vdev->fops = &rzg2l_cru_fops; 918 vdev->ioctl_ops = &rzg2l_cru_ioctl_ops; 919 920 /* Set a default format */ 921 cru->format.pixelformat = RZG2L_CRU_DEFAULT_FORMAT; 922 cru->format.width = RZG2L_CRU_DEFAULT_WIDTH; 923 cru->format.height = RZG2L_CRU_DEFAULT_HEIGHT; 924 cru->format.field = RZG2L_CRU_DEFAULT_FIELD; 925 cru->format.colorspace = RZG2L_CRU_DEFAULT_COLORSPACE; 926 rzg2l_cru_format_align(cru, &cru->format); 927 } 928 929 void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru) 930 { 931 media_device_unregister(&cru->mdev); 932 video_unregister_device(&cru->vdev); 933 } 934 935 int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru) 936 { 937 struct video_device *vdev = &cru->vdev; 938 int ret; 939 940 if (video_is_registered(&cru->vdev)) { 941 struct media_entity *entity; 942 943 entity = &cru->vdev.entity; 944 if (!entity->graph_obj.mdev) 945 entity->graph_obj.mdev = &cru->mdev; 946 return 0; 947 } 948 949 rzg2l_cru_v4l2_init(cru); 950 video_set_drvdata(vdev, cru); 951 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 952 if (ret) { 953 dev_err(cru->dev, "Failed to register video device\n"); 954 return ret; 955 } 956 957 ret = media_device_register(&cru->mdev); 958 if (ret) { 959 video_unregister_device(&cru->vdev); 960 return ret; 961 } 962 963 return 0; 964 } 965