107fc05bdSLad Prabhakar // SPDX-License-Identifier: GPL-2.0 207fc05bdSLad Prabhakar /* 307fc05bdSLad Prabhakar * Driver for Renesas RZ/G2L CRU 407fc05bdSLad Prabhakar * 507fc05bdSLad Prabhakar * Copyright (C) 2022 Renesas Electronics Corp. 607fc05bdSLad Prabhakar */ 707fc05bdSLad Prabhakar 8*9c7fa014SBiju Das #include <linux/delay.h> 907fc05bdSLad Prabhakar #include "rzg2l-cru.h" 1007fc05bdSLad Prabhakar 1107fc05bdSLad Prabhakar struct rzg2l_cru_ip_format { 1207fc05bdSLad Prabhakar u32 code; 1307fc05bdSLad Prabhakar unsigned int datatype; 1407fc05bdSLad Prabhakar unsigned int bpp; 1507fc05bdSLad Prabhakar }; 1607fc05bdSLad Prabhakar 1707fc05bdSLad Prabhakar static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] = { 1807fc05bdSLad Prabhakar { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 }, 1907fc05bdSLad Prabhakar }; 2007fc05bdSLad Prabhakar 2107fc05bdSLad Prabhakar enum rzg2l_csi2_pads { 2207fc05bdSLad Prabhakar RZG2L_CRU_IP_SINK = 0, 2307fc05bdSLad Prabhakar RZG2L_CRU_IP_SOURCE, 2407fc05bdSLad Prabhakar }; 2507fc05bdSLad Prabhakar 2607fc05bdSLad Prabhakar static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code) 2707fc05bdSLad Prabhakar { 2807fc05bdSLad Prabhakar unsigned int i; 2907fc05bdSLad Prabhakar 3007fc05bdSLad Prabhakar for (i = 0; i < ARRAY_SIZE(rzg2l_cru_ip_formats); i++) 3107fc05bdSLad Prabhakar if (rzg2l_cru_ip_formats[i].code == code) 3207fc05bdSLad Prabhakar return &rzg2l_cru_ip_formats[i]; 3307fc05bdSLad Prabhakar 3407fc05bdSLad Prabhakar return NULL; 3507fc05bdSLad Prabhakar } 3607fc05bdSLad Prabhakar 3707fc05bdSLad Prabhakar struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru) 3807fc05bdSLad Prabhakar { 3907fc05bdSLad Prabhakar struct v4l2_subdev_state *state; 4007fc05bdSLad Prabhakar struct v4l2_mbus_framefmt *fmt; 4107fc05bdSLad Prabhakar 4207fc05bdSLad Prabhakar state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev); 43bc0e8d91SSakari Ailus fmt = v4l2_subdev_state_get_format(state, 1); 4407fc05bdSLad Prabhakar v4l2_subdev_unlock_state(state); 4507fc05bdSLad Prabhakar 4607fc05bdSLad Prabhakar return fmt; 4707fc05bdSLad Prabhakar } 4807fc05bdSLad Prabhakar 4907fc05bdSLad Prabhakar static int rzg2l_cru_ip_s_stream(struct v4l2_subdev *sd, int enable) 5007fc05bdSLad Prabhakar { 5107fc05bdSLad Prabhakar struct rzg2l_cru_dev *cru; 5207fc05bdSLad Prabhakar int s_stream_ret = 0; 5307fc05bdSLad Prabhakar int ret; 5407fc05bdSLad Prabhakar 5507fc05bdSLad Prabhakar cru = v4l2_get_subdevdata(sd); 5607fc05bdSLad Prabhakar 5707fc05bdSLad Prabhakar if (!enable) { 5807fc05bdSLad Prabhakar ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); 5907fc05bdSLad Prabhakar if (ret) 6007fc05bdSLad Prabhakar s_stream_ret = ret; 6107fc05bdSLad Prabhakar 6207fc05bdSLad Prabhakar ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff); 6307fc05bdSLad Prabhakar if (ret == -ENOIOCTLCMD) 6407fc05bdSLad Prabhakar ret = 0; 6507fc05bdSLad Prabhakar if (ret && !s_stream_ret) 6607fc05bdSLad Prabhakar s_stream_ret = ret; 6707fc05bdSLad Prabhakar rzg2l_cru_stop_image_processing(cru); 6807fc05bdSLad Prabhakar } else { 6907fc05bdSLad Prabhakar ret = v4l2_subdev_call(cru->ip.remote, video, pre_streamon, 0); 7007fc05bdSLad Prabhakar if (ret == -ENOIOCTLCMD) 7107fc05bdSLad Prabhakar ret = 0; 7207fc05bdSLad Prabhakar if (ret) 7307fc05bdSLad Prabhakar return ret; 7407fc05bdSLad Prabhakar 75*9c7fa014SBiju Das fsleep(1000); 76*9c7fa014SBiju Das 7707fc05bdSLad Prabhakar ret = rzg2l_cru_start_image_processing(cru); 7807fc05bdSLad Prabhakar if (ret) { 7907fc05bdSLad Prabhakar v4l2_subdev_call(cru->ip.remote, video, post_streamoff); 8007fc05bdSLad Prabhakar return ret; 8107fc05bdSLad Prabhakar } 8207fc05bdSLad Prabhakar 8307fc05bdSLad Prabhakar rzg2l_cru_vclk_unprepare(cru); 8407fc05bdSLad Prabhakar 8507fc05bdSLad Prabhakar ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); 8607fc05bdSLad Prabhakar if (ret == -ENOIOCTLCMD) 8707fc05bdSLad Prabhakar ret = 0; 8807fc05bdSLad Prabhakar if (!ret) { 8907fc05bdSLad Prabhakar ret = rzg2l_cru_vclk_prepare(cru); 9007fc05bdSLad Prabhakar if (!ret) 9107fc05bdSLad Prabhakar return 0; 9207fc05bdSLad Prabhakar } else { 9307fc05bdSLad Prabhakar /* enable back vclk so that s_stream in error path disables it */ 9407fc05bdSLad Prabhakar if (rzg2l_cru_vclk_prepare(cru)) 9507fc05bdSLad Prabhakar dev_err(cru->dev, "Failed to enable vclk\n"); 9607fc05bdSLad Prabhakar } 9707fc05bdSLad Prabhakar 9807fc05bdSLad Prabhakar s_stream_ret = ret; 9907fc05bdSLad Prabhakar 10007fc05bdSLad Prabhakar v4l2_subdev_call(cru->ip.remote, video, post_streamoff); 10107fc05bdSLad Prabhakar rzg2l_cru_stop_image_processing(cru); 10207fc05bdSLad Prabhakar } 10307fc05bdSLad Prabhakar 10407fc05bdSLad Prabhakar return s_stream_ret; 10507fc05bdSLad Prabhakar } 10607fc05bdSLad Prabhakar 10707fc05bdSLad Prabhakar static int rzg2l_cru_ip_set_format(struct v4l2_subdev *sd, 10807fc05bdSLad Prabhakar struct v4l2_subdev_state *state, 10907fc05bdSLad Prabhakar struct v4l2_subdev_format *fmt) 11007fc05bdSLad Prabhakar { 11107fc05bdSLad Prabhakar struct v4l2_mbus_framefmt *src_format; 11207fc05bdSLad Prabhakar struct v4l2_mbus_framefmt *sink_format; 11307fc05bdSLad Prabhakar 114bc0e8d91SSakari Ailus src_format = v4l2_subdev_state_get_format(state, RZG2L_CRU_IP_SOURCE); 11507fc05bdSLad Prabhakar if (fmt->pad == RZG2L_CRU_IP_SOURCE) { 11607fc05bdSLad Prabhakar fmt->format = *src_format; 11707fc05bdSLad Prabhakar return 0; 11807fc05bdSLad Prabhakar } 11907fc05bdSLad Prabhakar 120bc0e8d91SSakari Ailus sink_format = v4l2_subdev_state_get_format(state, fmt->pad); 12107fc05bdSLad Prabhakar 12207fc05bdSLad Prabhakar if (!rzg2l_cru_ip_code_to_fmt(fmt->format.code)) 12307fc05bdSLad Prabhakar sink_format->code = rzg2l_cru_ip_formats[0].code; 12407fc05bdSLad Prabhakar else 12507fc05bdSLad Prabhakar sink_format->code = fmt->format.code; 12607fc05bdSLad Prabhakar 12707fc05bdSLad Prabhakar sink_format->field = V4L2_FIELD_NONE; 12807fc05bdSLad Prabhakar sink_format->colorspace = fmt->format.colorspace; 12907fc05bdSLad Prabhakar sink_format->xfer_func = fmt->format.xfer_func; 13007fc05bdSLad Prabhakar sink_format->ycbcr_enc = fmt->format.ycbcr_enc; 13107fc05bdSLad Prabhakar sink_format->quantization = fmt->format.quantization; 13207fc05bdSLad Prabhakar sink_format->width = clamp_t(u32, fmt->format.width, 13307fc05bdSLad Prabhakar RZG2L_CRU_MIN_INPUT_WIDTH, RZG2L_CRU_MAX_INPUT_WIDTH); 13407fc05bdSLad Prabhakar sink_format->height = clamp_t(u32, fmt->format.height, 13507fc05bdSLad Prabhakar RZG2L_CRU_MIN_INPUT_HEIGHT, RZG2L_CRU_MAX_INPUT_HEIGHT); 13607fc05bdSLad Prabhakar 13707fc05bdSLad Prabhakar fmt->format = *sink_format; 13807fc05bdSLad Prabhakar 13907fc05bdSLad Prabhakar /* propagate format to source pad */ 14007fc05bdSLad Prabhakar *src_format = *sink_format; 14107fc05bdSLad Prabhakar 14207fc05bdSLad Prabhakar return 0; 14307fc05bdSLad Prabhakar } 14407fc05bdSLad Prabhakar 14507fc05bdSLad Prabhakar static int rzg2l_cru_ip_enum_mbus_code(struct v4l2_subdev *sd, 14607fc05bdSLad Prabhakar struct v4l2_subdev_state *state, 14707fc05bdSLad Prabhakar struct v4l2_subdev_mbus_code_enum *code) 14807fc05bdSLad Prabhakar { 14907fc05bdSLad Prabhakar if (code->index >= ARRAY_SIZE(rzg2l_cru_ip_formats)) 15007fc05bdSLad Prabhakar return -EINVAL; 15107fc05bdSLad Prabhakar 15207fc05bdSLad Prabhakar code->code = rzg2l_cru_ip_formats[code->index].code; 15307fc05bdSLad Prabhakar return 0; 15407fc05bdSLad Prabhakar } 15507fc05bdSLad Prabhakar 15607fc05bdSLad Prabhakar static int rzg2l_cru_ip_enum_frame_size(struct v4l2_subdev *sd, 15707fc05bdSLad Prabhakar struct v4l2_subdev_state *state, 15807fc05bdSLad Prabhakar struct v4l2_subdev_frame_size_enum *fse) 15907fc05bdSLad Prabhakar { 16007fc05bdSLad Prabhakar if (fse->index != 0) 16107fc05bdSLad Prabhakar return -EINVAL; 16207fc05bdSLad Prabhakar 16307fc05bdSLad Prabhakar if (fse->code != MEDIA_BUS_FMT_UYVY8_1X16) 16407fc05bdSLad Prabhakar return -EINVAL; 16507fc05bdSLad Prabhakar 16607fc05bdSLad Prabhakar fse->min_width = RZG2L_CRU_MIN_INPUT_WIDTH; 16707fc05bdSLad Prabhakar fse->min_height = RZG2L_CRU_MIN_INPUT_HEIGHT; 16807fc05bdSLad Prabhakar fse->max_width = RZG2L_CRU_MAX_INPUT_WIDTH; 16907fc05bdSLad Prabhakar fse->max_height = RZG2L_CRU_MAX_INPUT_HEIGHT; 17007fc05bdSLad Prabhakar 17107fc05bdSLad Prabhakar return 0; 17207fc05bdSLad Prabhakar } 17307fc05bdSLad Prabhakar 1745755be5fSLaurent Pinchart static int rzg2l_cru_ip_init_state(struct v4l2_subdev *sd, 17507fc05bdSLad Prabhakar struct v4l2_subdev_state *sd_state) 17607fc05bdSLad Prabhakar { 17707fc05bdSLad Prabhakar struct v4l2_subdev_format fmt = { .pad = RZG2L_CRU_IP_SINK, }; 17807fc05bdSLad Prabhakar 17907fc05bdSLad Prabhakar fmt.format.width = RZG2L_CRU_MIN_INPUT_WIDTH; 18007fc05bdSLad Prabhakar fmt.format.height = RZG2L_CRU_MIN_INPUT_HEIGHT; 18107fc05bdSLad Prabhakar fmt.format.field = V4L2_FIELD_NONE; 18207fc05bdSLad Prabhakar fmt.format.code = MEDIA_BUS_FMT_UYVY8_1X16; 18307fc05bdSLad Prabhakar fmt.format.colorspace = V4L2_COLORSPACE_SRGB; 18407fc05bdSLad Prabhakar fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 18507fc05bdSLad Prabhakar fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT; 18607fc05bdSLad Prabhakar fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT; 18707fc05bdSLad Prabhakar 18807fc05bdSLad Prabhakar return rzg2l_cru_ip_set_format(sd, sd_state, &fmt); 18907fc05bdSLad Prabhakar } 19007fc05bdSLad Prabhakar 19107fc05bdSLad Prabhakar static const struct v4l2_subdev_video_ops rzg2l_cru_ip_video_ops = { 19207fc05bdSLad Prabhakar .s_stream = rzg2l_cru_ip_s_stream, 19307fc05bdSLad Prabhakar }; 19407fc05bdSLad Prabhakar 19507fc05bdSLad Prabhakar static const struct v4l2_subdev_pad_ops rzg2l_cru_ip_pad_ops = { 19607fc05bdSLad Prabhakar .enum_mbus_code = rzg2l_cru_ip_enum_mbus_code, 19707fc05bdSLad Prabhakar .enum_frame_size = rzg2l_cru_ip_enum_frame_size, 19807fc05bdSLad Prabhakar .get_fmt = v4l2_subdev_get_fmt, 19907fc05bdSLad Prabhakar .set_fmt = rzg2l_cru_ip_set_format, 20007fc05bdSLad Prabhakar }; 20107fc05bdSLad Prabhakar 20207fc05bdSLad Prabhakar static const struct v4l2_subdev_ops rzg2l_cru_ip_subdev_ops = { 20307fc05bdSLad Prabhakar .video = &rzg2l_cru_ip_video_ops, 20407fc05bdSLad Prabhakar .pad = &rzg2l_cru_ip_pad_ops, 20507fc05bdSLad Prabhakar }; 20607fc05bdSLad Prabhakar 2075755be5fSLaurent Pinchart static const struct v4l2_subdev_internal_ops rzg2l_cru_ip_internal_ops = { 2085755be5fSLaurent Pinchart .init_state = rzg2l_cru_ip_init_state, 2095755be5fSLaurent Pinchart }; 2105755be5fSLaurent Pinchart 21107fc05bdSLad Prabhakar static const struct media_entity_operations rzg2l_cru_ip_entity_ops = { 21207fc05bdSLad Prabhakar .link_validate = v4l2_subdev_link_validate, 21307fc05bdSLad Prabhakar }; 21407fc05bdSLad Prabhakar 21507fc05bdSLad Prabhakar int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru) 21607fc05bdSLad Prabhakar { 21707fc05bdSLad Prabhakar struct rzg2l_cru_ip *ip = &cru->ip; 21807fc05bdSLad Prabhakar int ret; 21907fc05bdSLad Prabhakar 22007fc05bdSLad Prabhakar ip->subdev.dev = cru->dev; 22107fc05bdSLad Prabhakar v4l2_subdev_init(&ip->subdev, &rzg2l_cru_ip_subdev_ops); 2225755be5fSLaurent Pinchart ip->subdev.internal_ops = &rzg2l_cru_ip_internal_ops; 22307fc05bdSLad Prabhakar v4l2_set_subdevdata(&ip->subdev, cru); 22407fc05bdSLad Prabhakar snprintf(ip->subdev.name, sizeof(ip->subdev.name), 22507fc05bdSLad Prabhakar "cru-ip-%s", dev_name(cru->dev)); 22607fc05bdSLad Prabhakar ip->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 22707fc05bdSLad Prabhakar 22807fc05bdSLad Prabhakar ip->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 22907fc05bdSLad Prabhakar ip->subdev.entity.ops = &rzg2l_cru_ip_entity_ops; 23007fc05bdSLad Prabhakar 23107fc05bdSLad Prabhakar ip->pads[0].flags = MEDIA_PAD_FL_SINK; 23207fc05bdSLad Prabhakar ip->pads[1].flags = MEDIA_PAD_FL_SOURCE; 23307fc05bdSLad Prabhakar 23407fc05bdSLad Prabhakar ret = media_entity_pads_init(&ip->subdev.entity, 2, ip->pads); 23507fc05bdSLad Prabhakar if (ret) 23607fc05bdSLad Prabhakar return ret; 23707fc05bdSLad Prabhakar 23807fc05bdSLad Prabhakar ret = v4l2_subdev_init_finalize(&ip->subdev); 23907fc05bdSLad Prabhakar if (ret < 0) 24007fc05bdSLad Prabhakar goto entity_cleanup; 24107fc05bdSLad Prabhakar 24207fc05bdSLad Prabhakar ret = v4l2_device_register_subdev(&cru->v4l2_dev, &ip->subdev); 24307fc05bdSLad Prabhakar if (ret < 0) 24407fc05bdSLad Prabhakar goto error_subdev; 24507fc05bdSLad Prabhakar 24607fc05bdSLad Prabhakar return 0; 24707fc05bdSLad Prabhakar error_subdev: 24807fc05bdSLad Prabhakar v4l2_subdev_cleanup(&ip->subdev); 24907fc05bdSLad Prabhakar entity_cleanup: 25007fc05bdSLad Prabhakar media_entity_cleanup(&ip->subdev.entity); 25107fc05bdSLad Prabhakar 25207fc05bdSLad Prabhakar return ret; 25307fc05bdSLad Prabhakar } 25407fc05bdSLad Prabhakar 25507fc05bdSLad Prabhakar void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru) 25607fc05bdSLad Prabhakar { 25707fc05bdSLad Prabhakar struct rzg2l_cru_ip *ip = &cru->ip; 25807fc05bdSLad Prabhakar 25907fc05bdSLad Prabhakar media_entity_cleanup(&ip->subdev.entity); 26007fc05bdSLad Prabhakar v4l2_subdev_cleanup(&ip->subdev); 26107fc05bdSLad Prabhakar v4l2_device_unregister_subdev(&ip->subdev); 26207fc05bdSLad Prabhakar } 263