1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Driver for Renesas RZ/G2L CRU 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RZG2L_CRU__ 9 #define __RZG2L_CRU__ 10 11 #include <linux/irqreturn.h> 12 #include <linux/reset.h> 13 14 #include <media/v4l2-async.h> 15 #include <media/v4l2-dev.h> 16 #include <media/v4l2-device.h> 17 #include <media/videobuf2-v4l2.h> 18 19 /* Number of HW buffers */ 20 #define RZG2L_CRU_HW_BUFFER_MAX 8 21 #define RZG2L_CRU_HW_BUFFER_DEFAULT 3 22 23 /* Address alignment mask for HW buffers */ 24 #define RZG2L_CRU_HW_BUFFER_MASK 0x1ff 25 26 /* Maximum number of CSI2 virtual channels */ 27 #define RZG2L_CRU_CSI2_VCHANNEL 4 28 29 #define RZG2L_CRU_MIN_INPUT_WIDTH 320 30 #define RZG2L_CRU_MAX_INPUT_WIDTH 2800 31 #define RZG2L_CRU_MIN_INPUT_HEIGHT 240 32 #define RZG2L_CRU_MAX_INPUT_HEIGHT 4095 33 34 enum rzg2l_csi2_pads { 35 RZG2L_CRU_IP_SINK = 0, 36 RZG2L_CRU_IP_SOURCE, 37 }; 38 39 /** 40 * enum rzg2l_cru_dma_state - DMA states 41 * @RZG2L_CRU_DMA_STOPPED: No operation in progress 42 * @RZG2L_CRU_DMA_STARTING: Capture starting up 43 * @RZG2L_CRU_DMA_RUNNING: Operation in progress have buffers 44 * @RZG2L_CRU_DMA_STOPPING: Stopping operation 45 */ 46 enum rzg2l_cru_dma_state { 47 RZG2L_CRU_DMA_STOPPED = 0, 48 RZG2L_CRU_DMA_STARTING, 49 RZG2L_CRU_DMA_RUNNING, 50 RZG2L_CRU_DMA_STOPPING, 51 }; 52 53 struct rzg2l_cru_csi { 54 struct v4l2_async_connection *asd; 55 struct v4l2_subdev *subdev; 56 }; 57 58 struct rzg2l_cru_ip { 59 struct v4l2_subdev subdev; 60 struct media_pad pads[2]; 61 struct v4l2_async_notifier notifier; 62 struct v4l2_subdev *remote; 63 }; 64 65 /** 66 * struct rzg2l_cru_ip_format - CRU IP format 67 * @code: Media bus code 68 * @datatype: MIPI CSI2 data type 69 * @format: 4CC format identifier (V4L2_PIX_FMT_*) 70 * @icndmr: ICnDMR register value 71 * @bpp: bytes per pixel 72 * @yuv: Flag to indicate whether the format is YUV-based. 73 */ 74 struct rzg2l_cru_ip_format { 75 u32 code; 76 u32 datatype; 77 u32 format; 78 u32 icndmr; 79 u8 bpp; 80 bool yuv; 81 }; 82 83 /** 84 * struct rzg2l_cru_dev - Renesas CRU device structure 85 * @dev: (OF) device 86 * @base: device I/O register space remapped to virtual memory 87 * @info: info about CRU instance 88 * 89 * @presetn: CRU_PRESETN reset line 90 * @aresetn: CRU_ARESETN reset line 91 * 92 * @vclk: CRU Main clock 93 * 94 * @vdev: V4L2 video device associated with CRU 95 * @v4l2_dev: V4L2 device 96 * @num_buf: Holds the current number of buffers enabled 97 * @notifier: V4L2 asynchronous subdevs notifier 98 * 99 * @ip: Image processing subdev info 100 * @csi: CSI info 101 * @mdev: media device 102 * @mdev_lock: protects the count, notifier and csi members 103 * @pad: media pad for the video device entity 104 * 105 * @lock: protects @queue 106 * @queue: vb2 buffers queue 107 * @scratch: cpu address for scratch buffer 108 * @scratch_phys: physical address of the scratch buffer 109 * 110 * @qlock: protects @queue_buf, @buf_list, @sequence 111 * @state 112 * @queue_buf: Keeps track of buffers given to HW slot 113 * @buf_list: list of queued buffers 114 * @sequence: V4L2 buffers sequence number 115 * @state: keeps track of operation state 116 * 117 * @format: active V4L2 pixel format 118 */ 119 struct rzg2l_cru_dev { 120 struct device *dev; 121 void __iomem *base; 122 const struct rzg2l_cru_info *info; 123 124 struct reset_control *presetn; 125 struct reset_control *aresetn; 126 127 struct clk *vclk; 128 129 struct video_device vdev; 130 struct v4l2_device v4l2_dev; 131 u8 num_buf; 132 133 struct v4l2_async_notifier notifier; 134 135 struct rzg2l_cru_ip ip; 136 struct rzg2l_cru_csi csi; 137 struct media_device mdev; 138 struct mutex mdev_lock; 139 struct media_pad pad; 140 141 struct mutex lock; 142 struct vb2_queue queue; 143 void *scratch; 144 dma_addr_t scratch_phys; 145 146 spinlock_t qlock; 147 struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX]; 148 struct list_head buf_list; 149 unsigned int sequence; 150 enum rzg2l_cru_dma_state state; 151 152 struct v4l2_pix_format format; 153 }; 154 155 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru); 156 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru); 157 158 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru); 159 void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru); 160 161 int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru); 162 void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru); 163 irqreturn_t rzg2l_cru_irq(int irq, void *data); 164 165 const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format); 166 167 int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru); 168 void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru); 169 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru); 170 171 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code); 172 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_format_to_fmt(u32 format); 173 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_index_to_fmt(u32 index); 174 175 #endif 176