1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Driver for Renesas RZ/G2L CRU 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RZG2L_CRU__ 9 #define __RZG2L_CRU__ 10 11 #include <linux/irqreturn.h> 12 #include <linux/reset.h> 13 14 #include <media/v4l2-async.h> 15 #include <media/v4l2-dev.h> 16 #include <media/v4l2-device.h> 17 #include <media/videobuf2-v4l2.h> 18 19 /* Number of HW buffers */ 20 #define RZG2L_CRU_HW_BUFFER_MAX 8 21 #define RZG2L_CRU_HW_BUFFER_DEFAULT 3 22 23 /* Address alignment mask for HW buffers */ 24 #define RZG2L_CRU_HW_BUFFER_MASK 0x1ff 25 26 /* Maximum number of CSI2 virtual channels */ 27 #define RZG2L_CRU_CSI2_VCHANNEL 4 28 29 #define RZG2L_CRU_MIN_INPUT_WIDTH 320 30 #define RZG2L_CRU_MIN_INPUT_HEIGHT 240 31 32 enum rzg2l_csi2_pads { 33 RZG2L_CRU_IP_SINK = 0, 34 RZG2L_CRU_IP_SOURCE, 35 }; 36 37 struct rzg2l_cru_dev; 38 39 /** 40 * enum rzg2l_cru_dma_state - DMA states 41 * @RZG2L_CRU_DMA_STOPPED: No operation in progress 42 * @RZG2L_CRU_DMA_STARTING: Capture starting up 43 * @RZG2L_CRU_DMA_RUNNING: Operation in progress have buffers 44 * @RZG2L_CRU_DMA_STOPPING: Stopping operation 45 */ 46 enum rzg2l_cru_dma_state { 47 RZG2L_CRU_DMA_STOPPED = 0, 48 RZG2L_CRU_DMA_STARTING, 49 RZG2L_CRU_DMA_RUNNING, 50 RZG2L_CRU_DMA_STOPPING, 51 }; 52 53 struct rzg2l_cru_csi { 54 struct v4l2_async_connection *asd; 55 struct v4l2_subdev *subdev; 56 }; 57 58 struct rzg2l_cru_ip { 59 struct v4l2_subdev subdev; 60 struct media_pad pads[2]; 61 struct v4l2_async_notifier notifier; 62 struct v4l2_subdev *remote; 63 }; 64 65 /** 66 * struct rzg2l_cru_ip_format - CRU IP format 67 * @code: Media bus code 68 * @datatype: MIPI CSI2 data type 69 * @format: 4CC format identifier (V4L2_PIX_FMT_*) 70 * @icndmr: ICnDMR register value 71 * @bpp: bytes per pixel 72 * @yuv: Flag to indicate whether the format is YUV-based. 73 */ 74 struct rzg2l_cru_ip_format { 75 u32 code; 76 u32 datatype; 77 u32 format; 78 u32 icndmr; 79 u8 bpp; 80 bool yuv; 81 }; 82 83 struct rzg2l_cru_info { 84 unsigned int max_width; 85 unsigned int max_height; 86 u16 image_conv; 87 const u16 *regs; 88 bool has_stride; 89 irqreturn_t (*irq_handler)(int irq, void *data); 90 void (*enable_interrupts)(struct rzg2l_cru_dev *cru); 91 void (*disable_interrupts)(struct rzg2l_cru_dev *cru); 92 bool (*fifo_empty)(struct rzg2l_cru_dev *cru); 93 void (*csi_setup)(struct rzg2l_cru_dev *cru, 94 const struct rzg2l_cru_ip_format *ip_fmt, 95 u8 csi_vc); 96 }; 97 98 /** 99 * struct rzg2l_cru_dev - Renesas CRU device structure 100 * @dev: (OF) device 101 * @base: device I/O register space remapped to virtual memory 102 * @info: info about CRU instance 103 * 104 * @presetn: CRU_PRESETN reset line 105 * @aresetn: CRU_ARESETN reset line 106 * 107 * @vclk: CRU Main clock 108 * 109 * @vdev: V4L2 video device associated with CRU 110 * @v4l2_dev: V4L2 device 111 * @num_buf: Holds the current number of buffers enabled 112 * @svc_channel: SVC0/1/2/3 to use for RZ/G3E 113 * @buf_addr: Memory addresses where current video data is written. 114 * @notifier: V4L2 asynchronous subdevs notifier 115 * 116 * @ip: Image processing subdev info 117 * @csi: CSI info 118 * @mdev: media device 119 * @mdev_lock: protects the count, notifier and csi members 120 * @pad: media pad for the video device entity 121 * 122 * @lock: protects @queue 123 * @queue: vb2 buffers queue 124 * @scratch: cpu address for scratch buffer 125 * @scratch_phys: physical address of the scratch buffer 126 * 127 * @qlock: protects @queue_buf, @buf_list, @sequence 128 * @state 129 * @queue_buf: Keeps track of buffers given to HW slot 130 * @buf_list: list of queued buffers 131 * @sequence: V4L2 buffers sequence number 132 * @state: keeps track of operation state 133 * 134 * @format: active V4L2 pixel format 135 */ 136 struct rzg2l_cru_dev { 137 struct device *dev; 138 void __iomem *base; 139 const struct rzg2l_cru_info *info; 140 141 struct reset_control *presetn; 142 struct reset_control *aresetn; 143 144 struct clk *vclk; 145 146 struct video_device vdev; 147 struct v4l2_device v4l2_dev; 148 u8 num_buf; 149 150 u8 svc_channel; 151 dma_addr_t buf_addr[RZG2L_CRU_HW_BUFFER_DEFAULT]; 152 153 struct v4l2_async_notifier notifier; 154 155 struct rzg2l_cru_ip ip; 156 struct rzg2l_cru_csi csi; 157 struct media_device mdev; 158 struct mutex mdev_lock; 159 struct media_pad pad; 160 161 struct mutex lock; 162 struct vb2_queue queue; 163 void *scratch; 164 dma_addr_t scratch_phys; 165 166 spinlock_t qlock; 167 struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX]; 168 struct list_head buf_list; 169 unsigned int sequence; 170 enum rzg2l_cru_dma_state state; 171 172 struct v4l2_pix_format format; 173 }; 174 175 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru); 176 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru); 177 178 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru); 179 void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru); 180 181 int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru); 182 void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru); 183 irqreturn_t rzg2l_cru_irq(int irq, void *data); 184 irqreturn_t rzg3e_cru_irq(int irq, void *data); 185 186 const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format); 187 188 int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru); 189 void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru); 190 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru); 191 192 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code); 193 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_format_to_fmt(u32 format); 194 const struct rzg2l_cru_ip_format *rzg2l_cru_ip_index_to_fmt(u32 index); 195 196 void rzg2l_cru_enable_interrupts(struct rzg2l_cru_dev *cru); 197 void rzg2l_cru_disable_interrupts(struct rzg2l_cru_dev *cru); 198 void rzg3e_cru_enable_interrupts(struct rzg2l_cru_dev *cru); 199 void rzg3e_cru_disable_interrupts(struct rzg2l_cru_dev *cru); 200 201 bool rzg2l_fifo_empty(struct rzg2l_cru_dev *cru); 202 bool rz3e_fifo_empty(struct rzg2l_cru_dev *cru); 203 void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, 204 const struct rzg2l_cru_ip_format *ip_fmt, 205 u8 csi_vc); 206 void rzg3e_cru_csi2_setup(struct rzg2l_cru_dev *cru, 207 const struct rzg2l_cru_ip_format *ip_fmt, 208 u8 csi_vc); 209 210 #endif 211