1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RZG2L_CRU_REGS_H__ 9 #define __RZG2L_CRU_REGS_H__ 10 11 /* HW CRU Registers Definition */ 12 13 /* CRU Control Register */ 14 #define CRUnCTRL 0x0 15 #define CRUnCTRL_VINSEL(x) ((x) << 0) 16 17 /* CRU Interrupt Enable Register */ 18 #define CRUnIE 0x4 19 #define CRUnIE_EFE BIT(17) 20 21 /* CRU Interrupt Status Register */ 22 #define CRUnINTS 0x8 23 #define CRUnINTS_SFS BIT(16) 24 25 /* CRU Reset Register */ 26 #define CRUnRST 0xc 27 #define CRUnRST_VRESETN BIT(0) 28 29 /* Memory Bank Base Address (Lower) Register for CRU Image Data */ 30 #define AMnMBxADDRL(x) (0x100 + ((x) * 8)) 31 32 /* Memory Bank Base Address (Higher) Register for CRU Image Data */ 33 #define AMnMBxADDRH(x) (0x104 + ((x) * 8)) 34 35 /* Memory Bank Enable Register for CRU Image Data */ 36 #define AMnMBVALID 0x148 37 #define AMnMBVALID_MBVALID(x) GENMASK(x, 0) 38 39 /* Memory Bank Status Register for CRU Image Data */ 40 #define AMnMBS 0x14c 41 #define AMnMBS_MBSTS 0x7 42 43 /* AXI Master Transfer Setting Register for CRU Image Data */ 44 #define AMnAXIATTR 0x158 45 #define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0) 46 #define AMnAXIATTR_AXILEN (0xf) 47 48 /* AXI Master FIFO Pointer Register for CRU Image Data */ 49 #define AMnFIFOPNTR 0x168 50 #define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0) 51 #define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16) 52 53 /* AXI Master Transfer Stop Register for CRU Image Data */ 54 #define AMnAXISTP 0x174 55 #define AMnAXISTP_AXI_STOP BIT(0) 56 57 /* AXI Master Transfer Stop Status Register for CRU Image Data */ 58 #define AMnAXISTPACK 0x178 59 #define AMnAXISTPACK_AXI_STOP_ACK BIT(0) 60 61 /* CRU Image Processing Enable Register */ 62 #define ICnEN 0x200 63 #define ICnEN_ICEN BIT(0) 64 65 /* CRU Image Processing Main Control Register */ 66 #define ICnMC 0x208 67 #define ICnMC_CSCTHR BIT(5) 68 #define ICnMC_INF(x) ((x) << 16) 69 #define ICnMC_VCSEL(x) ((x) << 22) 70 #define ICnMC_INF_MASK GENMASK(21, 16) 71 72 /* CRU Module Status Register */ 73 #define ICnMS 0x254 74 #define ICnMS_IA BIT(2) 75 76 /* CRU Data Output Mode Register */ 77 #define ICnDMR 0x26c 78 #define ICnDMR_YCMODE_UYVY (1 << 4) 79 80 #endif /* __RZG2L_CRU_REGS_H__ */ 81