1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface 4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 5 * 6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c" 7 * Copyright (C) 2008 Magnus Damm 8 * 9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c", 10 * Copyright (C) 2006, Sascha Hauer, Pengutronix 11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/err.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_graph.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/time.h> 31 #include <linux/videodev2.h> 32 33 #include <media/v4l2-async.h> 34 #include <media/v4l2-common.h> 35 #include <media/v4l2-ctrls.h> 36 #include <media/v4l2-dev.h> 37 #include <media/v4l2-device.h> 38 #include <media/v4l2-event.h> 39 #include <media/v4l2-fwnode.h> 40 #include <media/v4l2-image-sizes.h> 41 #include <media/v4l2-ioctl.h> 42 #include <media/v4l2-mediabus.h> 43 #include <media/videobuf2-dma-contig.h> 44 45 #include <media/drv-intf/renesas-ceu.h> 46 47 #define DRIVER_NAME "renesas-ceu" 48 49 /* CEU registers offsets and masks. */ 50 #define CEU_CAPSR 0x00 /* Capture start register */ 51 #define CEU_CAPCR 0x04 /* Capture control register */ 52 #define CEU_CAMCR 0x08 /* Capture interface control register */ 53 #define CEU_CAMOR 0x10 /* Capture interface offset register */ 54 #define CEU_CAPWR 0x14 /* Capture interface width register */ 55 #define CEU_CAIFR 0x18 /* Capture interface input format register */ 56 #define CEU_CRCNTR 0x28 /* CEU register control register */ 57 #define CEU_CRCMPR 0x2c /* CEU register forcible control register */ 58 #define CEU_CFLCR 0x30 /* Capture filter control register */ 59 #define CEU_CFSZR 0x34 /* Capture filter size clip register */ 60 #define CEU_CDWDR 0x38 /* Capture destination width register */ 61 #define CEU_CDAYR 0x3c /* Capture data address Y register */ 62 #define CEU_CDACR 0x40 /* Capture data address C register */ 63 #define CEU_CFWCR 0x5c /* Firewall operation control register */ 64 #define CEU_CDOCR 0x64 /* Capture data output control register */ 65 #define CEU_CEIER 0x70 /* Capture event interrupt enable register */ 66 #define CEU_CETCR 0x74 /* Capture event flag clear register */ 67 #define CEU_CSTSR 0x7c /* Capture status register */ 68 #define CEU_CSRTR 0x80 /* Capture software reset register */ 69 70 /* Data synchronous fetch mode. */ 71 #define CEU_CAMCR_JPEG BIT(4) 72 73 /* Input components ordering: CEU_CAMCR.DTARY field. */ 74 #define CEU_CAMCR_DTARY_8_UYVY (0x00 << 8) 75 #define CEU_CAMCR_DTARY_8_VYUY (0x01 << 8) 76 #define CEU_CAMCR_DTARY_8_YUYV (0x02 << 8) 77 #define CEU_CAMCR_DTARY_8_YVYU (0x03 << 8) 78 /* TODO: input components ordering for 16 bits input. */ 79 80 /* Bus transfer MTU. */ 81 #define CEU_CAPCR_BUS_WIDTH256 (0x3 << 20) 82 83 /* Bus width configuration. */ 84 #define CEU_CAMCR_DTIF_16BITS BIT(12) 85 86 /* No downsampling to planar YUV420 in image fetch mode. */ 87 #define CEU_CDOCR_NO_DOWSAMPLE BIT(4) 88 89 /* Swap all input data in 8-bit, 16-bits and 32-bits units (Figure 46.45). */ 90 #define CEU_CDOCR_SWAP_ENDIANNESS (7) 91 92 /* Capture reset and enable bits. */ 93 #define CEU_CAPSR_CPKIL BIT(16) 94 #define CEU_CAPSR_CE BIT(0) 95 96 /* CEU operating flag bit. */ 97 #define CEU_CAPCR_CTNCP BIT(16) 98 #define CEU_CSTRST_CPTON BIT(0) 99 100 /* Platform specific IRQ source flags. */ 101 #define CEU_CETCR_ALL_IRQS_RZ 0x397f313 102 #define CEU_CETCR_ALL_IRQS_SH4 0x3d7f313 103 104 /* Prohibited register access interrupt bit. */ 105 #define CEU_CETCR_IGRW BIT(4) 106 /* One-frame capture end interrupt. */ 107 #define CEU_CEIER_CPE BIT(0) 108 /* VBP error. */ 109 #define CEU_CEIER_VBP BIT(20) 110 #define CEU_CEIER_MASK (CEU_CEIER_CPE | CEU_CEIER_VBP) 111 112 #define CEU_MAX_WIDTH 2560 113 #define CEU_MAX_HEIGHT 1920 114 #define CEU_MAX_BPL 8188 115 #define CEU_W_MAX(w) ((w) < CEU_MAX_WIDTH ? (w) : CEU_MAX_WIDTH) 116 #define CEU_H_MAX(h) ((h) < CEU_MAX_HEIGHT ? (h) : CEU_MAX_HEIGHT) 117 118 /* 119 * ceu_bus_fmt - describe a 8-bits yuyv format the sensor can produce 120 * 121 * @mbus_code: bus format code 122 * @fmt_order: CEU_CAMCR.DTARY ordering of input components (Y, Cb, Cr) 123 * @fmt_order_swap: swapped CEU_CAMCR.DTARY ordering of input components 124 * (Y, Cr, Cb) 125 * @swapped: does Cr appear before Cb? 126 * @bps: number of bits sent over bus for each sample 127 * @bpp: number of bits per pixels unit 128 */ 129 struct ceu_mbus_fmt { 130 u32 mbus_code; 131 u32 fmt_order; 132 u32 fmt_order_swap; 133 bool swapped; 134 u8 bps; 135 u8 bpp; 136 }; 137 138 /* 139 * ceu_buffer - Link vb2 buffer to the list of available buffers. 140 */ 141 struct ceu_buffer { 142 struct vb2_v4l2_buffer vb; 143 struct list_head queue; 144 }; 145 146 static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf) 147 { 148 return container_of(vbuf, struct ceu_buffer, vb); 149 } 150 151 /* 152 * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice. 153 */ 154 struct ceu_subdev { 155 struct v4l2_async_subdev asd; 156 struct v4l2_subdev *v4l2_sd; 157 158 /* per-subdevice mbus configuration options */ 159 unsigned int mbus_flags; 160 struct ceu_mbus_fmt mbus_fmt; 161 }; 162 163 static struct ceu_subdev *to_ceu_subdev(struct v4l2_async_subdev *asd) 164 { 165 return container_of(asd, struct ceu_subdev, asd); 166 } 167 168 /* 169 * ceu_device - CEU device instance 170 */ 171 struct ceu_device { 172 struct device *dev; 173 struct video_device vdev; 174 struct v4l2_device v4l2_dev; 175 176 /* subdevices descriptors */ 177 struct ceu_subdev **subdevs; 178 /* the subdevice currently in use */ 179 struct ceu_subdev *sd; 180 unsigned int sd_index; 181 unsigned int num_sd; 182 183 /* platform specific mask with all IRQ sources flagged */ 184 u32 irq_mask; 185 186 /* currently configured field and pixel format */ 187 enum v4l2_field field; 188 struct v4l2_pix_format_mplane v4l2_pix; 189 190 /* async subdev notification helpers */ 191 struct v4l2_async_notifier notifier; 192 193 /* vb2 queue, capture buffer list and active buffer pointer */ 194 struct vb2_queue vb2_vq; 195 struct list_head capture; 196 struct vb2_v4l2_buffer *active; 197 unsigned int sequence; 198 199 /* mlock - lock access to interface reset and vb2 queue */ 200 struct mutex mlock; 201 202 /* lock - lock access to capture buffer queue and active buffer */ 203 spinlock_t lock; 204 205 /* base - CEU memory base address */ 206 void __iomem *base; 207 }; 208 209 static inline struct ceu_device *v4l2_to_ceu(struct v4l2_device *v4l2_dev) 210 { 211 return container_of(v4l2_dev, struct ceu_device, v4l2_dev); 212 } 213 214 /* --- CEU memory output formats --- */ 215 216 /* 217 * ceu_fmt - describe a memory output format supported by CEU interface. 218 * 219 * @fourcc: memory layout fourcc format code 220 * @bpp: number of bits for each pixel stored in memory 221 */ 222 struct ceu_fmt { 223 u32 fourcc; 224 u32 bpp; 225 }; 226 227 /* 228 * ceu_format_list - List of supported memory output formats 229 * 230 * If sensor provides any YUYV bus format, all the following planar memory 231 * formats are available thanks to CEU re-ordering and sub-sampling 232 * capabilities. 233 */ 234 static const struct ceu_fmt ceu_fmt_list[] = { 235 { 236 .fourcc = V4L2_PIX_FMT_NV16, 237 .bpp = 16, 238 }, 239 { 240 .fourcc = V4L2_PIX_FMT_NV61, 241 .bpp = 16, 242 }, 243 { 244 .fourcc = V4L2_PIX_FMT_NV12, 245 .bpp = 12, 246 }, 247 { 248 .fourcc = V4L2_PIX_FMT_NV21, 249 .bpp = 12, 250 }, 251 { 252 .fourcc = V4L2_PIX_FMT_YUYV, 253 .bpp = 16, 254 }, 255 { 256 .fourcc = V4L2_PIX_FMT_UYVY, 257 .bpp = 16, 258 }, 259 { 260 .fourcc = V4L2_PIX_FMT_YVYU, 261 .bpp = 16, 262 }, 263 { 264 .fourcc = V4L2_PIX_FMT_VYUY, 265 .bpp = 16, 266 }, 267 }; 268 269 static const struct ceu_fmt *get_ceu_fmt_from_fourcc(unsigned int fourcc) 270 { 271 const struct ceu_fmt *fmt = &ceu_fmt_list[0]; 272 unsigned int i; 273 274 for (i = 0; i < ARRAY_SIZE(ceu_fmt_list); i++, fmt++) 275 if (fmt->fourcc == fourcc) 276 return fmt; 277 278 return NULL; 279 } 280 281 static bool ceu_fmt_mplane(struct v4l2_pix_format_mplane *pix) 282 { 283 switch (pix->pixelformat) { 284 case V4L2_PIX_FMT_YUYV: 285 case V4L2_PIX_FMT_UYVY: 286 case V4L2_PIX_FMT_YVYU: 287 case V4L2_PIX_FMT_VYUY: 288 return false; 289 case V4L2_PIX_FMT_NV16: 290 case V4L2_PIX_FMT_NV61: 291 case V4L2_PIX_FMT_NV12: 292 case V4L2_PIX_FMT_NV21: 293 return true; 294 default: 295 return false; 296 } 297 } 298 299 /* --- CEU HW operations --- */ 300 301 static void ceu_write(struct ceu_device *priv, unsigned int reg_offs, u32 data) 302 { 303 iowrite32(data, priv->base + reg_offs); 304 } 305 306 static u32 ceu_read(struct ceu_device *priv, unsigned int reg_offs) 307 { 308 return ioread32(priv->base + reg_offs); 309 } 310 311 /* 312 * ceu_soft_reset() - Software reset the CEU interface. 313 * @ceu_device: CEU device. 314 * 315 * Returns 0 for success, -EIO for error. 316 */ 317 static int ceu_soft_reset(struct ceu_device *ceudev) 318 { 319 unsigned int i; 320 321 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CPKIL); 322 323 for (i = 0; i < 100; i++) { 324 if (!(ceu_read(ceudev, CEU_CSTSR) & CEU_CSTRST_CPTON)) 325 break; 326 udelay(1); 327 } 328 329 if (i == 100) { 330 dev_err(ceudev->dev, "soft reset time out\n"); 331 return -EIO; 332 } 333 334 for (i = 0; i < 100; i++) { 335 if (!(ceu_read(ceudev, CEU_CAPSR) & CEU_CAPSR_CPKIL)) 336 return 0; 337 udelay(1); 338 } 339 340 /* If we get here, CEU has not reset properly. */ 341 return -EIO; 342 } 343 344 /* --- CEU Capture Operations --- */ 345 346 /* 347 * ceu_hw_config() - Configure CEU interface registers. 348 */ 349 static int ceu_hw_config(struct ceu_device *ceudev) 350 { 351 u32 camcr, cdocr, cfzsr, cdwdr, capwr; 352 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 353 struct ceu_subdev *ceu_sd = ceudev->sd; 354 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt; 355 unsigned int mbus_flags = ceu_sd->mbus_flags; 356 357 /* Start configuring CEU registers */ 358 ceu_write(ceudev, CEU_CAIFR, 0); 359 ceu_write(ceudev, CEU_CFWCR, 0); 360 ceu_write(ceudev, CEU_CRCNTR, 0); 361 ceu_write(ceudev, CEU_CRCMPR, 0); 362 363 /* Set the frame capture period for both image capture and data sync. */ 364 capwr = (pix->height << 16) | pix->width * mbus_fmt->bpp / 8; 365 366 /* 367 * Swap input data endianness by default. 368 * In data fetch mode bytes are received in chunks of 8 bytes. 369 * D0, D1, D2, D3, D4, D5, D6, D7 (D0 received first) 370 * The data is however by default written to memory in reverse order: 371 * D7, D6, D5, D4, D3, D2, D1, D0 (D7 written to lowest byte) 372 * 373 * Use CEU_CDOCR[2:0] to swap data ordering. 374 */ 375 cdocr = CEU_CDOCR_SWAP_ENDIANNESS; 376 377 /* 378 * Configure CAMCR and CDOCR: 379 * match input components ordering with memory output format and 380 * handle downsampling to YUV420. 381 * 382 * If the memory output planar format is 'swapped' (Cr before Cb) and 383 * input format is not, use the swapped version of CAMCR.DTARY. 384 * 385 * If the memory output planar format is not 'swapped' (Cb before Cr) 386 * and input format is, use the swapped version of CAMCR.DTARY. 387 * 388 * CEU by default downsample to planar YUV420 (CDCOR[4] = 0). 389 * If output is planar YUV422 set CDOCR[4] = 1 390 * 391 * No downsample for data fetch sync mode. 392 */ 393 switch (pix->pixelformat) { 394 /* Data fetch sync mode */ 395 case V4L2_PIX_FMT_YUYV: 396 case V4L2_PIX_FMT_YVYU: 397 case V4L2_PIX_FMT_UYVY: 398 case V4L2_PIX_FMT_VYUY: 399 camcr = CEU_CAMCR_JPEG; 400 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 401 cfzsr = (pix->height << 16) | pix->width; 402 cdwdr = pix->plane_fmt[0].bytesperline; 403 break; 404 405 /* Non-swapped planar image capture mode. */ 406 case V4L2_PIX_FMT_NV16: 407 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 408 fallthrough; 409 case V4L2_PIX_FMT_NV12: 410 if (mbus_fmt->swapped) 411 camcr = mbus_fmt->fmt_order_swap; 412 else 413 camcr = mbus_fmt->fmt_order; 414 415 cfzsr = (pix->height << 16) | pix->width; 416 cdwdr = pix->width; 417 break; 418 419 /* Swapped planar image capture mode. */ 420 case V4L2_PIX_FMT_NV61: 421 cdocr |= CEU_CDOCR_NO_DOWSAMPLE; 422 fallthrough; 423 case V4L2_PIX_FMT_NV21: 424 if (mbus_fmt->swapped) 425 camcr = mbus_fmt->fmt_order; 426 else 427 camcr = mbus_fmt->fmt_order_swap; 428 429 cfzsr = (pix->height << 16) | pix->width; 430 cdwdr = pix->width; 431 break; 432 433 default: 434 return -EINVAL; 435 } 436 437 camcr |= mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW ? 1 << 1 : 0; 438 camcr |= mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW ? 1 << 0 : 0; 439 440 /* TODO: handle 16 bit bus width with DTIF bit in CAMCR */ 441 ceu_write(ceudev, CEU_CAMCR, camcr); 442 ceu_write(ceudev, CEU_CDOCR, cdocr); 443 ceu_write(ceudev, CEU_CAPCR, CEU_CAPCR_BUS_WIDTH256); 444 445 /* 446 * TODO: make CAMOR offsets configurable. 447 * CAMOR wants to know the number of blanks between a VS/HS signal 448 * and valid data. This value should actually come from the sensor... 449 */ 450 ceu_write(ceudev, CEU_CAMOR, 0); 451 452 /* TODO: 16 bit bus width require re-calculation of cdwdr and cfzsr */ 453 ceu_write(ceudev, CEU_CAPWR, capwr); 454 ceu_write(ceudev, CEU_CFSZR, cfzsr); 455 ceu_write(ceudev, CEU_CDWDR, cdwdr); 456 457 return 0; 458 } 459 460 /* 461 * ceu_capture() - Trigger start of a capture sequence. 462 * 463 * Program the CEU DMA registers with addresses where to transfer image data. 464 */ 465 static int ceu_capture(struct ceu_device *ceudev) 466 { 467 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 468 dma_addr_t phys_addr_top; 469 470 phys_addr_top = 471 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 0); 472 ceu_write(ceudev, CEU_CDAYR, phys_addr_top); 473 474 /* Ignore CbCr plane for non multi-planar image formats. */ 475 if (ceu_fmt_mplane(pix)) { 476 phys_addr_top = 477 vb2_dma_contig_plane_dma_addr(&ceudev->active->vb2_buf, 478 1); 479 ceu_write(ceudev, CEU_CDACR, phys_addr_top); 480 } 481 482 /* 483 * Trigger new capture start: once for each frame, as we work in 484 * one-frame capture mode. 485 */ 486 ceu_write(ceudev, CEU_CAPSR, CEU_CAPSR_CE); 487 488 return 0; 489 } 490 491 static irqreturn_t ceu_irq(int irq, void *data) 492 { 493 struct ceu_device *ceudev = data; 494 struct vb2_v4l2_buffer *vbuf; 495 struct ceu_buffer *buf; 496 u32 status; 497 498 /* Clean interrupt status. */ 499 status = ceu_read(ceudev, CEU_CETCR); 500 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask); 501 502 /* Unexpected interrupt. */ 503 if (!(status & CEU_CEIER_MASK)) 504 return IRQ_NONE; 505 506 spin_lock(&ceudev->lock); 507 508 /* Stale interrupt from a released buffer, ignore it. */ 509 vbuf = ceudev->active; 510 if (!vbuf) { 511 spin_unlock(&ceudev->lock); 512 return IRQ_HANDLED; 513 } 514 515 /* 516 * When a VBP interrupt occurs, no capture end interrupt will occur 517 * and the image of that frame is not captured correctly. 518 */ 519 if (status & CEU_CEIER_VBP) { 520 dev_err(ceudev->dev, "VBP interrupt: abort capture\n"); 521 goto error_irq_out; 522 } 523 524 /* Prepare to return the 'previous' buffer. */ 525 vbuf->vb2_buf.timestamp = ktime_get_ns(); 526 vbuf->sequence = ceudev->sequence++; 527 vbuf->field = ceudev->field; 528 529 /* Prepare a new 'active' buffer and trigger a new capture. */ 530 if (!list_empty(&ceudev->capture)) { 531 buf = list_first_entry(&ceudev->capture, struct ceu_buffer, 532 queue); 533 list_del(&buf->queue); 534 ceudev->active = &buf->vb; 535 536 ceu_capture(ceudev); 537 } 538 539 /* Return the 'previous' buffer. */ 540 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE); 541 542 spin_unlock(&ceudev->lock); 543 544 return IRQ_HANDLED; 545 546 error_irq_out: 547 /* Return the 'previous' buffer and all queued ones. */ 548 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_ERROR); 549 550 list_for_each_entry(buf, &ceudev->capture, queue) 551 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 552 553 spin_unlock(&ceudev->lock); 554 555 return IRQ_HANDLED; 556 } 557 558 /* --- CEU Videobuf2 operations --- */ 559 560 static void ceu_update_plane_sizes(struct v4l2_plane_pix_format *plane, 561 unsigned int bpl, unsigned int szimage) 562 { 563 memset(plane, 0, sizeof(*plane)); 564 565 plane->sizeimage = szimage; 566 if (plane->bytesperline < bpl || plane->bytesperline > CEU_MAX_BPL) 567 plane->bytesperline = bpl; 568 } 569 570 /* 571 * ceu_calc_plane_sizes() - Fill per-plane 'struct v4l2_plane_pix_format' 572 * information according to the currently configured 573 * pixel format. 574 * @ceu_device: CEU device. 575 * @ceu_fmt: Active image format. 576 * @pix: Pixel format information (store line width and image sizes) 577 */ 578 static void ceu_calc_plane_sizes(struct ceu_device *ceudev, 579 const struct ceu_fmt *ceu_fmt, 580 struct v4l2_pix_format_mplane *pix) 581 { 582 unsigned int bpl, szimage; 583 584 switch (pix->pixelformat) { 585 case V4L2_PIX_FMT_YUYV: 586 case V4L2_PIX_FMT_UYVY: 587 case V4L2_PIX_FMT_YVYU: 588 case V4L2_PIX_FMT_VYUY: 589 pix->num_planes = 1; 590 bpl = pix->width * ceu_fmt->bpp / 8; 591 szimage = pix->height * bpl; 592 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage); 593 break; 594 595 case V4L2_PIX_FMT_NV12: 596 case V4L2_PIX_FMT_NV21: 597 pix->num_planes = 2; 598 bpl = pix->width; 599 szimage = pix->height * pix->width; 600 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage); 601 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage / 2); 602 break; 603 604 case V4L2_PIX_FMT_NV16: 605 case V4L2_PIX_FMT_NV61: 606 default: 607 pix->num_planes = 2; 608 bpl = pix->width; 609 szimage = pix->height * pix->width; 610 ceu_update_plane_sizes(&pix->plane_fmt[0], bpl, szimage); 611 ceu_update_plane_sizes(&pix->plane_fmt[1], bpl, szimage); 612 break; 613 } 614 } 615 616 /* 617 * ceu_vb2_setup() - is called to check whether the driver can accept the 618 * requested number of buffers and to fill in plane sizes 619 * for the current frame format, if required. 620 */ 621 static int ceu_vb2_setup(struct vb2_queue *vq, unsigned int *count, 622 unsigned int *num_planes, unsigned int sizes[], 623 struct device *alloc_devs[]) 624 { 625 struct ceu_device *ceudev = vb2_get_drv_priv(vq); 626 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 627 unsigned int i; 628 629 /* num_planes is set: just check plane sizes. */ 630 if (*num_planes) { 631 for (i = 0; i < pix->num_planes; i++) 632 if (sizes[i] < pix->plane_fmt[i].sizeimage) 633 return -EINVAL; 634 635 return 0; 636 } 637 638 /* num_planes not set: called from REQBUFS, just set plane sizes. */ 639 *num_planes = pix->num_planes; 640 for (i = 0; i < pix->num_planes; i++) 641 sizes[i] = pix->plane_fmt[i].sizeimage; 642 643 return 0; 644 } 645 646 static void ceu_vb2_queue(struct vb2_buffer *vb) 647 { 648 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue); 649 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 650 struct ceu_buffer *buf = vb2_to_ceu(vbuf); 651 unsigned long irqflags; 652 653 spin_lock_irqsave(&ceudev->lock, irqflags); 654 list_add_tail(&buf->queue, &ceudev->capture); 655 spin_unlock_irqrestore(&ceudev->lock, irqflags); 656 } 657 658 static int ceu_vb2_prepare(struct vb2_buffer *vb) 659 { 660 struct ceu_device *ceudev = vb2_get_drv_priv(vb->vb2_queue); 661 struct v4l2_pix_format_mplane *pix = &ceudev->v4l2_pix; 662 unsigned int i; 663 664 for (i = 0; i < pix->num_planes; i++) { 665 if (vb2_plane_size(vb, i) < pix->plane_fmt[i].sizeimage) { 666 dev_err(ceudev->dev, 667 "Plane size too small (%lu < %u)\n", 668 vb2_plane_size(vb, i), 669 pix->plane_fmt[i].sizeimage); 670 return -EINVAL; 671 } 672 673 vb2_set_plane_payload(vb, i, pix->plane_fmt[i].sizeimage); 674 } 675 676 return 0; 677 } 678 679 static int ceu_start_streaming(struct vb2_queue *vq, unsigned int count) 680 { 681 struct ceu_device *ceudev = vb2_get_drv_priv(vq); 682 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 683 struct ceu_buffer *buf; 684 unsigned long irqflags; 685 int ret; 686 687 /* Program the CEU interface according to the CEU image format. */ 688 ret = ceu_hw_config(ceudev); 689 if (ret) 690 goto error_return_bufs; 691 692 ret = v4l2_subdev_call(v4l2_sd, video, s_stream, 1); 693 if (ret && ret != -ENOIOCTLCMD) { 694 dev_dbg(ceudev->dev, 695 "Subdevice failed to start streaming: %d\n", ret); 696 goto error_return_bufs; 697 } 698 699 spin_lock_irqsave(&ceudev->lock, irqflags); 700 ceudev->sequence = 0; 701 702 /* Grab the first available buffer and trigger the first capture. */ 703 buf = list_first_entry(&ceudev->capture, struct ceu_buffer, 704 queue); 705 706 list_del(&buf->queue); 707 ceudev->active = &buf->vb; 708 709 /* Clean and program interrupts for first capture. */ 710 ceu_write(ceudev, CEU_CETCR, ~ceudev->irq_mask); 711 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK); 712 713 ceu_capture(ceudev); 714 715 spin_unlock_irqrestore(&ceudev->lock, irqflags); 716 717 return 0; 718 719 error_return_bufs: 720 spin_lock_irqsave(&ceudev->lock, irqflags); 721 list_for_each_entry(buf, &ceudev->capture, queue) 722 vb2_buffer_done(&ceudev->active->vb2_buf, 723 VB2_BUF_STATE_QUEUED); 724 ceudev->active = NULL; 725 spin_unlock_irqrestore(&ceudev->lock, irqflags); 726 727 return ret; 728 } 729 730 static void ceu_stop_streaming(struct vb2_queue *vq) 731 { 732 struct ceu_device *ceudev = vb2_get_drv_priv(vq); 733 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 734 struct ceu_buffer *buf; 735 unsigned long irqflags; 736 737 /* Clean and disable interrupt sources. */ 738 ceu_write(ceudev, CEU_CETCR, 739 ceu_read(ceudev, CEU_CETCR) & ceudev->irq_mask); 740 ceu_write(ceudev, CEU_CEIER, CEU_CEIER_MASK); 741 742 v4l2_subdev_call(v4l2_sd, video, s_stream, 0); 743 744 spin_lock_irqsave(&ceudev->lock, irqflags); 745 if (ceudev->active) { 746 vb2_buffer_done(&ceudev->active->vb2_buf, 747 VB2_BUF_STATE_ERROR); 748 ceudev->active = NULL; 749 } 750 751 /* Release all queued buffers. */ 752 list_for_each_entry(buf, &ceudev->capture, queue) 753 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 754 INIT_LIST_HEAD(&ceudev->capture); 755 756 spin_unlock_irqrestore(&ceudev->lock, irqflags); 757 758 ceu_soft_reset(ceudev); 759 } 760 761 static const struct vb2_ops ceu_vb2_ops = { 762 .queue_setup = ceu_vb2_setup, 763 .buf_queue = ceu_vb2_queue, 764 .buf_prepare = ceu_vb2_prepare, 765 .wait_prepare = vb2_ops_wait_prepare, 766 .wait_finish = vb2_ops_wait_finish, 767 .start_streaming = ceu_start_streaming, 768 .stop_streaming = ceu_stop_streaming, 769 }; 770 771 /* --- CEU image formats handling --- */ 772 773 /* 774 * __ceu_try_fmt() - test format on CEU and sensor 775 * @ceudev: The CEU device. 776 * @v4l2_fmt: format to test. 777 * @sd_mbus_code: the media bus code accepted by the subdevice; output param. 778 * 779 * Returns 0 for success, < 0 for errors. 780 */ 781 static int __ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt, 782 u32 *sd_mbus_code) 783 { 784 struct ceu_subdev *ceu_sd = ceudev->sd; 785 struct v4l2_pix_format_mplane *pix = &v4l2_fmt->fmt.pix_mp; 786 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 787 struct v4l2_subdev_pad_config pad_cfg; 788 struct v4l2_subdev_state pad_state = { 789 .pads = &pad_cfg, 790 }; 791 const struct ceu_fmt *ceu_fmt; 792 u32 mbus_code_old; 793 u32 mbus_code; 794 int ret; 795 796 /* 797 * Set format on sensor sub device: bus format used to produce memory 798 * format is selected depending on YUV component ordering or 799 * at initialization time. 800 */ 801 struct v4l2_subdev_format sd_format = { 802 .which = V4L2_SUBDEV_FORMAT_TRY, 803 }; 804 805 mbus_code_old = ceu_sd->mbus_fmt.mbus_code; 806 807 switch (pix->pixelformat) { 808 case V4L2_PIX_FMT_YUYV: 809 mbus_code = MEDIA_BUS_FMT_YUYV8_2X8; 810 break; 811 case V4L2_PIX_FMT_UYVY: 812 mbus_code = MEDIA_BUS_FMT_UYVY8_2X8; 813 break; 814 case V4L2_PIX_FMT_YVYU: 815 mbus_code = MEDIA_BUS_FMT_YVYU8_2X8; 816 break; 817 case V4L2_PIX_FMT_VYUY: 818 mbus_code = MEDIA_BUS_FMT_VYUY8_2X8; 819 break; 820 case V4L2_PIX_FMT_NV16: 821 case V4L2_PIX_FMT_NV61: 822 case V4L2_PIX_FMT_NV12: 823 case V4L2_PIX_FMT_NV21: 824 mbus_code = ceu_sd->mbus_fmt.mbus_code; 825 break; 826 827 default: 828 pix->pixelformat = V4L2_PIX_FMT_NV16; 829 mbus_code = ceu_sd->mbus_fmt.mbus_code; 830 break; 831 } 832 833 ceu_fmt = get_ceu_fmt_from_fourcc(pix->pixelformat); 834 835 /* CFSZR requires height and width to be 4-pixel aligned. */ 836 v4l_bound_align_image(&pix->width, 2, CEU_MAX_WIDTH, 4, 837 &pix->height, 4, CEU_MAX_HEIGHT, 4, 0); 838 839 v4l2_fill_mbus_format_mplane(&sd_format.format, pix); 840 841 /* 842 * Try with the mbus_code matching YUYV components ordering first, 843 * if that one fails, fallback to default selected at initialization 844 * time. 845 */ 846 sd_format.format.code = mbus_code; 847 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, &pad_state, &sd_format); 848 if (ret) { 849 if (ret == -EINVAL) { 850 /* fallback */ 851 sd_format.format.code = mbus_code_old; 852 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, 853 &pad_state, &sd_format); 854 } 855 856 if (ret) 857 return ret; 858 } 859 860 /* Apply size returned by sensor as the CEU can't scale. */ 861 v4l2_fill_pix_format_mplane(pix, &sd_format.format); 862 863 /* Calculate per-plane sizes based on image format. */ 864 ceu_calc_plane_sizes(ceudev, ceu_fmt, pix); 865 866 /* Report to caller the configured mbus format. */ 867 *sd_mbus_code = sd_format.format.code; 868 869 return 0; 870 } 871 872 /* 873 * ceu_try_fmt() - Wrapper for __ceu_try_fmt; discard configured mbus_fmt 874 */ 875 static int ceu_try_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt) 876 { 877 u32 mbus_code; 878 879 return __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code); 880 } 881 882 /* 883 * ceu_set_fmt() - Apply the supplied format to both sensor and CEU 884 */ 885 static int ceu_set_fmt(struct ceu_device *ceudev, struct v4l2_format *v4l2_fmt) 886 { 887 struct ceu_subdev *ceu_sd = ceudev->sd; 888 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 889 u32 mbus_code; 890 int ret; 891 892 /* 893 * Set format on sensor sub device: bus format used to produce memory 894 * format is selected at initialization time. 895 */ 896 struct v4l2_subdev_format format = { 897 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 898 }; 899 900 ret = __ceu_try_fmt(ceudev, v4l2_fmt, &mbus_code); 901 if (ret) 902 return ret; 903 904 format.format.code = mbus_code; 905 v4l2_fill_mbus_format_mplane(&format.format, &v4l2_fmt->fmt.pix_mp); 906 ret = v4l2_subdev_call(v4l2_sd, pad, set_fmt, NULL, &format); 907 if (ret) 908 return ret; 909 910 ceudev->v4l2_pix = v4l2_fmt->fmt.pix_mp; 911 ceudev->field = V4L2_FIELD_NONE; 912 913 return 0; 914 } 915 916 /* 917 * ceu_set_default_fmt() - Apply default NV16 memory output format with VGA 918 * sizes. 919 */ 920 static int ceu_set_default_fmt(struct ceu_device *ceudev) 921 { 922 int ret; 923 924 struct v4l2_format v4l2_fmt = { 925 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, 926 .fmt.pix_mp = { 927 .width = VGA_WIDTH, 928 .height = VGA_HEIGHT, 929 .field = V4L2_FIELD_NONE, 930 .pixelformat = V4L2_PIX_FMT_NV16, 931 .num_planes = 2, 932 .plane_fmt = { 933 [0] = { 934 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2, 935 .bytesperline = VGA_WIDTH * 2, 936 }, 937 [1] = { 938 .sizeimage = VGA_WIDTH * VGA_HEIGHT * 2, 939 .bytesperline = VGA_WIDTH * 2, 940 }, 941 }, 942 }, 943 }; 944 945 ret = ceu_try_fmt(ceudev, &v4l2_fmt); 946 if (ret) 947 return ret; 948 949 ceudev->v4l2_pix = v4l2_fmt.fmt.pix_mp; 950 ceudev->field = V4L2_FIELD_NONE; 951 952 return 0; 953 } 954 955 /* 956 * ceu_init_mbus_fmt() - Query sensor for supported formats and initialize 957 * CEU media bus format used to produce memory formats. 958 * 959 * Find out if sensor can produce a permutation of 8-bits YUYV bus format. 960 * From a single 8-bits YUYV bus format the CEU can produce several memory 961 * output formats: 962 * - NV[12|21|16|61] through image fetch mode; 963 * - YUYV422 if sensor provides YUYV422 964 * 965 * TODO: Other YUYV422 permutations through data fetch sync mode and DTARY 966 * TODO: Binary data (eg. JPEG) and raw formats through data fetch sync mode 967 */ 968 static int ceu_init_mbus_fmt(struct ceu_device *ceudev) 969 { 970 struct ceu_subdev *ceu_sd = ceudev->sd; 971 struct ceu_mbus_fmt *mbus_fmt = &ceu_sd->mbus_fmt; 972 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 973 bool yuyv_bus_fmt = false; 974 975 struct v4l2_subdev_mbus_code_enum sd_mbus_fmt = { 976 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 977 .index = 0, 978 }; 979 980 /* Find out if sensor can produce any permutation of 8-bits YUYV422. */ 981 while (!yuyv_bus_fmt && 982 !v4l2_subdev_call(v4l2_sd, pad, enum_mbus_code, 983 NULL, &sd_mbus_fmt)) { 984 switch (sd_mbus_fmt.code) { 985 case MEDIA_BUS_FMT_YUYV8_2X8: 986 case MEDIA_BUS_FMT_YVYU8_2X8: 987 case MEDIA_BUS_FMT_UYVY8_2X8: 988 case MEDIA_BUS_FMT_VYUY8_2X8: 989 yuyv_bus_fmt = true; 990 break; 991 default: 992 /* 993 * Only support 8-bits YUYV bus formats at the moment; 994 * 995 * TODO: add support for binary formats (data sync 996 * fetch mode). 997 */ 998 break; 999 } 1000 1001 sd_mbus_fmt.index++; 1002 } 1003 1004 if (!yuyv_bus_fmt) 1005 return -ENXIO; 1006 1007 /* 1008 * Save the first encountered YUYV format as "mbus_fmt" and use it 1009 * to output all planar YUV422 and YUV420 (NV*) formats to memory as 1010 * well as for data synch fetch mode (YUYV - YVYU etc. ). 1011 */ 1012 mbus_fmt->mbus_code = sd_mbus_fmt.code; 1013 mbus_fmt->bps = 8; 1014 1015 /* Annotate the selected bus format components ordering. */ 1016 switch (sd_mbus_fmt.code) { 1017 case MEDIA_BUS_FMT_YUYV8_2X8: 1018 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YUYV; 1019 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YVYU; 1020 mbus_fmt->swapped = false; 1021 mbus_fmt->bpp = 16; 1022 break; 1023 1024 case MEDIA_BUS_FMT_YVYU8_2X8: 1025 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_YVYU; 1026 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_YUYV; 1027 mbus_fmt->swapped = true; 1028 mbus_fmt->bpp = 16; 1029 break; 1030 1031 case MEDIA_BUS_FMT_UYVY8_2X8: 1032 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_UYVY; 1033 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_VYUY; 1034 mbus_fmt->swapped = false; 1035 mbus_fmt->bpp = 16; 1036 break; 1037 1038 case MEDIA_BUS_FMT_VYUY8_2X8: 1039 mbus_fmt->fmt_order = CEU_CAMCR_DTARY_8_VYUY; 1040 mbus_fmt->fmt_order_swap = CEU_CAMCR_DTARY_8_UYVY; 1041 mbus_fmt->swapped = true; 1042 mbus_fmt->bpp = 16; 1043 break; 1044 } 1045 1046 return 0; 1047 } 1048 1049 /* --- Runtime PM Handlers --- */ 1050 1051 /* 1052 * ceu_runtime_resume() - soft-reset the interface and turn sensor power on. 1053 */ 1054 static int __maybe_unused ceu_runtime_resume(struct device *dev) 1055 { 1056 struct ceu_device *ceudev = dev_get_drvdata(dev); 1057 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 1058 1059 v4l2_subdev_call(v4l2_sd, core, s_power, 1); 1060 1061 ceu_soft_reset(ceudev); 1062 1063 return 0; 1064 } 1065 1066 /* 1067 * ceu_runtime_suspend() - disable capture and interrupts and soft-reset. 1068 * Turn sensor power off. 1069 */ 1070 static int __maybe_unused ceu_runtime_suspend(struct device *dev) 1071 { 1072 struct ceu_device *ceudev = dev_get_drvdata(dev); 1073 struct v4l2_subdev *v4l2_sd = ceudev->sd->v4l2_sd; 1074 1075 v4l2_subdev_call(v4l2_sd, core, s_power, 0); 1076 1077 ceu_write(ceudev, CEU_CEIER, 0); 1078 ceu_soft_reset(ceudev); 1079 1080 return 0; 1081 } 1082 1083 /* --- File Operations --- */ 1084 1085 static int ceu_open(struct file *file) 1086 { 1087 struct ceu_device *ceudev = video_drvdata(file); 1088 int ret; 1089 1090 ret = v4l2_fh_open(file); 1091 if (ret) 1092 return ret; 1093 1094 mutex_lock(&ceudev->mlock); 1095 /* Causes soft-reset and sensor power on on first open */ 1096 ret = pm_runtime_resume_and_get(ceudev->dev); 1097 mutex_unlock(&ceudev->mlock); 1098 1099 return ret; 1100 } 1101 1102 static int ceu_release(struct file *file) 1103 { 1104 struct ceu_device *ceudev = video_drvdata(file); 1105 1106 vb2_fop_release(file); 1107 1108 mutex_lock(&ceudev->mlock); 1109 /* Causes soft-reset and sensor power down on last close */ 1110 pm_runtime_put(ceudev->dev); 1111 mutex_unlock(&ceudev->mlock); 1112 1113 return 0; 1114 } 1115 1116 static const struct v4l2_file_operations ceu_fops = { 1117 .owner = THIS_MODULE, 1118 .open = ceu_open, 1119 .release = ceu_release, 1120 .unlocked_ioctl = video_ioctl2, 1121 .mmap = vb2_fop_mmap, 1122 .poll = vb2_fop_poll, 1123 }; 1124 1125 /* --- Video Device IOCTLs --- */ 1126 1127 static int ceu_querycap(struct file *file, void *priv, 1128 struct v4l2_capability *cap) 1129 { 1130 struct ceu_device *ceudev = video_drvdata(file); 1131 1132 strscpy(cap->card, "Renesas CEU", sizeof(cap->card)); 1133 strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver)); 1134 snprintf(cap->bus_info, sizeof(cap->bus_info), 1135 "platform:renesas-ceu-%s", dev_name(ceudev->dev)); 1136 1137 return 0; 1138 } 1139 1140 static int ceu_enum_fmt_vid_cap(struct file *file, void *priv, 1141 struct v4l2_fmtdesc *f) 1142 { 1143 const struct ceu_fmt *fmt; 1144 1145 if (f->index >= ARRAY_SIZE(ceu_fmt_list)) 1146 return -EINVAL; 1147 1148 fmt = &ceu_fmt_list[f->index]; 1149 f->pixelformat = fmt->fourcc; 1150 1151 return 0; 1152 } 1153 1154 static int ceu_try_fmt_vid_cap(struct file *file, void *priv, 1155 struct v4l2_format *f) 1156 { 1157 struct ceu_device *ceudev = video_drvdata(file); 1158 1159 return ceu_try_fmt(ceudev, f); 1160 } 1161 1162 static int ceu_s_fmt_vid_cap(struct file *file, void *priv, 1163 struct v4l2_format *f) 1164 { 1165 struct ceu_device *ceudev = video_drvdata(file); 1166 1167 if (vb2_is_streaming(&ceudev->vb2_vq)) 1168 return -EBUSY; 1169 1170 return ceu_set_fmt(ceudev, f); 1171 } 1172 1173 static int ceu_g_fmt_vid_cap(struct file *file, void *priv, 1174 struct v4l2_format *f) 1175 { 1176 struct ceu_device *ceudev = video_drvdata(file); 1177 1178 f->fmt.pix_mp = ceudev->v4l2_pix; 1179 1180 return 0; 1181 } 1182 1183 static int ceu_enum_input(struct file *file, void *priv, 1184 struct v4l2_input *inp) 1185 { 1186 struct ceu_device *ceudev = video_drvdata(file); 1187 struct ceu_subdev *ceusd; 1188 1189 if (inp->index >= ceudev->num_sd) 1190 return -EINVAL; 1191 1192 ceusd = ceudev->subdevs[inp->index]; 1193 1194 inp->type = V4L2_INPUT_TYPE_CAMERA; 1195 inp->std = 0; 1196 snprintf(inp->name, sizeof(inp->name), "Camera%u: %s", 1197 inp->index, ceusd->v4l2_sd->name); 1198 1199 return 0; 1200 } 1201 1202 static int ceu_g_input(struct file *file, void *priv, unsigned int *i) 1203 { 1204 struct ceu_device *ceudev = video_drvdata(file); 1205 1206 *i = ceudev->sd_index; 1207 1208 return 0; 1209 } 1210 1211 static int ceu_s_input(struct file *file, void *priv, unsigned int i) 1212 { 1213 struct ceu_device *ceudev = video_drvdata(file); 1214 struct ceu_subdev *ceu_sd_old; 1215 int ret; 1216 1217 if (i >= ceudev->num_sd) 1218 return -EINVAL; 1219 1220 if (vb2_is_streaming(&ceudev->vb2_vq)) 1221 return -EBUSY; 1222 1223 if (i == ceudev->sd_index) 1224 return 0; 1225 1226 ceu_sd_old = ceudev->sd; 1227 ceudev->sd = ceudev->subdevs[i]; 1228 1229 /* 1230 * Make sure we can generate output image formats and apply 1231 * default one. 1232 */ 1233 ret = ceu_init_mbus_fmt(ceudev); 1234 if (ret) { 1235 ceudev->sd = ceu_sd_old; 1236 return -EINVAL; 1237 } 1238 1239 ret = ceu_set_default_fmt(ceudev); 1240 if (ret) { 1241 ceudev->sd = ceu_sd_old; 1242 return -EINVAL; 1243 } 1244 1245 /* Now that we're sure we can use the sensor, power off the old one. */ 1246 v4l2_subdev_call(ceu_sd_old->v4l2_sd, core, s_power, 0); 1247 v4l2_subdev_call(ceudev->sd->v4l2_sd, core, s_power, 1); 1248 1249 ceudev->sd_index = i; 1250 1251 return 0; 1252 } 1253 1254 static int ceu_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1255 { 1256 struct ceu_device *ceudev = video_drvdata(file); 1257 1258 return v4l2_g_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a); 1259 } 1260 1261 static int ceu_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1262 { 1263 struct ceu_device *ceudev = video_drvdata(file); 1264 1265 return v4l2_s_parm_cap(video_devdata(file), ceudev->sd->v4l2_sd, a); 1266 } 1267 1268 static int ceu_enum_framesizes(struct file *file, void *fh, 1269 struct v4l2_frmsizeenum *fsize) 1270 { 1271 struct ceu_device *ceudev = video_drvdata(file); 1272 struct ceu_subdev *ceu_sd = ceudev->sd; 1273 const struct ceu_fmt *ceu_fmt; 1274 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 1275 int ret; 1276 1277 struct v4l2_subdev_frame_size_enum fse = { 1278 .code = ceu_sd->mbus_fmt.mbus_code, 1279 .index = fsize->index, 1280 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1281 }; 1282 1283 /* Just check if user supplied pixel format is supported. */ 1284 ceu_fmt = get_ceu_fmt_from_fourcc(fsize->pixel_format); 1285 if (!ceu_fmt) 1286 return -EINVAL; 1287 1288 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_size, 1289 NULL, &fse); 1290 if (ret) 1291 return ret; 1292 1293 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1294 fsize->discrete.width = CEU_W_MAX(fse.max_width); 1295 fsize->discrete.height = CEU_H_MAX(fse.max_height); 1296 1297 return 0; 1298 } 1299 1300 static int ceu_enum_frameintervals(struct file *file, void *fh, 1301 struct v4l2_frmivalenum *fival) 1302 { 1303 struct ceu_device *ceudev = video_drvdata(file); 1304 struct ceu_subdev *ceu_sd = ceudev->sd; 1305 const struct ceu_fmt *ceu_fmt; 1306 struct v4l2_subdev *v4l2_sd = ceu_sd->v4l2_sd; 1307 int ret; 1308 1309 struct v4l2_subdev_frame_interval_enum fie = { 1310 .code = ceu_sd->mbus_fmt.mbus_code, 1311 .index = fival->index, 1312 .width = fival->width, 1313 .height = fival->height, 1314 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1315 }; 1316 1317 /* Just check if user supplied pixel format is supported. */ 1318 ceu_fmt = get_ceu_fmt_from_fourcc(fival->pixel_format); 1319 if (!ceu_fmt) 1320 return -EINVAL; 1321 1322 ret = v4l2_subdev_call(v4l2_sd, pad, enum_frame_interval, NULL, 1323 &fie); 1324 if (ret) 1325 return ret; 1326 1327 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; 1328 fival->discrete = fie.interval; 1329 1330 return 0; 1331 } 1332 1333 static const struct v4l2_ioctl_ops ceu_ioctl_ops = { 1334 .vidioc_querycap = ceu_querycap, 1335 1336 .vidioc_enum_fmt_vid_cap = ceu_enum_fmt_vid_cap, 1337 .vidioc_try_fmt_vid_cap_mplane = ceu_try_fmt_vid_cap, 1338 .vidioc_s_fmt_vid_cap_mplane = ceu_s_fmt_vid_cap, 1339 .vidioc_g_fmt_vid_cap_mplane = ceu_g_fmt_vid_cap, 1340 1341 .vidioc_enum_input = ceu_enum_input, 1342 .vidioc_g_input = ceu_g_input, 1343 .vidioc_s_input = ceu_s_input, 1344 1345 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1346 .vidioc_querybuf = vb2_ioctl_querybuf, 1347 .vidioc_qbuf = vb2_ioctl_qbuf, 1348 .vidioc_expbuf = vb2_ioctl_expbuf, 1349 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1350 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1351 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1352 .vidioc_streamon = vb2_ioctl_streamon, 1353 .vidioc_streamoff = vb2_ioctl_streamoff, 1354 1355 .vidioc_g_parm = ceu_g_parm, 1356 .vidioc_s_parm = ceu_s_parm, 1357 .vidioc_enum_framesizes = ceu_enum_framesizes, 1358 .vidioc_enum_frameintervals = ceu_enum_frameintervals, 1359 1360 .vidioc_log_status = v4l2_ctrl_log_status, 1361 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1362 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1363 }; 1364 1365 /* 1366 * ceu_vdev_release() - release CEU video device memory when last reference 1367 * to this driver is closed 1368 */ 1369 static void ceu_vdev_release(struct video_device *vdev) 1370 { 1371 struct ceu_device *ceudev = video_get_drvdata(vdev); 1372 1373 kfree(ceudev); 1374 } 1375 1376 static int ceu_notify_bound(struct v4l2_async_notifier *notifier, 1377 struct v4l2_subdev *v4l2_sd, 1378 struct v4l2_async_subdev *asd) 1379 { 1380 struct v4l2_device *v4l2_dev = notifier->v4l2_dev; 1381 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev); 1382 struct ceu_subdev *ceu_sd = to_ceu_subdev(asd); 1383 1384 ceu_sd->v4l2_sd = v4l2_sd; 1385 ceudev->num_sd++; 1386 1387 return 0; 1388 } 1389 1390 static int ceu_notify_complete(struct v4l2_async_notifier *notifier) 1391 { 1392 struct v4l2_device *v4l2_dev = notifier->v4l2_dev; 1393 struct ceu_device *ceudev = v4l2_to_ceu(v4l2_dev); 1394 struct video_device *vdev = &ceudev->vdev; 1395 struct vb2_queue *q = &ceudev->vb2_vq; 1396 struct v4l2_subdev *v4l2_sd; 1397 int ret; 1398 1399 /* Initialize vb2 queue. */ 1400 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1401 q->io_modes = VB2_MMAP | VB2_DMABUF; 1402 q->drv_priv = ceudev; 1403 q->ops = &ceu_vb2_ops; 1404 q->mem_ops = &vb2_dma_contig_memops; 1405 q->buf_struct_size = sizeof(struct ceu_buffer); 1406 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1407 q->min_buffers_needed = 2; 1408 q->lock = &ceudev->mlock; 1409 q->dev = ceudev->v4l2_dev.dev; 1410 1411 ret = vb2_queue_init(q); 1412 if (ret) 1413 return ret; 1414 1415 /* 1416 * Make sure at least one sensor is primary and use it to initialize 1417 * ceu formats. 1418 */ 1419 if (!ceudev->sd) { 1420 ceudev->sd = ceudev->subdevs[0]; 1421 ceudev->sd_index = 0; 1422 } 1423 1424 v4l2_sd = ceudev->sd->v4l2_sd; 1425 1426 ret = ceu_init_mbus_fmt(ceudev); 1427 if (ret) 1428 return ret; 1429 1430 ret = ceu_set_default_fmt(ceudev); 1431 if (ret) 1432 return ret; 1433 1434 /* Register the video device. */ 1435 strscpy(vdev->name, DRIVER_NAME, sizeof(vdev->name)); 1436 vdev->v4l2_dev = v4l2_dev; 1437 vdev->lock = &ceudev->mlock; 1438 vdev->queue = &ceudev->vb2_vq; 1439 vdev->ctrl_handler = v4l2_sd->ctrl_handler; 1440 vdev->fops = &ceu_fops; 1441 vdev->ioctl_ops = &ceu_ioctl_ops; 1442 vdev->release = ceu_vdev_release; 1443 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1444 V4L2_CAP_STREAMING; 1445 video_set_drvdata(vdev, ceudev); 1446 1447 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1448 if (ret < 0) { 1449 v4l2_err(vdev->v4l2_dev, 1450 "video_register_device failed: %d\n", ret); 1451 return ret; 1452 } 1453 1454 return 0; 1455 } 1456 1457 static const struct v4l2_async_notifier_operations ceu_notify_ops = { 1458 .bound = ceu_notify_bound, 1459 .complete = ceu_notify_complete, 1460 }; 1461 1462 /* 1463 * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in 1464 * ceu device. Both DT and platform data parsing use 1465 * this routine. 1466 * 1467 * Returns 0 for success, -ENOMEM for failure. 1468 */ 1469 static int ceu_init_async_subdevs(struct ceu_device *ceudev, unsigned int n_sd) 1470 { 1471 /* Reserve memory for 'n_sd' ceu_subdev descriptors. */ 1472 ceudev->subdevs = devm_kcalloc(ceudev->dev, n_sd, 1473 sizeof(*ceudev->subdevs), GFP_KERNEL); 1474 if (!ceudev->subdevs) 1475 return -ENOMEM; 1476 1477 ceudev->sd = NULL; 1478 ceudev->sd_index = 0; 1479 ceudev->num_sd = 0; 1480 1481 return 0; 1482 } 1483 1484 /* 1485 * ceu_parse_platform_data() - Initialize async_subdevices using platform 1486 * device provided data. 1487 */ 1488 static int ceu_parse_platform_data(struct ceu_device *ceudev, 1489 const struct ceu_platform_data *pdata) 1490 { 1491 const struct ceu_async_subdev *async_sd; 1492 struct ceu_subdev *ceu_sd; 1493 unsigned int i; 1494 int ret; 1495 1496 if (pdata->num_subdevs == 0) 1497 return -ENODEV; 1498 1499 ret = ceu_init_async_subdevs(ceudev, pdata->num_subdevs); 1500 if (ret) 1501 return ret; 1502 1503 for (i = 0; i < pdata->num_subdevs; i++) { 1504 1505 /* Setup the ceu subdevice and the async subdevice. */ 1506 async_sd = &pdata->subdevs[i]; 1507 ceu_sd = v4l2_async_nf_add_i2c(&ceudev->notifier, 1508 async_sd->i2c_adapter_id, 1509 async_sd->i2c_address, 1510 struct ceu_subdev); 1511 if (IS_ERR(ceu_sd)) { 1512 v4l2_async_nf_cleanup(&ceudev->notifier); 1513 return PTR_ERR(ceu_sd); 1514 } 1515 ceu_sd->mbus_flags = async_sd->flags; 1516 ceudev->subdevs[i] = ceu_sd; 1517 } 1518 1519 return pdata->num_subdevs; 1520 } 1521 1522 /* 1523 * ceu_parse_dt() - Initialize async_subdevs parsing device tree graph. 1524 */ 1525 static int ceu_parse_dt(struct ceu_device *ceudev) 1526 { 1527 struct device_node *of = ceudev->dev->of_node; 1528 struct device_node *ep; 1529 struct ceu_subdev *ceu_sd; 1530 unsigned int i; 1531 int num_ep; 1532 int ret; 1533 1534 num_ep = of_graph_get_endpoint_count(of); 1535 if (!num_ep) 1536 return -ENODEV; 1537 1538 ret = ceu_init_async_subdevs(ceudev, num_ep); 1539 if (ret) 1540 return ret; 1541 1542 for (i = 0; i < num_ep; i++) { 1543 struct v4l2_fwnode_endpoint fw_ep = { 1544 .bus_type = V4L2_MBUS_PARALLEL, 1545 .bus = { 1546 .parallel = { 1547 .flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH | 1548 V4L2_MBUS_VSYNC_ACTIVE_HIGH, 1549 .bus_width = 8, 1550 }, 1551 }, 1552 }; 1553 1554 ep = of_graph_get_endpoint_by_regs(of, 0, i); 1555 if (!ep) { 1556 dev_err(ceudev->dev, 1557 "No subdevice connected on endpoint %u.\n", i); 1558 ret = -ENODEV; 1559 goto error_cleanup; 1560 } 1561 1562 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &fw_ep); 1563 if (ret) { 1564 dev_err(ceudev->dev, 1565 "Unable to parse endpoint #%u: %d.\n", i, ret); 1566 goto error_cleanup; 1567 } 1568 1569 /* Setup the ceu subdevice and the async subdevice. */ 1570 ceu_sd = v4l2_async_nf_add_fwnode_remote(&ceudev->notifier, 1571 of_fwnode_handle(ep), 1572 struct ceu_subdev); 1573 if (IS_ERR(ceu_sd)) { 1574 ret = PTR_ERR(ceu_sd); 1575 goto error_cleanup; 1576 } 1577 ceu_sd->mbus_flags = fw_ep.bus.parallel.flags; 1578 ceudev->subdevs[i] = ceu_sd; 1579 1580 of_node_put(ep); 1581 } 1582 1583 return num_ep; 1584 1585 error_cleanup: 1586 v4l2_async_nf_cleanup(&ceudev->notifier); 1587 of_node_put(ep); 1588 return ret; 1589 } 1590 1591 /* 1592 * struct ceu_data - Platform specific CEU data 1593 * @irq_mask: CETCR mask with all interrupt sources enabled. The mask differs 1594 * between SH4 and RZ platforms. 1595 */ 1596 struct ceu_data { 1597 u32 irq_mask; 1598 }; 1599 1600 static const struct ceu_data ceu_data_sh4 = { 1601 .irq_mask = CEU_CETCR_ALL_IRQS_SH4, 1602 }; 1603 1604 #if IS_ENABLED(CONFIG_OF) 1605 static const struct ceu_data ceu_data_rz = { 1606 .irq_mask = CEU_CETCR_ALL_IRQS_RZ, 1607 }; 1608 1609 static const struct of_device_id ceu_of_match[] = { 1610 { .compatible = "renesas,r7s72100-ceu", .data = &ceu_data_rz }, 1611 { .compatible = "renesas,r8a7740-ceu", .data = &ceu_data_rz }, 1612 { } 1613 }; 1614 MODULE_DEVICE_TABLE(of, ceu_of_match); 1615 #endif 1616 1617 static int ceu_probe(struct platform_device *pdev) 1618 { 1619 struct device *dev = &pdev->dev; 1620 const struct ceu_data *ceu_data; 1621 struct ceu_device *ceudev; 1622 unsigned int irq; 1623 int num_subdevs; 1624 int ret; 1625 1626 ceudev = kzalloc(sizeof(*ceudev), GFP_KERNEL); 1627 if (!ceudev) 1628 return -ENOMEM; 1629 1630 platform_set_drvdata(pdev, ceudev); 1631 ceudev->dev = dev; 1632 1633 INIT_LIST_HEAD(&ceudev->capture); 1634 spin_lock_init(&ceudev->lock); 1635 mutex_init(&ceudev->mlock); 1636 1637 ceudev->base = devm_platform_ioremap_resource(pdev, 0); 1638 if (IS_ERR(ceudev->base)) { 1639 ret = PTR_ERR(ceudev->base); 1640 goto error_free_ceudev; 1641 } 1642 1643 ret = platform_get_irq(pdev, 0); 1644 if (ret < 0) 1645 goto error_free_ceudev; 1646 irq = ret; 1647 1648 ret = devm_request_irq(dev, irq, ceu_irq, 1649 0, dev_name(dev), ceudev); 1650 if (ret) { 1651 dev_err(&pdev->dev, "Unable to request CEU interrupt.\n"); 1652 goto error_free_ceudev; 1653 } 1654 1655 pm_runtime_enable(dev); 1656 1657 ret = v4l2_device_register(dev, &ceudev->v4l2_dev); 1658 if (ret) 1659 goto error_pm_disable; 1660 1661 v4l2_async_nf_init(&ceudev->notifier); 1662 1663 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 1664 ceu_data = of_device_get_match_data(dev); 1665 num_subdevs = ceu_parse_dt(ceudev); 1666 } else if (dev->platform_data) { 1667 /* Assume SH4 if booting with platform data. */ 1668 ceu_data = &ceu_data_sh4; 1669 num_subdevs = ceu_parse_platform_data(ceudev, 1670 dev->platform_data); 1671 } else { 1672 num_subdevs = -EINVAL; 1673 } 1674 1675 if (num_subdevs < 0) { 1676 ret = num_subdevs; 1677 goto error_v4l2_unregister; 1678 } 1679 ceudev->irq_mask = ceu_data->irq_mask; 1680 1681 ceudev->notifier.v4l2_dev = &ceudev->v4l2_dev; 1682 ceudev->notifier.ops = &ceu_notify_ops; 1683 ret = v4l2_async_nf_register(&ceudev->v4l2_dev, &ceudev->notifier); 1684 if (ret) 1685 goto error_cleanup; 1686 1687 dev_info(dev, "Renesas Capture Engine Unit %s\n", dev_name(dev)); 1688 1689 return 0; 1690 1691 error_cleanup: 1692 v4l2_async_nf_cleanup(&ceudev->notifier); 1693 error_v4l2_unregister: 1694 v4l2_device_unregister(&ceudev->v4l2_dev); 1695 error_pm_disable: 1696 pm_runtime_disable(dev); 1697 error_free_ceudev: 1698 kfree(ceudev); 1699 1700 return ret; 1701 } 1702 1703 static void ceu_remove(struct platform_device *pdev) 1704 { 1705 struct ceu_device *ceudev = platform_get_drvdata(pdev); 1706 1707 pm_runtime_disable(ceudev->dev); 1708 1709 v4l2_async_nf_unregister(&ceudev->notifier); 1710 1711 v4l2_async_nf_cleanup(&ceudev->notifier); 1712 1713 v4l2_device_unregister(&ceudev->v4l2_dev); 1714 1715 video_unregister_device(&ceudev->vdev); 1716 } 1717 1718 static const struct dev_pm_ops ceu_pm_ops = { 1719 SET_RUNTIME_PM_OPS(ceu_runtime_suspend, 1720 ceu_runtime_resume, 1721 NULL) 1722 }; 1723 1724 static struct platform_driver ceu_driver = { 1725 .driver = { 1726 .name = DRIVER_NAME, 1727 .pm = &ceu_pm_ops, 1728 .of_match_table = of_match_ptr(ceu_of_match), 1729 }, 1730 .probe = ceu_probe, 1731 .remove_new = ceu_remove, 1732 }; 1733 1734 module_platform_driver(ceu_driver); 1735 1736 MODULE_DESCRIPTION("Renesas CEU camera driver"); 1737 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org>"); 1738 MODULE_LICENSE("GPL v2"); 1739