1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/math64.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/sys_soc.h> 19 #include <linux/units.h> 20 21 #include <media/mipi-csi2.h> 22 #include <media/v4l2-ctrls.h> 23 #include <media/v4l2-device.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-mc.h> 26 #include <media/v4l2-subdev.h> 27 28 struct rcar_csi2; 29 30 /* Register offsets and bits */ 31 32 /* Control Timing Select */ 33 #define TREF_REG 0x00 34 #define TREF_TREF BIT(0) 35 36 /* Software Reset */ 37 #define SRST_REG 0x04 38 #define SRST_SRST BIT(0) 39 40 /* PHY Operation Control */ 41 #define PHYCNT_REG 0x08 42 #define PHYCNT_SHUTDOWNZ BIT(17) 43 #define PHYCNT_RSTZ BIT(16) 44 #define PHYCNT_ENABLECLK BIT(4) 45 #define PHYCNT_ENABLE_3 BIT(3) 46 #define PHYCNT_ENABLE_2 BIT(2) 47 #define PHYCNT_ENABLE_1 BIT(1) 48 #define PHYCNT_ENABLE_0 BIT(0) 49 50 /* Checksum Control */ 51 #define CHKSUM_REG 0x0c 52 #define CHKSUM_ECC_EN BIT(1) 53 #define CHKSUM_CRC_EN BIT(0) 54 55 /* 56 * Channel Data Type Select 57 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 58 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 59 */ 60 #define VCDT_REG 0x10 61 #define VCDT2_REG 0x14 62 #define VCDT_VCDTN_EN BIT(15) 63 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 64 #define VCDT_SEL_DTN_ON BIT(6) 65 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 66 67 /* Frame Data Type Select */ 68 #define FRDT_REG 0x18 69 70 /* Field Detection Control */ 71 #define FLD_REG 0x1c 72 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 73 #define FLD_DET_SEL(n) (((n) & 0x3) << 4) 74 #define FLD_FLD_EN(ch) BIT(ch) 75 76 /* Automatic Standby Control */ 77 #define ASTBY_REG 0x20 78 79 /* Long Data Type Setting 0 */ 80 #define LNGDT0_REG 0x28 81 82 /* Long Data Type Setting 1 */ 83 #define LNGDT1_REG 0x2c 84 85 /* Interrupt Enable */ 86 #define INTEN_REG 0x30 87 #define INTEN_INT_AFIFO_OF BIT(27) 88 #define INTEN_INT_ERRSOTHS BIT(4) 89 #define INTEN_INT_ERRSOTSYNCHS BIT(3) 90 91 /* Interrupt Source Mask */ 92 #define INTCLOSE_REG 0x34 93 94 /* Interrupt Status Monitor */ 95 #define INTSTATE_REG 0x38 96 #define INTSTATE_INT_ULPS_START BIT(7) 97 #define INTSTATE_INT_ULPS_END BIT(6) 98 99 /* Interrupt Error Status Monitor */ 100 #define INTERRSTATE_REG 0x3c 101 102 /* Short Packet Data */ 103 #define SHPDAT_REG 0x40 104 105 /* Short Packet Count */ 106 #define SHPCNT_REG 0x44 107 108 /* LINK Operation Control */ 109 #define LINKCNT_REG 0x48 110 #define LINKCNT_MONITOR_EN BIT(31) 111 #define LINKCNT_REG_MONI_PACT_EN BIT(25) 112 #define LINKCNT_ICLK_NONSTOP BIT(24) 113 114 /* Lane Swap */ 115 #define LSWAP_REG 0x4c 116 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 117 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 118 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 119 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 120 121 /* PHY Test Interface Write Register */ 122 #define PHTW_REG 0x50 123 #define PHTW_DWEN BIT(24) 124 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 125 #define PHTW_CWEN BIT(8) 126 #define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 127 128 #define PHYFRX_REG 0x64 129 #define PHYFRX_FORCERX_MODE_3 BIT(3) 130 #define PHYFRX_FORCERX_MODE_2 BIT(2) 131 #define PHYFRX_FORCERX_MODE_1 BIT(1) 132 #define PHYFRX_FORCERX_MODE_0 BIT(0) 133 134 /* V4H BASE registers */ 135 #define V4H_N_LANES_REG 0x0004 136 #define V4H_CSI2_RESETN_REG 0x0008 137 138 #define V4H_PHY_MODE_REG 0x001c 139 #define V4H_PHY_MODE_DPHY 0 140 #define V4H_PHY_MODE_CPHY 1 141 142 #define V4H_PHY_SHUTDOWNZ_REG 0x0040 143 #define V4H_DPHY_RSTZ_REG 0x0044 144 #define V4H_FLDC_REG 0x0804 145 #define V4H_FLDD_REG 0x0808 146 #define V4H_IDIC_REG 0x0810 147 148 #define V4H_PHY_EN_REG 0x2000 149 #define V4H_PHY_EN_ENABLE_3 BIT(7) 150 #define V4H_PHY_EN_ENABLE_2 BIT(6) 151 #define V4H_PHY_EN_ENABLE_1 BIT(5) 152 #define V4H_PHY_EN_ENABLE_0 BIT(4) 153 #define V4H_PHY_EN_ENABLE_CLK BIT(0) 154 155 #define V4H_ST_PHYST_REG 0x2814 156 #define V4H_ST_PHYST_ST_PHY_READY BIT(31) 157 #define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3) 158 #define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2) 159 #define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1) 160 #define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0) 161 162 /* V4H PPI registers */ 163 #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */ 164 #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822 165 #define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c 166 #define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02 167 #define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04 168 #define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06 169 #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a 170 #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c 171 #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10 172 #define V4H_PPI_RW_DDLCAL_CFG_n_REG(n) (0x21c40 + ((n) * 2)) /* n = 0 - 7 */ 173 #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c 174 #define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80 175 #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0 176 177 /* V4H CORE registers */ 178 179 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, n) (0x22040 + ((l) * 0x400) + ((n) * 2)) 180 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_3_REG(l, n) (0x22060 + ((l) * 0x400) + ((n) * 2)) 181 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_4_REG(l, n) (0x22080 + ((l) * 0x400) + ((n) * 2)) 182 183 #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */ 184 #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */ 185 #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */ 186 #define V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG 0x23fe0 187 188 #define V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, n) (0x26000 + ((l) * 0x400) + ((n) * 2)) 189 #define V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, n) (0x26080 + ((l) * 0x400) + ((n) * 2)) 190 #define V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, n) (0x26100 + ((l) * 0x400) + ((n) * 2)) 191 #define V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(4, (n)) 192 #define V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(4, (n)) 193 194 /* V4H C-PHY */ 195 #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */ 196 #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */ 197 #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */ 198 #define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000 199 #define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080 200 #define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */ 201 #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400 202 #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480 203 #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */ 204 #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c 205 #define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800 206 #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880 207 #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */ 208 209 struct rcsi2_cphy_setting { 210 u16 msps; 211 u16 rx2; 212 u16 trio0; 213 u16 trio1; 214 u16 trio2; 215 u16 lane27; 216 u16 lane29; 217 }; 218 219 static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = { 220 { .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 }, 221 { .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 }, 222 { .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 }, 223 { .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 }, 224 { .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 }, 225 { .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 }, 226 { .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 }, 227 { .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 }, 228 { .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 }, 229 { .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 }, 230 { .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 }, 231 { .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 }, 232 { .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 }, 233 { .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 }, 234 { .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 235 { .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 236 { .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 237 { .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 238 { .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 239 { .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 240 { .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 241 { .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 242 { .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 243 { .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 244 { .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 245 { .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 }, 246 { .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 247 { .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 248 { .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 249 { .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 250 { .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 251 { .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 252 { .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 253 { .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 254 { .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 255 { .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 256 { /* sentinel */ }, 257 }; 258 259 /* V4M registers */ 260 #define V4M_OVR1_REG 0x0848 261 #define V4M_OVR1_FORCERXMODE_3 BIT(12) 262 #define V4M_OVR1_FORCERXMODE_2 BIT(11) 263 #define V4M_OVR1_FORCERXMODE_1 BIT(10) 264 #define V4M_OVR1_FORCERXMODE_0 BIT(9) 265 266 #define V4M_FRXM_REG 0x2004 267 #define V4M_FRXM_FORCERXMODE_3 BIT(3) 268 #define V4M_FRXM_FORCERXMODE_2 BIT(2) 269 #define V4M_FRXM_FORCERXMODE_1 BIT(1) 270 #define V4M_FRXM_FORCERXMODE_0 BIT(0) 271 272 #define V4M_PHYPLL_REG 0x02050 273 #define V4M_CSI0CLKFCPR_REG 0x02054 274 #define V4M_PHTW_REG 0x02060 275 #define V4M_PHTR_REG 0x02064 276 #define V4M_PHTC_REG 0x02068 277 278 struct phtw_value { 279 u8 data; 280 u8 code; 281 }; 282 283 struct rcsi2_mbps_info { 284 u16 mbps; 285 u8 reg; 286 u16 osc_freq; /* V4M */ 287 }; 288 289 static const struct rcsi2_mbps_info phtw_mbps_v3u[] = { 290 { .mbps = 1500, .reg = 0xcc }, 291 { .mbps = 1550, .reg = 0x1d }, 292 { .mbps = 1600, .reg = 0x27 }, 293 { .mbps = 1650, .reg = 0x30 }, 294 { .mbps = 1700, .reg = 0x39 }, 295 { .mbps = 1750, .reg = 0x42 }, 296 { .mbps = 1800, .reg = 0x4b }, 297 { .mbps = 1850, .reg = 0x55 }, 298 { .mbps = 1900, .reg = 0x5e }, 299 { .mbps = 1950, .reg = 0x67 }, 300 { .mbps = 2000, .reg = 0x71 }, 301 { .mbps = 2050, .reg = 0x79 }, 302 { .mbps = 2100, .reg = 0x83 }, 303 { .mbps = 2150, .reg = 0x8c }, 304 { .mbps = 2200, .reg = 0x95 }, 305 { .mbps = 2250, .reg = 0x9e }, 306 { .mbps = 2300, .reg = 0xa7 }, 307 { .mbps = 2350, .reg = 0xb0 }, 308 { .mbps = 2400, .reg = 0xba }, 309 { .mbps = 2450, .reg = 0xc3 }, 310 { .mbps = 2500, .reg = 0xcc }, 311 { /* sentinel */ }, 312 }; 313 314 static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = { 315 { .mbps = 80, .reg = 0x86 }, 316 { .mbps = 90, .reg = 0x86 }, 317 { .mbps = 100, .reg = 0x87 }, 318 { .mbps = 110, .reg = 0x87 }, 319 { .mbps = 120, .reg = 0x88 }, 320 { .mbps = 130, .reg = 0x88 }, 321 { .mbps = 140, .reg = 0x89 }, 322 { .mbps = 150, .reg = 0x89 }, 323 { .mbps = 160, .reg = 0x8a }, 324 { .mbps = 170, .reg = 0x8a }, 325 { .mbps = 180, .reg = 0x8b }, 326 { .mbps = 190, .reg = 0x8b }, 327 { .mbps = 205, .reg = 0x8c }, 328 { .mbps = 220, .reg = 0x8d }, 329 { .mbps = 235, .reg = 0x8e }, 330 { .mbps = 250, .reg = 0x8e }, 331 { /* sentinel */ }, 332 }; 333 334 static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = { 335 { .mbps = 80, .reg = 0x00 }, 336 { .mbps = 90, .reg = 0x20 }, 337 { .mbps = 100, .reg = 0x40 }, 338 { .mbps = 110, .reg = 0x02 }, 339 { .mbps = 130, .reg = 0x22 }, 340 { .mbps = 140, .reg = 0x42 }, 341 { .mbps = 150, .reg = 0x04 }, 342 { .mbps = 170, .reg = 0x24 }, 343 { .mbps = 180, .reg = 0x44 }, 344 { .mbps = 200, .reg = 0x06 }, 345 { .mbps = 220, .reg = 0x26 }, 346 { .mbps = 240, .reg = 0x46 }, 347 { .mbps = 250, .reg = 0x08 }, 348 { .mbps = 270, .reg = 0x28 }, 349 { .mbps = 300, .reg = 0x0a }, 350 { .mbps = 330, .reg = 0x2a }, 351 { .mbps = 360, .reg = 0x4a }, 352 { .mbps = 400, .reg = 0x0c }, 353 { .mbps = 450, .reg = 0x2c }, 354 { .mbps = 500, .reg = 0x0e }, 355 { .mbps = 550, .reg = 0x2e }, 356 { .mbps = 600, .reg = 0x10 }, 357 { .mbps = 650, .reg = 0x30 }, 358 { .mbps = 700, .reg = 0x12 }, 359 { .mbps = 750, .reg = 0x32 }, 360 { .mbps = 800, .reg = 0x52 }, 361 { .mbps = 850, .reg = 0x72 }, 362 { .mbps = 900, .reg = 0x14 }, 363 { .mbps = 950, .reg = 0x34 }, 364 { .mbps = 1000, .reg = 0x54 }, 365 { .mbps = 1050, .reg = 0x74 }, 366 { .mbps = 1125, .reg = 0x16 }, 367 { /* sentinel */ }, 368 }; 369 370 /* PHY Test Interface Clear */ 371 #define PHTC_REG 0x58 372 #define PHTC_TESTCLR BIT(0) 373 374 /* PHY Frequency Control */ 375 #define PHYPLL_REG 0x68 376 #define PHYPLL_HSFREQRANGE(n) ((n) << 16) 377 378 static const struct rcsi2_mbps_info hsfreqrange_v3u[] = { 379 { .mbps = 80, .reg = 0x00 }, 380 { .mbps = 90, .reg = 0x10 }, 381 { .mbps = 100, .reg = 0x20 }, 382 { .mbps = 110, .reg = 0x30 }, 383 { .mbps = 120, .reg = 0x01 }, 384 { .mbps = 130, .reg = 0x11 }, 385 { .mbps = 140, .reg = 0x21 }, 386 { .mbps = 150, .reg = 0x31 }, 387 { .mbps = 160, .reg = 0x02 }, 388 { .mbps = 170, .reg = 0x12 }, 389 { .mbps = 180, .reg = 0x22 }, 390 { .mbps = 190, .reg = 0x32 }, 391 { .mbps = 205, .reg = 0x03 }, 392 { .mbps = 220, .reg = 0x13 }, 393 { .mbps = 235, .reg = 0x23 }, 394 { .mbps = 250, .reg = 0x33 }, 395 { .mbps = 275, .reg = 0x04 }, 396 { .mbps = 300, .reg = 0x14 }, 397 { .mbps = 325, .reg = 0x25 }, 398 { .mbps = 350, .reg = 0x35 }, 399 { .mbps = 400, .reg = 0x05 }, 400 { .mbps = 450, .reg = 0x16 }, 401 { .mbps = 500, .reg = 0x26 }, 402 { .mbps = 550, .reg = 0x37 }, 403 { .mbps = 600, .reg = 0x07 }, 404 { .mbps = 650, .reg = 0x18 }, 405 { .mbps = 700, .reg = 0x28 }, 406 { .mbps = 750, .reg = 0x39 }, 407 { .mbps = 800, .reg = 0x09 }, 408 { .mbps = 850, .reg = 0x19 }, 409 { .mbps = 900, .reg = 0x29 }, 410 { .mbps = 950, .reg = 0x3a }, 411 { .mbps = 1000, .reg = 0x0a }, 412 { .mbps = 1050, .reg = 0x1a }, 413 { .mbps = 1100, .reg = 0x2a }, 414 { .mbps = 1150, .reg = 0x3b }, 415 { .mbps = 1200, .reg = 0x0b }, 416 { .mbps = 1250, .reg = 0x1b }, 417 { .mbps = 1300, .reg = 0x2b }, 418 { .mbps = 1350, .reg = 0x3c }, 419 { .mbps = 1400, .reg = 0x0c }, 420 { .mbps = 1450, .reg = 0x1c }, 421 { .mbps = 1500, .reg = 0x2c }, 422 { .mbps = 1550, .reg = 0x3d }, 423 { .mbps = 1600, .reg = 0x0d }, 424 { .mbps = 1650, .reg = 0x1d }, 425 { .mbps = 1700, .reg = 0x2e }, 426 { .mbps = 1750, .reg = 0x3e }, 427 { .mbps = 1800, .reg = 0x0e }, 428 { .mbps = 1850, .reg = 0x1e }, 429 { .mbps = 1900, .reg = 0x2f }, 430 { .mbps = 1950, .reg = 0x3f }, 431 { .mbps = 2000, .reg = 0x0f }, 432 { .mbps = 2050, .reg = 0x40 }, 433 { .mbps = 2100, .reg = 0x41 }, 434 { .mbps = 2150, .reg = 0x42 }, 435 { .mbps = 2200, .reg = 0x43 }, 436 { .mbps = 2300, .reg = 0x45 }, 437 { .mbps = 2350, .reg = 0x46 }, 438 { .mbps = 2400, .reg = 0x47 }, 439 { .mbps = 2450, .reg = 0x48 }, 440 { .mbps = 2500, .reg = 0x49 }, 441 { /* sentinel */ }, 442 }; 443 444 static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = { 445 { .mbps = 80, .reg = 0x00 }, 446 { .mbps = 90, .reg = 0x10 }, 447 { .mbps = 100, .reg = 0x20 }, 448 { .mbps = 110, .reg = 0x30 }, 449 { .mbps = 120, .reg = 0x01 }, 450 { .mbps = 130, .reg = 0x11 }, 451 { .mbps = 140, .reg = 0x21 }, 452 { .mbps = 150, .reg = 0x31 }, 453 { .mbps = 160, .reg = 0x02 }, 454 { .mbps = 170, .reg = 0x12 }, 455 { .mbps = 180, .reg = 0x22 }, 456 { .mbps = 190, .reg = 0x32 }, 457 { .mbps = 205, .reg = 0x03 }, 458 { .mbps = 220, .reg = 0x13 }, 459 { .mbps = 235, .reg = 0x23 }, 460 { .mbps = 250, .reg = 0x33 }, 461 { .mbps = 275, .reg = 0x04 }, 462 { .mbps = 300, .reg = 0x14 }, 463 { .mbps = 325, .reg = 0x25 }, 464 { .mbps = 350, .reg = 0x35 }, 465 { .mbps = 400, .reg = 0x05 }, 466 { .mbps = 450, .reg = 0x16 }, 467 { .mbps = 500, .reg = 0x26 }, 468 { .mbps = 550, .reg = 0x37 }, 469 { .mbps = 600, .reg = 0x07 }, 470 { .mbps = 650, .reg = 0x18 }, 471 { .mbps = 700, .reg = 0x28 }, 472 { .mbps = 750, .reg = 0x39 }, 473 { .mbps = 800, .reg = 0x09 }, 474 { .mbps = 850, .reg = 0x19 }, 475 { .mbps = 900, .reg = 0x29 }, 476 { .mbps = 950, .reg = 0x3a }, 477 { .mbps = 1000, .reg = 0x0a }, 478 { .mbps = 1050, .reg = 0x1a }, 479 { .mbps = 1100, .reg = 0x2a }, 480 { .mbps = 1150, .reg = 0x3b }, 481 { .mbps = 1200, .reg = 0x0b }, 482 { .mbps = 1250, .reg = 0x1b }, 483 { .mbps = 1300, .reg = 0x2b }, 484 { .mbps = 1350, .reg = 0x3c }, 485 { .mbps = 1400, .reg = 0x0c }, 486 { .mbps = 1450, .reg = 0x1c }, 487 { .mbps = 1500, .reg = 0x2c }, 488 { /* sentinel */ }, 489 }; 490 491 static const struct rcsi2_mbps_info hsfreqrange_m3w[] = { 492 { .mbps = 80, .reg = 0x00 }, 493 { .mbps = 90, .reg = 0x10 }, 494 { .mbps = 100, .reg = 0x20 }, 495 { .mbps = 110, .reg = 0x30 }, 496 { .mbps = 120, .reg = 0x01 }, 497 { .mbps = 130, .reg = 0x11 }, 498 { .mbps = 140, .reg = 0x21 }, 499 { .mbps = 150, .reg = 0x31 }, 500 { .mbps = 160, .reg = 0x02 }, 501 { .mbps = 170, .reg = 0x12 }, 502 { .mbps = 180, .reg = 0x22 }, 503 { .mbps = 190, .reg = 0x32 }, 504 { .mbps = 205, .reg = 0x03 }, 505 { .mbps = 220, .reg = 0x13 }, 506 { .mbps = 235, .reg = 0x23 }, 507 { .mbps = 250, .reg = 0x33 }, 508 { .mbps = 275, .reg = 0x04 }, 509 { .mbps = 300, .reg = 0x14 }, 510 { .mbps = 325, .reg = 0x05 }, 511 { .mbps = 350, .reg = 0x15 }, 512 { .mbps = 400, .reg = 0x25 }, 513 { .mbps = 450, .reg = 0x06 }, 514 { .mbps = 500, .reg = 0x16 }, 515 { .mbps = 550, .reg = 0x07 }, 516 { .mbps = 600, .reg = 0x17 }, 517 { .mbps = 650, .reg = 0x08 }, 518 { .mbps = 700, .reg = 0x18 }, 519 { .mbps = 750, .reg = 0x09 }, 520 { .mbps = 800, .reg = 0x19 }, 521 { .mbps = 850, .reg = 0x29 }, 522 { .mbps = 900, .reg = 0x39 }, 523 { .mbps = 950, .reg = 0x0a }, 524 { .mbps = 1000, .reg = 0x1a }, 525 { .mbps = 1050, .reg = 0x2a }, 526 { .mbps = 1100, .reg = 0x3a }, 527 { .mbps = 1150, .reg = 0x0b }, 528 { .mbps = 1200, .reg = 0x1b }, 529 { .mbps = 1250, .reg = 0x2b }, 530 { .mbps = 1300, .reg = 0x3b }, 531 { .mbps = 1350, .reg = 0x0c }, 532 { .mbps = 1400, .reg = 0x1c }, 533 { .mbps = 1450, .reg = 0x2c }, 534 { .mbps = 1500, .reg = 0x3c }, 535 { /* sentinel */ }, 536 }; 537 538 static const struct rcsi2_mbps_info hsfreqrange_v4m[] = { 539 { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 }, 540 { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 }, 541 { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 }, 542 { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 }, 543 { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 }, 544 { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 }, 545 { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 }, 546 { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 }, 547 { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 }, 548 { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 }, 549 { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 }, 550 { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 }, 551 { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 }, 552 { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 }, 553 { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 }, 554 { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 }, 555 { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 }, 556 { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 }, 557 { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 }, 558 { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 }, 559 { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 }, 560 { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 }, 561 { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 }, 562 { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 }, 563 { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 }, 564 { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 }, 565 { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 }, 566 { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 }, 567 { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 }, 568 { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 }, 569 { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 }, 570 { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 }, 571 { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 }, 572 { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 }, 573 { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 }, 574 { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 }, 575 { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 }, 576 { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 }, 577 { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 }, 578 { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 }, 579 { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 }, 580 { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 }, 581 { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 }, 582 { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 }, 583 { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 }, 584 { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 }, 585 { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 }, 586 { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a }, 587 { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 }, 588 { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b }, 589 { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 }, 590 { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c }, 591 { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 }, 592 { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d }, 593 { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 }, 594 { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e }, 595 { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 }, 596 { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f }, 597 { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 }, 598 { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 }, 599 { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 }, 600 { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 }, 601 { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 }, 602 { /* sentinel */ }, 603 }; 604 605 /* PHY ESC Error Monitor */ 606 #define PHEERM_REG 0x74 607 608 /* PHY Clock Lane Monitor */ 609 #define PHCLM_REG 0x78 610 #define PHCLM_STOPSTATECKL BIT(0) 611 612 /* PHY Data Lane Monitor */ 613 #define PHDLM_REG 0x7c 614 615 /* CSI0CLK Frequency Configuration Preset Register */ 616 #define CSI0CLKFCPR_REG 0x260 617 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 618 619 struct rcar_csi2_format { 620 u32 code; 621 unsigned int datatype; 622 unsigned int bpp; 623 }; 624 625 static const struct rcar_csi2_format rcar_csi2_formats[] = { 626 { 627 .code = MEDIA_BUS_FMT_RGB888_1X24, 628 .datatype = MIPI_CSI2_DT_RGB888, 629 .bpp = 24, 630 }, { 631 .code = MEDIA_BUS_FMT_UYVY8_1X16, 632 .datatype = MIPI_CSI2_DT_YUV422_8B, 633 .bpp = 16, 634 }, { 635 .code = MEDIA_BUS_FMT_YUYV8_1X16, 636 .datatype = MIPI_CSI2_DT_YUV422_8B, 637 .bpp = 16, 638 }, { 639 .code = MEDIA_BUS_FMT_UYVY8_2X8, 640 .datatype = MIPI_CSI2_DT_YUV422_8B, 641 .bpp = 16, 642 }, { 643 .code = MEDIA_BUS_FMT_YUYV10_2X10, 644 .datatype = MIPI_CSI2_DT_YUV422_8B, 645 .bpp = 20, 646 }, { 647 .code = MEDIA_BUS_FMT_Y8_1X8, 648 .datatype = MIPI_CSI2_DT_RAW8, 649 .bpp = 8, 650 }, { 651 .code = MEDIA_BUS_FMT_Y10_1X10, 652 .datatype = MIPI_CSI2_DT_RAW10, 653 .bpp = 10, 654 }, { 655 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 656 .datatype = MIPI_CSI2_DT_RAW8, 657 .bpp = 8, 658 }, { 659 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 660 .datatype = MIPI_CSI2_DT_RAW8, 661 .bpp = 8, 662 }, { 663 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 664 .datatype = MIPI_CSI2_DT_RAW8, 665 .bpp = 8, 666 }, { 667 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 668 .datatype = MIPI_CSI2_DT_RAW8, 669 .bpp = 8, 670 }, { 671 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 672 .datatype = MIPI_CSI2_DT_RAW10, 673 .bpp = 10, 674 }, { 675 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 676 .datatype = MIPI_CSI2_DT_RAW10, 677 .bpp = 10, 678 }, { 679 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 680 .datatype = MIPI_CSI2_DT_RAW10, 681 .bpp = 10, 682 }, { 683 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 684 .datatype = MIPI_CSI2_DT_RAW10, 685 .bpp = 10, 686 }, { 687 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 688 .datatype = MIPI_CSI2_DT_RAW12, 689 .bpp = 12, 690 }, { 691 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 692 .datatype = MIPI_CSI2_DT_RAW12, 693 .bpp = 12, 694 }, { 695 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 696 .datatype = MIPI_CSI2_DT_RAW12, 697 .bpp = 12, 698 }, { 699 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 700 .datatype = MIPI_CSI2_DT_RAW12, 701 .bpp = 12, 702 }, 703 }; 704 705 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 706 { 707 unsigned int i; 708 709 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 710 if (rcar_csi2_formats[i].code == code) 711 return &rcar_csi2_formats[i]; 712 713 return NULL; 714 } 715 716 struct rcsi2_cphy_line_order { 717 enum v4l2_mbus_csi2_cphy_line_orders_type order; 718 u16 cfg; 719 u16 ctrl29; 720 }; 721 722 static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = { 723 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ABC, .cfg = 0x0, .ctrl29 = 0x0 }, 724 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ACB, .cfg = 0xa, .ctrl29 = 0x1 }, 725 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BAC, .cfg = 0xc, .ctrl29 = 0x1 }, 726 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BCA, .cfg = 0x5, .ctrl29 = 0x0 }, 727 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CAB, .cfg = 0x3, .ctrl29 = 0x0 }, 728 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CBA, .cfg = 0x9, .ctrl29 = 0x1 } 729 }; 730 731 enum rcar_csi2_pads { 732 RCAR_CSI2_SINK, 733 RCAR_CSI2_SOURCE_VC0, 734 RCAR_CSI2_SOURCE_VC1, 735 RCAR_CSI2_SOURCE_VC2, 736 RCAR_CSI2_SOURCE_VC3, 737 NR_OF_RCAR_CSI2_PAD, 738 }; 739 740 struct rcsi2_register_layout { 741 unsigned int phtw; 742 unsigned int phypll; 743 }; 744 745 struct rcar_csi2_info { 746 const struct rcsi2_register_layout *regs; 747 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 748 int (*phy_post_init)(struct rcar_csi2 *priv); 749 int (*start_receiver)(struct rcar_csi2 *priv, 750 struct v4l2_subdev_state *state); 751 void (*enter_standby)(struct rcar_csi2 *priv); 752 const struct rcsi2_mbps_info *hsfreqrange; 753 unsigned int csi0clkfreqrange; 754 unsigned int num_channels; 755 bool clear_ulps; 756 bool use_isp; 757 bool support_dphy; 758 bool support_cphy; 759 }; 760 761 struct rcar_csi2 { 762 struct device *dev; 763 void __iomem *base; 764 const struct rcar_csi2_info *info; 765 struct reset_control *rstc; 766 767 struct v4l2_subdev subdev; 768 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 769 770 struct v4l2_async_notifier notifier; 771 struct v4l2_subdev *remote; 772 unsigned int remote_pad; 773 774 int channel_vc[4]; 775 776 int stream_count; 777 778 bool cphy; 779 unsigned short lanes; 780 unsigned char lane_swap[4]; 781 enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3]; 782 }; 783 784 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 785 { 786 return container_of(sd, struct rcar_csi2, subdev); 787 } 788 789 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 790 { 791 return container_of(n, struct rcar_csi2, notifier); 792 } 793 794 static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv) 795 { 796 /* Used together with R-Car ISP: one sink and one source pad. */ 797 if (priv->info->use_isp) 798 return 2; 799 800 /* Used together with R-Car VIN: one sink and four source pads. */ 801 return 5; 802 } 803 804 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 805 { 806 return ioread32(priv->base + reg); 807 } 808 809 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 810 { 811 iowrite32(data, priv->base + reg); 812 } 813 814 static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg) 815 { 816 return ioread16(priv->base + reg); 817 } 818 819 static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) 820 { 821 iowrite16(data, priv->base + reg); 822 } 823 824 static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask) 825 { 826 u16 val; 827 828 val = rcsi2_read16(priv, reg) & ~mask; 829 rcsi2_write16(priv, reg, val | data); 830 } 831 832 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) 833 { 834 unsigned int timeout; 835 836 rcsi2_write(priv, priv->info->regs->phtw, 837 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 838 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 839 840 /* Wait for DWEN and CWEN to be cleared by hardware. */ 841 for (timeout = 0; timeout <= 20; timeout++) { 842 if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) 843 return 0; 844 845 usleep_range(1000, 2000); 846 } 847 848 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 849 850 return -ETIMEDOUT; 851 } 852 853 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 854 const struct phtw_value *values, 855 unsigned int size) 856 { 857 int ret; 858 859 for (unsigned int i = 0; i < size; i++) { 860 ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); 861 if (ret) 862 return ret; 863 } 864 865 return 0; 866 } 867 868 static const struct rcsi2_mbps_info * 869 rcsi2_mbps_to_info(struct rcar_csi2 *priv, 870 const struct rcsi2_mbps_info *infotable, unsigned int mbps) 871 { 872 const struct rcsi2_mbps_info *info; 873 const struct rcsi2_mbps_info *prev = NULL; 874 875 if (mbps < infotable->mbps) 876 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", 877 mbps, infotable->mbps); 878 879 for (info = infotable; info->mbps != 0; info++) { 880 if (info->mbps >= mbps) 881 break; 882 prev = info; 883 } 884 885 if (!info->mbps) { 886 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 887 return NULL; 888 } 889 890 if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps))) 891 info = prev; 892 893 return info; 894 } 895 896 static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) 897 { 898 rcsi2_write(priv, PHYCNT_REG, 0); 899 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 900 } 901 902 static void rcsi2_enter_standby(struct rcar_csi2 *priv) 903 { 904 if (priv->info->enter_standby) 905 priv->info->enter_standby(priv); 906 907 reset_control_assert(priv->rstc); 908 usleep_range(100, 150); 909 pm_runtime_put(priv->dev); 910 } 911 912 static int rcsi2_exit_standby(struct rcar_csi2 *priv) 913 { 914 int ret; 915 916 ret = pm_runtime_resume_and_get(priv->dev); 917 if (ret < 0) 918 return ret; 919 920 reset_control_deassert(priv->rstc); 921 922 return 0; 923 } 924 925 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 926 unsigned int lanes) 927 { 928 unsigned int timeout; 929 930 /* Wait for the clock and data lanes to enter LP-11 state. */ 931 for (timeout = 0; timeout <= 20; timeout++) { 932 const u32 lane_mask = (1 << lanes) - 1; 933 934 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 935 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 936 return 0; 937 938 usleep_range(1000, 2000); 939 } 940 941 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 942 943 return -ETIMEDOUT; 944 } 945 946 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 947 { 948 const struct rcsi2_mbps_info *info; 949 950 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 951 if (!info) 952 return -ERANGE; 953 954 rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(info->reg)); 955 956 return 0; 957 } 958 959 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 960 unsigned int *lanes) 961 { 962 struct v4l2_mbus_config mbus_config = { 0 }; 963 int ret; 964 965 *lanes = priv->lanes; 966 967 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 968 priv->remote_pad, &mbus_config); 969 if (ret == -ENOIOCTLCMD) { 970 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 971 return 0; 972 } 973 974 if (ret) { 975 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 976 return ret; 977 } 978 979 switch (mbus_config.type) { 980 case V4L2_MBUS_CSI2_CPHY: 981 if (!priv->cphy) 982 return -EINVAL; 983 break; 984 case V4L2_MBUS_CSI2_DPHY: 985 if (priv->cphy) 986 return -EINVAL; 987 break; 988 default: 989 dev_err(priv->dev, "Unsupported media bus type %u\n", 990 mbus_config.type); 991 return -EINVAL; 992 } 993 994 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) { 995 dev_err(priv->dev, 996 "Unsupported mbus config: too many data lanes %u\n", 997 mbus_config.bus.mipi_csi2.num_data_lanes); 998 return -EINVAL; 999 } 1000 1001 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes; 1002 1003 return 0; 1004 } 1005 1006 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, 1007 struct v4l2_subdev_state *state) 1008 { 1009 struct media_pad *remote_pad; 1010 struct v4l2_subdev *source; 1011 s64 freq; 1012 u64 mbps; 1013 1014 if (!priv->remote) 1015 return -ENODEV; 1016 1017 source = priv->remote; 1018 remote_pad = &source->entity.pads[priv->remote_pad]; 1019 1020 /* 1021 * First try to get the real link freq. If that fails, try the heuristic 1022 * method with bpp and lanes (but that only works for one route). 1023 */ 1024 freq = v4l2_get_link_freq(remote_pad, 0, 0); 1025 if (freq < 0) { 1026 const struct rcar_csi2_format *format; 1027 const struct v4l2_mbus_framefmt *fmt; 1028 unsigned int lanes; 1029 unsigned int bpp; 1030 int ret; 1031 1032 ret = rcsi2_get_active_lanes(priv, &lanes); 1033 if (ret) 1034 return ret; 1035 1036 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1037 if (!fmt) 1038 return -EINVAL; 1039 1040 format = rcsi2_code_to_fmt(fmt->code); 1041 if (!format) 1042 return -EINVAL; 1043 1044 bpp = format->bpp; 1045 1046 freq = v4l2_get_link_freq(remote_pad, bpp, 2 * lanes); 1047 if (freq < 0) { 1048 int ret = (int)freq; 1049 1050 dev_err(priv->dev, "failed to get link freq for %s: %d\n", 1051 source->name, ret); 1052 1053 return ret; 1054 } 1055 } 1056 1057 mbps = div_u64(freq * 2, MEGA); 1058 1059 return mbps; 1060 } 1061 1062 static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv, 1063 struct v4l2_subdev_state *state) 1064 { 1065 const struct rcar_csi2_format *format; 1066 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 1067 const struct v4l2_mbus_framefmt *fmt; 1068 unsigned int lanes; 1069 unsigned int i; 1070 int mbps, ret; 1071 1072 /* Use the format on the sink pad to compute the receiver config. */ 1073 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1074 1075 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 1076 fmt->width, fmt->height, 1077 fmt->field == V4L2_FIELD_NONE ? 'p' : 'i'); 1078 1079 /* Code is validated in set_fmt. */ 1080 format = rcsi2_code_to_fmt(fmt->code); 1081 if (!format) 1082 return -EINVAL; 1083 1084 /* 1085 * Enable all supported CSI-2 channels with virtual channel and 1086 * data type matching. 1087 * 1088 * NOTE: It's not possible to get individual datatype for each 1089 * source virtual channel. Once this is possible in V4L2 1090 * it should be used here. 1091 */ 1092 for (i = 0; i < priv->info->num_channels; i++) { 1093 u32 vcdt_part; 1094 1095 if (priv->channel_vc[i] < 0) 1096 continue; 1097 1098 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN | 1099 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype); 1100 1101 /* Store in correct reg and offset. */ 1102 if (i < 2) 1103 vcdt |= vcdt_part << ((i % 2) * 16); 1104 else 1105 vcdt2 |= vcdt_part << ((i % 2) * 16); 1106 } 1107 1108 if (fmt->field == V4L2_FIELD_ALTERNATE) 1109 fld = FLD_DET_SEL(1) | FLD_FLD_EN(3) | FLD_FLD_EN(2) | 1110 FLD_FLD_EN(1) | FLD_FLD_EN(0); 1111 1112 /* 1113 * Get the number of active data lanes inspecting the remote mbus 1114 * configuration. 1115 */ 1116 ret = rcsi2_get_active_lanes(priv, &lanes); 1117 if (ret) 1118 return ret; 1119 1120 phycnt = PHYCNT_ENABLECLK; 1121 phycnt |= (1 << lanes) - 1; 1122 1123 mbps = rcsi2_calc_mbps(priv, state); 1124 if (mbps < 0) 1125 return mbps; 1126 1127 /* Enable interrupts. */ 1128 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 1129 | INTEN_INT_ERRSOTSYNCHS); 1130 1131 /* Init */ 1132 rcsi2_write(priv, TREF_REG, TREF_TREF); 1133 rcsi2_write(priv, PHTC_REG, 0); 1134 1135 /* Configure */ 1136 if (!priv->info->use_isp) { 1137 rcsi2_write(priv, VCDT_REG, vcdt); 1138 if (vcdt2) 1139 rcsi2_write(priv, VCDT2_REG, vcdt2); 1140 } 1141 1142 /* Lanes are zero indexed. */ 1143 rcsi2_write(priv, LSWAP_REG, 1144 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 1145 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 1146 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 1147 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 1148 1149 /* Start */ 1150 if (priv->info->init_phtw) { 1151 ret = priv->info->init_phtw(priv, mbps); 1152 if (ret) 1153 return ret; 1154 } 1155 1156 if (priv->info->hsfreqrange) { 1157 ret = rcsi2_set_phypll(priv, mbps); 1158 if (ret) 1159 return ret; 1160 } 1161 1162 if (priv->info->csi0clkfreqrange) 1163 rcsi2_write(priv, CSI0CLKFCPR_REG, 1164 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1165 1166 if (priv->info->use_isp) 1167 rcsi2_write(priv, PHYFRX_REG, 1168 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 | 1169 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0); 1170 1171 rcsi2_write(priv, PHYCNT_REG, phycnt); 1172 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 1173 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 1174 rcsi2_write(priv, FLD_REG, fld); 1175 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 1176 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 1177 1178 ret = rcsi2_wait_phy_start(priv, lanes); 1179 if (ret) 1180 return ret; 1181 1182 if (priv->info->use_isp) 1183 rcsi2_write(priv, PHYFRX_REG, 0); 1184 1185 /* Run post PHY start initialization, if needed. */ 1186 if (priv->info->phy_post_init) { 1187 ret = priv->info->phy_post_init(priv); 1188 if (ret) 1189 return ret; 1190 } 1191 1192 /* Clear Ultra Low Power interrupt. */ 1193 if (priv->info->clear_ulps) 1194 rcsi2_write(priv, INTSTATE_REG, 1195 INTSTATE_INT_ULPS_START | 1196 INTSTATE_INT_ULPS_END); 1197 return 0; 1198 } 1199 1200 static void rsci2_set_line_order(struct rcar_csi2 *priv, 1201 enum v4l2_mbus_csi2_cphy_line_orders_type order, 1202 unsigned int cfgreg, unsigned int ctrlreg) 1203 { 1204 const struct rcsi2_cphy_line_order *info = NULL; 1205 1206 for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) { 1207 if (rcsi2_cphy_line_orders[i].order == order) { 1208 info = &rcsi2_cphy_line_orders[i]; 1209 break; 1210 } 1211 } 1212 1213 if (!info) 1214 return; 1215 1216 rcsi2_modify16(priv, cfgreg, info->cfg, 0x000f); 1217 rcsi2_modify16(priv, ctrlreg, info->ctrl29, 0x0100); 1218 } 1219 1220 static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match) 1221 { 1222 unsigned int timeout; 1223 u32 status; 1224 1225 for (timeout = 0; timeout <= 10; timeout++) { 1226 status = rcsi2_read(priv, V4H_ST_PHYST_REG); 1227 if ((status & match) == match) 1228 return 0; 1229 1230 usleep_range(1000, 2000); 1231 } 1232 1233 return -ETIMEDOUT; 1234 } 1235 1236 static const struct rcsi2_cphy_setting * 1237 rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) 1238 { 1239 const struct rcsi2_cphy_setting *conf; 1240 int msps; 1241 1242 /* Adjust for C-PHY symbols, divide by 2.8. */ 1243 msps = div_u64(mbps * 5, 14); 1244 1245 for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) { 1246 if (conf->msps > msps) 1247 break; 1248 } 1249 1250 if (!conf->msps) { 1251 dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", msps); 1252 return NULL; 1253 } 1254 1255 /* C-PHY specific */ 1256 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155); 1257 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068); 1258 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010); 1259 1260 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c); 1261 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c); 1262 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c); 1263 1264 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5); 1265 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5); 1266 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5); 1267 1268 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013); 1269 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013); 1270 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013); 1271 1272 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013); 1273 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013); 1274 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013); 1275 1276 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a); 1277 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a); 1278 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a); 1279 1280 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(2), conf->rx2); 1281 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2); 1282 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2); 1283 1284 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x0001); 1285 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0); 1286 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x0001); 1287 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x0001); 1288 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0); 1289 1290 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0); 1291 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0); 1292 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0); 1293 1294 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(2), conf->trio2); 1295 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(2), conf->trio2); 1296 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(2), conf->trio2); 1297 1298 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(1), conf->trio1); 1299 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1); 1300 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1); 1301 1302 /* Configure data line order. */ 1303 rsci2_set_line_order(priv, priv->line_orders[0], 1304 V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG, 1305 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 9)); 1306 rsci2_set_line_order(priv, priv->line_orders[1], 1307 V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, 1308 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 9)); 1309 rsci2_set_line_order(priv, priv->line_orders[2], 1310 V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG, 1311 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 9)); 1312 1313 /* TODO: This registers is not documented. */ 1314 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000); 1315 1316 return conf; 1317 } 1318 1319 struct rcsi2_d_phy_setting_v4h_lut_value { 1320 unsigned int mbps; 1321 unsigned char cfg_1; 1322 unsigned char cfg_5_94; 1323 unsigned char cfg_5_30; 1324 unsigned char lane_ctrl_2_8; 1325 unsigned char rw_hs_rx_3_83; 1326 unsigned char rw_hs_rx_3_20; 1327 unsigned char rw_hs_rx_6; 1328 unsigned char rw_hs_rx_1; 1329 }; 1330 1331 static const struct rcsi2_d_phy_setting_v4h_lut_value * 1332 rcsi2_d_phy_setting_v4h_lut_lookup(int mbps) 1333 { 1334 static const struct rcsi2_d_phy_setting_v4h_lut_value values[] = { 1335 { 4500, 0x3f, 0x07, 0x00, 0x01, 0x02, 0x01, 0x0d, 0x10 }, 1336 { 4000, 0x47, 0x08, 0x01, 0x01, 0x05, 0x01, 0x0f, 0x0d }, 1337 { 3600, 0x4f, 0x09, 0x01, 0x01, 0x06, 0x01, 0x10, 0x0b }, 1338 { 3230, 0x57, 0x0a, 0x01, 0x01, 0x06, 0x01, 0x12, 0x09 }, 1339 { 3000, 0x47, 0x08, 0x00, 0x00, 0x03, 0x01, 0x0f, 0x0c }, 1340 { 2700, 0x4f, 0x09, 0x01, 0x00, 0x06, 0x01, 0x10, 0x0b }, 1341 { 2455, 0x57, 0x0a, 0x01, 0x00, 0x06, 0x01, 0x12, 0x09 }, 1342 { 2250, 0x5f, 0x0b, 0x01, 0x00, 0x08, 0x01, 0x13, 0x08 }, 1343 { 2077, 0x67, 0x0c, 0x01, 0x00, 0x06, 0x02, 0x15, 0x0d }, 1344 { 1929, 0x6f, 0x0d, 0x02, 0x00, 0x06, 0x02, 0x17, 0x0d }, 1345 { 1800, 0x77, 0x0e, 0x02, 0x00, 0x06, 0x02, 0x18, 0x0d }, 1346 { 1688, 0x7f, 0x0f, 0x02, 0x00, 0x08, 0x02, 0x1a, 0x0d }, 1347 { 1588, 0x87, 0x10, 0x02, 0x00, 0x08, 0x02, 0x1b, 0x0d }, 1348 { 1500, 0x8f, 0x11, 0x03, 0x00, 0x08, 0x02, 0x1d, 0x0c }, 1349 }; 1350 1351 for (unsigned int i = 0; i < ARRAY_SIZE(values); i++) 1352 if (mbps >= values[i].mbps) 1353 return &values[i]; 1354 1355 return NULL; 1356 } 1357 1358 static int rcsi2_d_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) 1359 { 1360 const struct rcsi2_d_phy_setting_v4h_lut_value *lut = 1361 rcsi2_d_phy_setting_v4h_lut_lookup(mbps); 1362 u16 val; 1363 1364 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0000); 1365 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), mbps > 1500 ? 0x0028 : 0x0068); 1366 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0050); 1367 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(0), 0x0063); 1368 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(7), 0x1132); 1369 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(1), 0x1340); 1370 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(2), 0x4b13); 1371 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(4), 0x000a); 1372 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(6), 0x800a); 1373 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(7), 0x1109); 1374 1375 if (mbps > 1500) { 1376 val = DIV_ROUND_UP(5 * mbps, 64); 1377 rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(3), val); 1378 } 1379 1380 if (lut) { 1381 rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(1), 1382 lut->cfg_1, 0x00ff); 1383 rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(5), 1384 lut->cfg_5_94 << 4, 0x03f0); 1385 rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(5), 1386 lut->cfg_5_30 << 0, 0x000f); 1387 1388 for (unsigned int l = 0; l < 5; l++) 1389 rcsi2_modify16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 8), 1390 lut->lane_ctrl_2_8 << 12, 0x1000); 1391 } 1392 1393 for (unsigned int l = 0; l < 4; l++) 1394 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, 0), 0x463c); 1395 1396 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x0000); 1397 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0x0000); 1398 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x0001); 1399 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x0000); 1400 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0x0000); 1401 1402 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(6), 0x0009); 1403 1404 val = mbps > 1500 ? 0x0800 : 0x0802; 1405 for (unsigned int l = 0; l < 5; l++) 1406 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 12), val); 1407 1408 val = mbps > 1500 ? 0x0000 : 0x0002; 1409 for (unsigned int l = 0; l < 5; l++) 1410 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 13), val); 1411 1412 if (mbps >= 80) { 1413 /* 2560: 6, 1280: 5, 640: 4, 320: 3, 160: 2, 80: 1 */ 1414 val = ilog2(mbps / 80) + 1; 1415 rcsi2_modify16(priv, 1416 V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 9), 1417 val << 5, 0xe0); 1418 } 1419 1420 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(0), 0x091c); 1421 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(7), 0x3b06); 1422 1423 val = DIV_ROUND_UP(1200, mbps) + 12; 1424 for (unsigned int l = 0; l < 4; l++) 1425 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 0), val << 8, 0xf0); 1426 1427 val = mbps > 1500 ? 0x0004 : 0x0008; 1428 for (unsigned int l = 0; l < 4; l++) 1429 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, 1), val); 1430 1431 val = mbps > 2500 ? 0x669a : mbps > 1500 ? 0xe69a : 0xe69b; 1432 for (unsigned int l = 0; l < 4; l++) 1433 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 2), val); 1434 1435 for (unsigned int l = 0; l < 4; l++) 1436 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, 0), 0x163c); 1437 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(0), 0x163c); 1438 1439 if (lut) { 1440 for (unsigned int l = 0; l < 4; l++) 1441 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 1), 1442 lut->rw_hs_rx_1, 0xff); 1443 } 1444 1445 for (unsigned int l = 0; l < 4; l++) 1446 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 3), 0x9209); 1447 1448 for (unsigned int l = 0; l < 4; l++) 1449 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 4), 0x0096); 1450 1451 for (unsigned int l = 0; l < 4; l++) 1452 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 5), 0x0100); 1453 1454 for (unsigned int l = 0; l < 4; l++) 1455 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 6), 0x2d02); 1456 1457 for (unsigned int l = 0; l < 4; l++) 1458 rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 7), 0x1b06); 1459 1460 if (lut) { 1461 /* 1462 * Documentation LUT have two values but document writing both 1463 * values in a single write. 1464 */ 1465 for (unsigned int l = 0; l < 4; l++) 1466 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 3), 1467 lut->rw_hs_rx_3_83 << 3 | lut->rw_hs_rx_3_20, 0x1ff); 1468 1469 for (unsigned int l = 0; l < 4; l++) 1470 rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 6), 1471 lut->rw_hs_rx_6 << 8, 0xff00); 1472 } 1473 1474 static const u16 deskew_fine[] = { 1475 0x0404, 0x040c, 0x0414, 0x041c, 0x0423, 0x0429, 0x0430, 0x043a, 1476 0x0445, 0x044a, 0x0450, 0x045a, 0x0465, 0x0469, 0x0472, 0x047a, 1477 0x0485, 0x0489, 0x0490, 0x049a, 0x04a4, 0x04ac, 0x04b4, 0x04bc, 1478 0x04c4, 0x04cc, 0x04d4, 0x04dc, 0x04e4, 0x04ec, 0x04f4, 0x04fc, 1479 0x0504, 0x050c, 0x0514, 0x051c, 0x0523, 0x0529, 0x0530, 0x053a, 1480 0x0545, 0x054a, 0x0550, 0x055a, 0x0565, 0x0569, 0x0572, 0x057a, 1481 0x0585, 0x0589, 0x0590, 0x059a, 0x05a4, 0x05ac, 0x05b4, 0x05bc, 1482 0x05c4, 0x05cc, 0x05d4, 0x05dc, 0x05e4, 0x05ec, 0x05f4, 0x05fc, 1483 0x0604, 0x060c, 0x0614, 0x061c, 0x0623, 0x0629, 0x0632, 0x063a, 1484 0x0645, 0x064a, 0x0650, 0x065a, 0x0665, 0x0669, 0x0672, 0x067a, 1485 0x0685, 0x0689, 0x0690, 0x069a, 0x06a4, 0x06ac, 0x06b4, 0x06bc, 1486 0x06c4, 0x06cc, 0x06d4, 0x06dc, 0x06e4, 0x06ec, 0x06f4, 0x06fc, 1487 0x0704, 0x070c, 0x0714, 0x071c, 0x0723, 0x072a, 0x0730, 0x073a, 1488 0x0745, 0x074a, 0x0750, 0x075a, 0x0765, 0x0769, 0x0772, 0x077a, 1489 0x0785, 0x0789, 0x0790, 0x079a, 0x07a4, 0x07ac, 0x07b4, 0x07bc, 1490 0x07c4, 0x07cc, 0x07d4, 0x07dc, 0x07e4, 0x07ec, 0x07f4, 0x07fc, 1491 }; 1492 1493 for (unsigned int i = 0; i < ARRAY_SIZE(deskew_fine); i++) { 1494 rcsi2_write16(priv, V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG, 1495 deskew_fine[i]); 1496 } 1497 1498 return 0; 1499 } 1500 1501 static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, 1502 struct v4l2_subdev_state *state) 1503 { 1504 const struct rcsi2_cphy_setting *cphy = NULL; 1505 unsigned int lanes; 1506 int mbps; 1507 int ret; 1508 1509 ret = rcsi2_get_active_lanes(priv, &lanes); 1510 if (ret) 1511 return ret; 1512 1513 mbps = rcsi2_calc_mbps(priv, state); 1514 if (mbps < 0) 1515 return mbps; 1516 1517 /* T0: Reset LINK and PHY*/ 1518 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1519 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1520 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1521 1522 /* T1: PHY static setting */ 1523 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | 1524 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | 1525 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); 1526 rcsi2_write(priv, V4H_FLDC_REG, 0); 1527 rcsi2_write(priv, V4H_FLDD_REG, 0); 1528 rcsi2_write(priv, V4H_IDIC_REG, 0); 1529 rcsi2_write(priv, V4H_PHY_MODE_REG, 1530 priv->cphy ? V4H_PHY_MODE_CPHY : V4H_PHY_MODE_DPHY); 1531 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1532 1533 rcsi2_write(priv, V4M_FRXM_REG, 1534 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | 1535 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); 1536 rcsi2_write(priv, V4M_OVR1_REG, 1537 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | 1538 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); 1539 1540 /* T2: Reset CSI2 */ 1541 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1542 1543 /* Registers static setting through APB */ 1544 /* Common setting */ 1545 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(10), 0x0030); 1546 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(2), 0x1444); 1547 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd); 1548 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233); 1549 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027); 1550 rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4); 1551 rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013); 1552 rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003); 1553 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f); 1554 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320); 1555 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f); 1556 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18); 1557 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c); 1558 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105); 1559 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000); 1560 rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); 1561 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(0), 0x0000); 1562 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(1), 0x0400); 1563 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(3), 0x41f6); 1564 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(0), 0x0000); 1565 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(3), 0x43f6); 1566 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x3000); 1567 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(7), 0x0000); 1568 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x7000); 1569 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(7), 0x0000); 1570 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(5), 0x4000); 1571 1572 /* T3: PHY settings */ 1573 if (priv->cphy) { 1574 cphy = rcsi2_c_phy_setting_v4h(priv, mbps); 1575 if (!cphy) 1576 return -ERANGE; 1577 } else { 1578 ret = rcsi2_d_phy_setting_v4h(priv, mbps); 1579 if (ret) 1580 return ret; 1581 } 1582 1583 /* T4: Leave Shutdown mode */ 1584 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1585 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1586 1587 /* T5: Wait for calibration */ 1588 if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) { 1589 dev_err(priv->dev, "PHY calibration failed\n"); 1590 return -ETIMEDOUT; 1591 } 1592 1593 /* T6: Analog programming */ 1594 if (priv->cphy) { 1595 for (unsigned int l = 0; l < 3; l++) { 1596 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), 1597 cphy->lane29); 1598 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 7), 1599 cphy->lane27); 1600 } 1601 } else { 1602 u16 val_2_9 = mbps > 2500 ? 0x14 : mbps > 1500 ? 0x04 : 0x00; 1603 u16 val_2_15 = mbps > 1500 ? 0x03 : 0x00; 1604 1605 for (unsigned int l = 0; l < 5; l++) { 1606 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), 1607 val_2_9); 1608 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 15), 1609 val_2_15); 1610 } 1611 } 1612 1613 /* T7: Wait for stop state */ 1614 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1615 V4H_ST_PHYST_ST_STOPSTATE_1 | 1616 V4H_ST_PHYST_ST_STOPSTATE_2 | 1617 V4H_ST_PHYST_ST_STOPSTATE_3); 1618 1619 /* T8: De-assert FRXM */ 1620 rcsi2_write(priv, V4M_FRXM_REG, 0); 1621 1622 return 0; 1623 } 1624 1625 static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int mbps) 1626 { 1627 unsigned int timeout; 1628 int ret; 1629 1630 static const struct phtw_value step1[] = { 1631 { .data = 0x00, .code = 0x00 }, 1632 { .data = 0x00, .code = 0x1e }, 1633 }; 1634 1635 /* Shutdown and reset PHY. */ 1636 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1637 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1638 1639 /* Start internal calibration (POR). */ 1640 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1641 if (ret) 1642 return ret; 1643 1644 /* Wait for POR to complete. */ 1645 for (timeout = 10; timeout > 0; timeout--) { 1646 if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000) 1647 break; 1648 usleep_range(1000, 2000); 1649 } 1650 1651 if (!timeout) { 1652 dev_err(priv->dev, "D-PHY calibration failed\n"); 1653 return -ETIMEDOUT; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps) 1660 { 1661 const struct rcsi2_mbps_info *info; 1662 struct phtw_value steps[] = { 1663 { .data = 0x00, .code = 0x00 }, 1664 { .code = 0xe2 }, /* Data filled in below. */ 1665 { .code = 0xe3 }, /* Data filled in below. */ 1666 { .data = 0x01, .code = 0xe4 }, 1667 }; 1668 1669 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 1670 if (!info) 1671 return -ERANGE; 1672 1673 /* Fill in data for command. */ 1674 steps[1].data = (info->osc_freq & 0x00ff) >> 0; 1675 steps[2].data = (info->osc_freq & 0x0f00) >> 8; 1676 1677 return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps)); 1678 } 1679 1680 static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps) 1681 { 1682 int ret; 1683 1684 static const struct phtw_value step1[] = { 1685 { .data = 0x00, .code = 0x00 }, 1686 { .data = 0x3c, .code = 0x08 }, 1687 }; 1688 1689 static const struct phtw_value step2[] = { 1690 { .data = 0x00, .code = 0x00 }, 1691 { .data = 0x80, .code = 0xe0 }, 1692 { .data = 0x31, .code = 0xe1 }, 1693 { .data = 0x06, .code = 0x00 }, 1694 { .data = 0x11, .code = 0x11 }, 1695 { .data = 0x08, .code = 0x00 }, 1696 { .data = 0x11, .code = 0x11 }, 1697 { .data = 0x0a, .code = 0x00 }, 1698 { .data = 0x11, .code = 0x11 }, 1699 { .data = 0x0c, .code = 0x00 }, 1700 { .data = 0x11, .code = 0x11 }, 1701 { .data = 0x01, .code = 0x00 }, 1702 { .data = 0x31, .code = 0xaa }, 1703 { .data = 0x05, .code = 0x00 }, 1704 { .data = 0x05, .code = 0x09 }, 1705 { .data = 0x07, .code = 0x00 }, 1706 { .data = 0x05, .code = 0x09 }, 1707 { .data = 0x09, .code = 0x00 }, 1708 { .data = 0x05, .code = 0x09 }, 1709 { .data = 0x0b, .code = 0x00 }, 1710 { .data = 0x05, .code = 0x09 }, 1711 }; 1712 1713 static const struct phtw_value step3[] = { 1714 { .data = 0x01, .code = 0x00 }, 1715 { .data = 0x06, .code = 0xab }, 1716 }; 1717 1718 if (priv->info->hsfreqrange) { 1719 ret = rcsi2_set_phypll(priv, mbps); 1720 if (ret) 1721 return ret; 1722 1723 ret = rcsi2_set_osc_freq(priv, mbps); 1724 if (ret) 1725 return ret; 1726 } 1727 1728 if (mbps <= 1500) { 1729 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1730 if (ret) 1731 return ret; 1732 } 1733 1734 if (priv->info->csi0clkfreqrange) 1735 rcsi2_write(priv, V4M_CSI0CLKFCPR_REG, 1736 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1737 1738 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | 1739 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | 1740 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); 1741 1742 if (mbps > 1500) { 1743 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1744 if (ret) 1745 return ret; 1746 } 1747 1748 return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 1749 } 1750 1751 static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv, 1752 struct v4l2_subdev_state *state) 1753 { 1754 unsigned int lanes; 1755 int mbps; 1756 int ret; 1757 1758 ret = rcsi2_get_active_lanes(priv, &lanes); 1759 if (ret) 1760 return ret; 1761 1762 mbps = rcsi2_calc_mbps(priv, state); 1763 if (mbps < 0) 1764 return mbps; 1765 1766 /* Reset LINK and PHY */ 1767 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1768 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1769 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1770 rcsi2_write(priv, V4M_PHTC_REG, PHTC_TESTCLR); 1771 1772 /* PHY static setting */ 1773 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1774 rcsi2_write(priv, V4H_FLDC_REG, 0); 1775 rcsi2_write(priv, V4H_FLDD_REG, 0); 1776 rcsi2_write(priv, V4H_IDIC_REG, 0); 1777 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_DPHY); 1778 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1779 1780 rcsi2_write(priv, V4M_FRXM_REG, 1781 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | 1782 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); 1783 rcsi2_write(priv, V4M_OVR1_REG, 1784 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | 1785 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); 1786 1787 /* Reset CSI2 */ 1788 rcsi2_write(priv, V4M_PHTC_REG, 0); 1789 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1790 1791 /* Common settings */ 1792 ret = rcsi2_init_common_v4m(priv, mbps); 1793 if (ret) 1794 return ret; 1795 1796 /* D-PHY settings */ 1797 ret = rcsi2_d_phy_setting_v4m(priv, mbps); 1798 if (ret) 1799 return ret; 1800 1801 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1802 V4H_ST_PHYST_ST_STOPSTATE_1 | 1803 V4H_ST_PHYST_ST_STOPSTATE_2 | 1804 V4H_ST_PHYST_ST_STOPSTATE_3); 1805 1806 rcsi2_write(priv, V4M_FRXM_REG, 0); 1807 1808 return 0; 1809 } 1810 1811 static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) 1812 { 1813 int ret; 1814 1815 ret = rcsi2_exit_standby(priv); 1816 if (ret < 0) 1817 return ret; 1818 1819 ret = priv->info->start_receiver(priv, state); 1820 if (ret) { 1821 rcsi2_enter_standby(priv); 1822 return ret; 1823 } 1824 1825 ret = v4l2_subdev_enable_streams(priv->remote, priv->remote_pad, 1826 BIT_ULL(0)); 1827 if (ret) { 1828 rcsi2_enter_standby(priv); 1829 return ret; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static void rcsi2_stop(struct rcar_csi2 *priv) 1836 { 1837 rcsi2_enter_standby(priv); 1838 v4l2_subdev_disable_streams(priv->remote, priv->remote_pad, BIT_ULL(0)); 1839 } 1840 1841 static int rcsi2_enable_streams(struct v4l2_subdev *sd, 1842 struct v4l2_subdev_state *state, u32 source_pad, 1843 u64 source_streams_mask) 1844 { 1845 struct rcar_csi2 *priv = sd_to_csi2(sd); 1846 int ret = 0; 1847 1848 if (source_streams_mask != 1) 1849 return -EINVAL; 1850 1851 if (!priv->remote) 1852 return -ENODEV; 1853 1854 if (priv->stream_count == 0) { 1855 ret = rcsi2_start(priv, state); 1856 if (ret) 1857 return ret; 1858 } 1859 1860 priv->stream_count += 1; 1861 1862 return ret; 1863 } 1864 1865 static int rcsi2_disable_streams(struct v4l2_subdev *sd, 1866 struct v4l2_subdev_state *state, 1867 u32 source_pad, u64 source_streams_mask) 1868 { 1869 struct rcar_csi2 *priv = sd_to_csi2(sd); 1870 int ret = 0; 1871 1872 if (source_streams_mask != 1) 1873 return -EINVAL; 1874 1875 if (!priv->remote) 1876 return -ENODEV; 1877 1878 if (priv->stream_count == 1) 1879 rcsi2_stop(priv); 1880 1881 priv->stream_count -= 1; 1882 1883 return ret; 1884 } 1885 1886 static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 1887 struct v4l2_subdev_state *state, 1888 struct v4l2_subdev_format *format) 1889 { 1890 struct rcar_csi2 *priv = sd_to_csi2(sd); 1891 unsigned int num_pads = rcsi2_num_pads(priv); 1892 1893 if (format->pad > RCAR_CSI2_SINK) 1894 return v4l2_subdev_get_fmt(sd, state, format); 1895 1896 if (!rcsi2_code_to_fmt(format->format.code)) 1897 format->format.code = rcar_csi2_formats[0].code; 1898 1899 *v4l2_subdev_state_get_format(state, format->pad) = format->format; 1900 1901 /* Propagate the format to the source pads. */ 1902 for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 1903 *v4l2_subdev_state_get_format(state, i) = format->format; 1904 1905 return 0; 1906 } 1907 1908 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 1909 .enable_streams = rcsi2_enable_streams, 1910 .disable_streams = rcsi2_disable_streams, 1911 1912 .set_fmt = rcsi2_set_pad_format, 1913 .get_fmt = v4l2_subdev_get_fmt, 1914 }; 1915 1916 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 1917 .pad = &rcar_csi2_pad_ops, 1918 }; 1919 1920 static int rcsi2_init_state(struct v4l2_subdev *sd, 1921 struct v4l2_subdev_state *state) 1922 { 1923 struct rcar_csi2 *priv = sd_to_csi2(sd); 1924 unsigned int num_pads = rcsi2_num_pads(priv); 1925 1926 static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = { 1927 .width = 1920, 1928 .height = 1080, 1929 .code = MEDIA_BUS_FMT_RGB888_1X24, 1930 .colorspace = V4L2_COLORSPACE_SRGB, 1931 .field = V4L2_FIELD_NONE, 1932 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 1933 .quantization = V4L2_QUANTIZATION_DEFAULT, 1934 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 1935 }; 1936 1937 for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++) 1938 *v4l2_subdev_state_get_format(state, i) = rcar_csi2_default_fmt; 1939 1940 return 0; 1941 } 1942 1943 static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = { 1944 .init_state = rcsi2_init_state, 1945 }; 1946 1947 static irqreturn_t rcsi2_irq(int irq, void *data) 1948 { 1949 struct rcar_csi2 *priv = data; 1950 u32 status, err_status; 1951 1952 status = rcsi2_read(priv, INTSTATE_REG); 1953 err_status = rcsi2_read(priv, INTERRSTATE_REG); 1954 1955 if (!status) 1956 return IRQ_HANDLED; 1957 1958 rcsi2_write(priv, INTSTATE_REG, status); 1959 1960 if (!err_status) 1961 return IRQ_HANDLED; 1962 1963 rcsi2_write(priv, INTERRSTATE_REG, err_status); 1964 1965 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 1966 1967 return IRQ_WAKE_THREAD; 1968 } 1969 1970 static irqreturn_t rcsi2_irq_thread(int irq, void *data) 1971 { 1972 struct v4l2_subdev_state *state; 1973 struct rcar_csi2 *priv = data; 1974 1975 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev); 1976 1977 rcsi2_stop(priv); 1978 usleep_range(1000, 2000); 1979 if (rcsi2_start(priv, state)) 1980 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 1981 1982 v4l2_subdev_unlock_state(state); 1983 1984 return IRQ_HANDLED; 1985 } 1986 1987 /* ----------------------------------------------------------------------------- 1988 * Async handling and registration of subdevices and links. 1989 */ 1990 1991 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 1992 struct v4l2_subdev *subdev, 1993 struct v4l2_async_connection *asc) 1994 { 1995 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1996 int pad; 1997 1998 pad = media_entity_get_fwnode_pad(&subdev->entity, asc->match.fwnode, 1999 MEDIA_PAD_FL_SOURCE); 2000 if (pad < 0) { 2001 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 2002 return pad; 2003 } 2004 2005 priv->remote = subdev; 2006 priv->remote_pad = pad; 2007 2008 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 2009 2010 return media_create_pad_link(&subdev->entity, pad, 2011 &priv->subdev.entity, 0, 2012 MEDIA_LNK_FL_ENABLED | 2013 MEDIA_LNK_FL_IMMUTABLE); 2014 } 2015 2016 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 2017 struct v4l2_subdev *subdev, 2018 struct v4l2_async_connection *asc) 2019 { 2020 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 2021 2022 priv->remote = NULL; 2023 2024 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 2025 } 2026 2027 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 2028 .bound = rcsi2_notify_bound, 2029 .unbind = rcsi2_notify_unbind, 2030 }; 2031 2032 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 2033 struct v4l2_fwnode_endpoint *vep) 2034 { 2035 unsigned int i; 2036 2037 /* Only port 0 endpoint 0 is valid. */ 2038 if (vep->base.port || vep->base.id) 2039 return -ENOTCONN; 2040 2041 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 2042 2043 switch (vep->bus_type) { 2044 case V4L2_MBUS_CSI2_DPHY: 2045 if (!priv->info->support_dphy) { 2046 dev_err(priv->dev, "D-PHY not supported\n"); 2047 return -EINVAL; 2048 } 2049 2050 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 2051 dev_err(priv->dev, 2052 "Unsupported number of data-lanes for D-PHY: %u\n", 2053 priv->lanes); 2054 return -EINVAL; 2055 } 2056 2057 priv->cphy = false; 2058 break; 2059 case V4L2_MBUS_CSI2_CPHY: 2060 if (!priv->info->support_cphy) { 2061 dev_err(priv->dev, "C-PHY not supported\n"); 2062 return -EINVAL; 2063 } 2064 2065 if (priv->lanes != 3) { 2066 dev_err(priv->dev, 2067 "Unsupported number of data-lanes for C-PHY: %u\n", 2068 priv->lanes); 2069 return -EINVAL; 2070 } 2071 2072 priv->cphy = true; 2073 break; 2074 default: 2075 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 2076 return -EINVAL; 2077 } 2078 2079 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 2080 priv->lane_swap[i] = i < priv->lanes ? 2081 vep->bus.mipi_csi2.data_lanes[i] : i; 2082 2083 /* Check for valid lane number. */ 2084 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 2085 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 2086 return -EINVAL; 2087 } 2088 } 2089 2090 for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++) 2091 priv->line_orders[i] = vep->bus.mipi_csi2.line_orders[i]; 2092 2093 return 0; 2094 } 2095 2096 static int rcsi2_parse_dt(struct rcar_csi2 *priv) 2097 { 2098 struct v4l2_async_connection *asc; 2099 struct fwnode_handle *fwnode; 2100 struct fwnode_handle *ep; 2101 struct v4l2_fwnode_endpoint v4l2_ep = { 2102 .bus_type = V4L2_MBUS_UNKNOWN, 2103 }; 2104 int ret; 2105 2106 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); 2107 if (!ep) { 2108 dev_err(priv->dev, "Not connected to subdevice\n"); 2109 return -EINVAL; 2110 } 2111 2112 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 2113 if (ret) { 2114 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 2115 fwnode_handle_put(ep); 2116 return -EINVAL; 2117 } 2118 2119 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 2120 if (ret) { 2121 fwnode_handle_put(ep); 2122 return ret; 2123 } 2124 2125 fwnode = fwnode_graph_get_remote_endpoint(ep); 2126 fwnode_handle_put(ep); 2127 2128 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 2129 2130 v4l2_async_subdev_nf_init(&priv->notifier, &priv->subdev); 2131 priv->notifier.ops = &rcar_csi2_notify_ops; 2132 2133 asc = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, 2134 struct v4l2_async_connection); 2135 fwnode_handle_put(fwnode); 2136 if (IS_ERR(asc)) 2137 return PTR_ERR(asc); 2138 2139 ret = v4l2_async_nf_register(&priv->notifier); 2140 if (ret) 2141 v4l2_async_nf_cleanup(&priv->notifier); 2142 2143 return ret; 2144 } 2145 2146 /* ----------------------------------------------------------------------------- 2147 * PHTW initialization sequences. 2148 * 2149 * NOTE: Magic values are from the datasheet and lack documentation. 2150 */ 2151 2152 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 2153 const struct rcsi2_mbps_info *values, u8 code) 2154 { 2155 const struct rcsi2_mbps_info *info; 2156 2157 info = rcsi2_mbps_to_info(priv, values, mbps); 2158 if (!info) 2159 return -ERANGE; 2160 2161 return rcsi2_phtw_write(priv, info->reg, code); 2162 } 2163 2164 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 2165 unsigned int mbps) 2166 { 2167 static const struct phtw_value step1[] = { 2168 { .data = 0xcc, .code = 0xe2 }, 2169 { .data = 0x01, .code = 0xe3 }, 2170 { .data = 0x11, .code = 0xe4 }, 2171 { .data = 0x01, .code = 0xe5 }, 2172 { .data = 0x10, .code = 0x04 }, 2173 }; 2174 2175 static const struct phtw_value step2[] = { 2176 { .data = 0x38, .code = 0x08 }, 2177 { .data = 0x01, .code = 0x00 }, 2178 { .data = 0x4b, .code = 0xac }, 2179 { .data = 0x03, .code = 0x00 }, 2180 { .data = 0x80, .code = 0x07 }, 2181 }; 2182 2183 int ret; 2184 2185 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2186 if (ret) 2187 return ret; 2188 2189 if (mbps != 0 && mbps <= 250) { 2190 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 2191 if (ret) 2192 return ret; 2193 2194 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 2195 0xf1); 2196 if (ret) 2197 return ret; 2198 } 2199 2200 return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 2201 } 2202 2203 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 2204 { 2205 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 2206 } 2207 2208 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 2209 { 2210 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 2211 } 2212 2213 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 2214 { 2215 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 2216 } 2217 2218 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 2219 { 2220 static const struct phtw_value step1[] = { 2221 { .data = 0xee, .code = 0x34 }, 2222 { .data = 0xee, .code = 0x44 }, 2223 { .data = 0xee, .code = 0x54 }, 2224 { .data = 0xee, .code = 0x84 }, 2225 { .data = 0xee, .code = 0x94 }, 2226 }; 2227 2228 return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2229 } 2230 2231 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, 2232 unsigned int mbps) 2233 { 2234 /* In case of 1500Mbps or less */ 2235 static const struct phtw_value step1[] = { 2236 { .data = 0xcc, .code = 0xe2 }, 2237 }; 2238 2239 static const struct phtw_value step2[] = { 2240 { .data = 0x01, .code = 0xe3 }, 2241 { .data = 0x11, .code = 0xe4 }, 2242 { .data = 0x01, .code = 0xe5 }, 2243 }; 2244 2245 /* In case of 1500Mbps or less */ 2246 static const struct phtw_value step3[] = { 2247 { .data = 0x38, .code = 0x08 }, 2248 }; 2249 2250 static const struct phtw_value step4[] = { 2251 { .data = 0x01, .code = 0x00 }, 2252 { .data = 0x4b, .code = 0xac }, 2253 { .data = 0x03, .code = 0x00 }, 2254 { .data = 0x80, .code = 0x07 }, 2255 }; 2256 2257 int ret; 2258 2259 if (mbps != 0 && mbps <= 1500) 2260 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2261 else 2262 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); 2263 if (ret) 2264 return ret; 2265 2266 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 2267 if (ret) 2268 return ret; 2269 2270 if (mbps != 0 && mbps <= 1500) { 2271 ret = rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 2272 if (ret) 2273 return ret; 2274 } 2275 2276 ret = rcsi2_phtw_write_array(priv, step4, ARRAY_SIZE(step4)); 2277 if (ret) 2278 return ret; 2279 2280 return ret; 2281 } 2282 2283 /* ----------------------------------------------------------------------------- 2284 * Platform Device Driver. 2285 */ 2286 2287 static int rcsi2_link_setup(struct media_entity *entity, 2288 const struct media_pad *local, 2289 const struct media_pad *remote, u32 flags) 2290 { 2291 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 2292 struct rcar_csi2 *priv = sd_to_csi2(sd); 2293 struct video_device *vdev; 2294 int channel, vc; 2295 u32 id; 2296 2297 if (!is_media_entity_v4l2_video_device(remote->entity)) { 2298 dev_err(priv->dev, "Remote is not a video device\n"); 2299 return -EINVAL; 2300 } 2301 2302 vdev = media_entity_to_video_device(remote->entity); 2303 2304 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) { 2305 dev_err(priv->dev, "No renesas,id, can't configure routing\n"); 2306 return -EINVAL; 2307 } 2308 2309 channel = id % 4; 2310 2311 if (flags & MEDIA_LNK_FL_ENABLED) { 2312 if (media_pad_remote_pad_first(local)) { 2313 dev_dbg(priv->dev, 2314 "Each VC can only be routed to one output channel\n"); 2315 return -EINVAL; 2316 } 2317 2318 vc = local->index - 1; 2319 2320 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n", 2321 vc, id, channel); 2322 } else { 2323 vc = -1; 2324 } 2325 2326 priv->channel_vc[channel] = vc; 2327 2328 return 0; 2329 } 2330 2331 static const struct media_entity_operations rcar_csi2_entity_ops = { 2332 .link_setup = rcsi2_link_setup, 2333 .link_validate = v4l2_subdev_link_validate, 2334 }; 2335 2336 static int rcsi2_probe_resources(struct rcar_csi2 *priv, 2337 struct platform_device *pdev) 2338 { 2339 int irq, ret; 2340 2341 priv->base = devm_platform_ioremap_resource(pdev, 0); 2342 if (IS_ERR(priv->base)) 2343 return PTR_ERR(priv->base); 2344 2345 irq = platform_get_irq(pdev, 0); 2346 if (irq < 0) 2347 return irq; 2348 2349 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 2350 rcsi2_irq_thread, IRQF_SHARED, 2351 KBUILD_MODNAME, priv); 2352 if (ret) 2353 return ret; 2354 2355 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 2356 2357 return PTR_ERR_OR_ZERO(priv->rstc); 2358 } 2359 2360 static const struct rcsi2_register_layout rcsi2_registers_gen3 = { 2361 .phtw = PHTW_REG, 2362 .phypll = PHYPLL_REG, 2363 }; 2364 2365 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 2366 .regs = &rcsi2_registers_gen3, 2367 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2368 .start_receiver = rcsi2_start_receiver_gen3, 2369 .enter_standby = rcsi2_enter_standby_gen3, 2370 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2371 .csi0clkfreqrange = 0x20, 2372 .num_channels = 4, 2373 .clear_ulps = true, 2374 .support_dphy = true, 2375 }; 2376 2377 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 2378 .regs = &rcsi2_registers_gen3, 2379 .init_phtw = rcsi2_init_phtw_h3es2, 2380 .start_receiver = rcsi2_start_receiver_gen3, 2381 .enter_standby = rcsi2_enter_standby_gen3, 2382 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2383 .csi0clkfreqrange = 0x20, 2384 .num_channels = 4, 2385 .clear_ulps = true, 2386 .support_dphy = true, 2387 }; 2388 2389 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 2390 .regs = &rcsi2_registers_gen3, 2391 .start_receiver = rcsi2_start_receiver_gen3, 2392 .enter_standby = rcsi2_enter_standby_gen3, 2393 .hsfreqrange = hsfreqrange_m3w, 2394 .num_channels = 4, 2395 .support_dphy = true, 2396 }; 2397 2398 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { 2399 .regs = &rcsi2_registers_gen3, 2400 .start_receiver = rcsi2_start_receiver_gen3, 2401 .enter_standby = rcsi2_enter_standby_gen3, 2402 .hsfreqrange = hsfreqrange_m3w, 2403 .num_channels = 4, 2404 .support_dphy = true, 2405 }; 2406 2407 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 2408 .regs = &rcsi2_registers_gen3, 2409 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2410 .start_receiver = rcsi2_start_receiver_gen3, 2411 .enter_standby = rcsi2_enter_standby_gen3, 2412 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2413 .csi0clkfreqrange = 0x20, 2414 .num_channels = 4, 2415 .clear_ulps = true, 2416 .support_dphy = true, 2417 }; 2418 2419 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 2420 .regs = &rcsi2_registers_gen3, 2421 .init_phtw = rcsi2_init_phtw_v3m_e3, 2422 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2423 .start_receiver = rcsi2_start_receiver_gen3, 2424 .enter_standby = rcsi2_enter_standby_gen3, 2425 .num_channels = 4, 2426 .support_dphy = true, 2427 }; 2428 2429 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 2430 .regs = &rcsi2_registers_gen3, 2431 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2432 .start_receiver = rcsi2_start_receiver_gen3, 2433 .enter_standby = rcsi2_enter_standby_gen3, 2434 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2435 .csi0clkfreqrange = 0x20, 2436 .clear_ulps = true, 2437 .support_dphy = true, 2438 }; 2439 2440 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 2441 .regs = &rcsi2_registers_gen3, 2442 .init_phtw = rcsi2_init_phtw_v3m_e3, 2443 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2444 .start_receiver = rcsi2_start_receiver_gen3, 2445 .enter_standby = rcsi2_enter_standby_gen3, 2446 .num_channels = 2, 2447 .support_dphy = true, 2448 }; 2449 2450 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { 2451 .regs = &rcsi2_registers_gen3, 2452 .init_phtw = rcsi2_init_phtw_v3u, 2453 .start_receiver = rcsi2_start_receiver_gen3, 2454 .enter_standby = rcsi2_enter_standby_gen3, 2455 .hsfreqrange = hsfreqrange_v3u, 2456 .csi0clkfreqrange = 0x20, 2457 .clear_ulps = true, 2458 .use_isp = true, 2459 .support_dphy = true, 2460 }; 2461 2462 static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = { 2463 .regs = &rcsi2_registers_gen3, 2464 .start_receiver = rcsi2_start_receiver_v4h, 2465 .use_isp = true, 2466 .support_cphy = true, 2467 .support_dphy = true, 2468 }; 2469 2470 static const struct rcsi2_register_layout rcsi2_registers_v4m = { 2471 .phtw = V4M_PHTW_REG, 2472 .phypll = V4M_PHYPLL_REG, 2473 }; 2474 2475 static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = { 2476 .regs = &rcsi2_registers_v4m, 2477 .start_receiver = rcsi2_start_receiver_v4m, 2478 .hsfreqrange = hsfreqrange_v4m, 2479 .csi0clkfreqrange = 0x0c, 2480 .use_isp = true, 2481 .support_dphy = true, 2482 }; 2483 2484 static const struct of_device_id rcar_csi2_of_table[] = { 2485 { 2486 .compatible = "renesas,r8a774a1-csi2", 2487 .data = &rcar_csi2_info_r8a7796, 2488 }, 2489 { 2490 .compatible = "renesas,r8a774b1-csi2", 2491 .data = &rcar_csi2_info_r8a77965, 2492 }, 2493 { 2494 .compatible = "renesas,r8a774c0-csi2", 2495 .data = &rcar_csi2_info_r8a77990, 2496 }, 2497 { 2498 .compatible = "renesas,r8a774e1-csi2", 2499 .data = &rcar_csi2_info_r8a7795, 2500 }, 2501 { 2502 .compatible = "renesas,r8a7795-csi2", 2503 .data = &rcar_csi2_info_r8a7795, 2504 }, 2505 { 2506 .compatible = "renesas,r8a7796-csi2", 2507 .data = &rcar_csi2_info_r8a7796, 2508 }, 2509 { 2510 .compatible = "renesas,r8a77961-csi2", 2511 .data = &rcar_csi2_info_r8a77961, 2512 }, 2513 { 2514 .compatible = "renesas,r8a77965-csi2", 2515 .data = &rcar_csi2_info_r8a77965, 2516 }, 2517 { 2518 .compatible = "renesas,r8a77970-csi2", 2519 .data = &rcar_csi2_info_r8a77970, 2520 }, 2521 { 2522 .compatible = "renesas,r8a77980-csi2", 2523 .data = &rcar_csi2_info_r8a77980, 2524 }, 2525 { 2526 .compatible = "renesas,r8a77990-csi2", 2527 .data = &rcar_csi2_info_r8a77990, 2528 }, 2529 { 2530 .compatible = "renesas,r8a779a0-csi2", 2531 .data = &rcar_csi2_info_r8a779a0, 2532 }, 2533 { 2534 .compatible = "renesas,r8a779g0-csi2", 2535 .data = &rcar_csi2_info_r8a779g0, 2536 }, 2537 { 2538 .compatible = "renesas,r8a779h0-csi2", 2539 .data = &rcar_csi2_info_r8a779h0, 2540 }, 2541 { /* sentinel */ }, 2542 }; 2543 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 2544 2545 static const struct soc_device_attribute r8a7795[] = { 2546 { 2547 .soc_id = "r8a7795", .revision = "ES2.*", 2548 .data = &rcar_csi2_info_r8a7795es2, 2549 }, 2550 { /* sentinel */ } 2551 }; 2552 2553 static int rcsi2_probe(struct platform_device *pdev) 2554 { 2555 const struct soc_device_attribute *attr; 2556 struct rcar_csi2 *priv; 2557 unsigned int i, num_pads; 2558 int ret; 2559 2560 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2561 if (!priv) 2562 return -ENOMEM; 2563 2564 priv->info = of_device_get_match_data(&pdev->dev); 2565 2566 /* 2567 * The different ES versions of r8a7795 (H3) behave differently but 2568 * share the same compatible string. 2569 */ 2570 attr = soc_device_match(r8a7795); 2571 if (attr) 2572 priv->info = attr->data; 2573 2574 priv->dev = &pdev->dev; 2575 2576 priv->stream_count = 0; 2577 2578 ret = rcsi2_probe_resources(priv, pdev); 2579 if (ret) { 2580 dev_err(priv->dev, "Failed to get resources\n"); 2581 return ret; 2582 } 2583 2584 platform_set_drvdata(pdev, priv); 2585 2586 ret = rcsi2_parse_dt(priv); 2587 if (ret) 2588 return ret; 2589 2590 priv->subdev.owner = THIS_MODULE; 2591 priv->subdev.dev = &pdev->dev; 2592 priv->subdev.internal_ops = &rcar_csi2_internal_ops; 2593 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 2594 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 2595 snprintf(priv->subdev.name, sizeof(priv->subdev.name), "%s %s", 2596 KBUILD_MODNAME, dev_name(&pdev->dev)); 2597 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 2598 2599 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 2600 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 2601 2602 num_pads = rcsi2_num_pads(priv); 2603 2604 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 2605 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 2606 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 2607 2608 ret = media_entity_pads_init(&priv->subdev.entity, num_pads, 2609 priv->pads); 2610 if (ret) 2611 goto error_async; 2612 2613 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) 2614 priv->channel_vc[i] = -1; 2615 2616 pm_runtime_enable(&pdev->dev); 2617 2618 ret = v4l2_subdev_init_finalize(&priv->subdev); 2619 if (ret) 2620 goto error_pm_runtime; 2621 2622 ret = v4l2_async_register_subdev(&priv->subdev); 2623 if (ret < 0) 2624 goto error_subdev; 2625 2626 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 2627 2628 return 0; 2629 2630 error_subdev: 2631 v4l2_subdev_cleanup(&priv->subdev); 2632 error_pm_runtime: 2633 pm_runtime_disable(&pdev->dev); 2634 error_async: 2635 v4l2_async_nf_unregister(&priv->notifier); 2636 v4l2_async_nf_cleanup(&priv->notifier); 2637 2638 return ret; 2639 } 2640 2641 static void rcsi2_remove(struct platform_device *pdev) 2642 { 2643 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 2644 2645 v4l2_async_nf_unregister(&priv->notifier); 2646 v4l2_async_nf_cleanup(&priv->notifier); 2647 v4l2_async_unregister_subdev(&priv->subdev); 2648 v4l2_subdev_cleanup(&priv->subdev); 2649 2650 pm_runtime_disable(&pdev->dev); 2651 } 2652 2653 static struct platform_driver rcar_csi2_pdrv = { 2654 .remove = rcsi2_remove, 2655 .probe = rcsi2_probe, 2656 .driver = { 2657 .name = "rcar-csi2", 2658 .suppress_bind_attrs = true, 2659 .of_match_table = rcar_csi2_of_table, 2660 }, 2661 }; 2662 2663 module_platform_driver(rcar_csi2_pdrv); 2664 2665 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 2666 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 2667 MODULE_LICENSE("GPL"); 2668