1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 #include <linux/sys_soc.h> 18 19 #include <media/mipi-csi2.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-mc.h> 24 #include <media/v4l2-subdev.h> 25 26 struct rcar_csi2; 27 28 /* Register offsets and bits */ 29 30 /* Control Timing Select */ 31 #define TREF_REG 0x00 32 #define TREF_TREF BIT(0) 33 34 /* Software Reset */ 35 #define SRST_REG 0x04 36 #define SRST_SRST BIT(0) 37 38 /* PHY Operation Control */ 39 #define PHYCNT_REG 0x08 40 #define PHYCNT_SHUTDOWNZ BIT(17) 41 #define PHYCNT_RSTZ BIT(16) 42 #define PHYCNT_ENABLECLK BIT(4) 43 #define PHYCNT_ENABLE_3 BIT(3) 44 #define PHYCNT_ENABLE_2 BIT(2) 45 #define PHYCNT_ENABLE_1 BIT(1) 46 #define PHYCNT_ENABLE_0 BIT(0) 47 48 /* Checksum Control */ 49 #define CHKSUM_REG 0x0c 50 #define CHKSUM_ECC_EN BIT(1) 51 #define CHKSUM_CRC_EN BIT(0) 52 53 /* 54 * Channel Data Type Select 55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 57 */ 58 #define VCDT_REG 0x10 59 #define VCDT2_REG 0x14 60 #define VCDT_VCDTN_EN BIT(15) 61 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 62 #define VCDT_SEL_DTN_ON BIT(6) 63 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 64 65 /* Frame Data Type Select */ 66 #define FRDT_REG 0x18 67 68 /* Field Detection Control */ 69 #define FLD_REG 0x1c 70 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 71 #define FLD_DET_SEL(n) (((n) & 0x3) << 4) 72 #define FLD_FLD_EN4 BIT(3) 73 #define FLD_FLD_EN3 BIT(2) 74 #define FLD_FLD_EN2 BIT(1) 75 #define FLD_FLD_EN BIT(0) 76 77 /* Automatic Standby Control */ 78 #define ASTBY_REG 0x20 79 80 /* Long Data Type Setting 0 */ 81 #define LNGDT0_REG 0x28 82 83 /* Long Data Type Setting 1 */ 84 #define LNGDT1_REG 0x2c 85 86 /* Interrupt Enable */ 87 #define INTEN_REG 0x30 88 #define INTEN_INT_AFIFO_OF BIT(27) 89 #define INTEN_INT_ERRSOTHS BIT(4) 90 #define INTEN_INT_ERRSOTSYNCHS BIT(3) 91 92 /* Interrupt Source Mask */ 93 #define INTCLOSE_REG 0x34 94 95 /* Interrupt Status Monitor */ 96 #define INTSTATE_REG 0x38 97 #define INTSTATE_INT_ULPS_START BIT(7) 98 #define INTSTATE_INT_ULPS_END BIT(6) 99 100 /* Interrupt Error Status Monitor */ 101 #define INTERRSTATE_REG 0x3c 102 103 /* Short Packet Data */ 104 #define SHPDAT_REG 0x40 105 106 /* Short Packet Count */ 107 #define SHPCNT_REG 0x44 108 109 /* LINK Operation Control */ 110 #define LINKCNT_REG 0x48 111 #define LINKCNT_MONITOR_EN BIT(31) 112 #define LINKCNT_REG_MONI_PACT_EN BIT(25) 113 #define LINKCNT_ICLK_NONSTOP BIT(24) 114 115 /* Lane Swap */ 116 #define LSWAP_REG 0x4c 117 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 118 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 119 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 120 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 121 122 /* PHY Test Interface Write Register */ 123 #define PHTW_REG 0x50 124 #define PHTW_DWEN BIT(24) 125 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 126 #define PHTW_CWEN BIT(8) 127 #define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 128 129 #define PHYFRX_REG 0x64 130 #define PHYFRX_FORCERX_MODE_3 BIT(3) 131 #define PHYFRX_FORCERX_MODE_2 BIT(2) 132 #define PHYFRX_FORCERX_MODE_1 BIT(1) 133 #define PHYFRX_FORCERX_MODE_0 BIT(0) 134 135 /* V4H BASE registers */ 136 #define V4H_N_LANES_REG 0x0004 137 #define V4H_CSI2_RESETN_REG 0x0008 138 139 #define V4H_PHY_MODE_REG 0x001c 140 #define V4H_PHY_MODE_DPHY 0 141 #define V4H_PHY_MODE_CPHY 1 142 143 #define V4H_PHY_SHUTDOWNZ_REG 0x0040 144 #define V4H_DPHY_RSTZ_REG 0x0044 145 #define V4H_FLDC_REG 0x0804 146 #define V4H_FLDD_REG 0x0808 147 #define V4H_IDIC_REG 0x0810 148 149 #define V4H_PHY_EN_REG 0x2000 150 #define V4H_PHY_EN_ENABLE_3 BIT(7) 151 #define V4H_PHY_EN_ENABLE_2 BIT(6) 152 #define V4H_PHY_EN_ENABLE_1 BIT(5) 153 #define V4H_PHY_EN_ENABLE_0 BIT(4) 154 #define V4H_PHY_EN_ENABLE_CLK BIT(0) 155 156 #define V4H_ST_PHYST_REG 0x2814 157 #define V4H_ST_PHYST_ST_PHY_READY BIT(31) 158 #define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3) 159 #define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2) 160 #define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1) 161 #define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0) 162 163 /* V4H PPI registers */ 164 #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */ 165 #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822 166 #define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c 167 #define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02 168 #define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04 169 #define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06 170 #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a 171 #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c 172 #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10 173 #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c 174 #define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80 175 #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0 176 177 /* V4H CORE registers */ 178 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2)) /* n = 0 - 15 */ 179 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2)) /* n = 0 - 15 */ 180 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2)) /* n = 0 - 15 */ 181 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2)) /* n = 0 - 15 */ 182 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2)) /* n = 0 - 15 */ 183 #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */ 184 #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */ 185 #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */ 186 #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400 187 #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c 188 189 /* V4H C-PHY */ 190 #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */ 191 #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */ 192 #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */ 193 #define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080 194 #define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */ 195 #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480 196 #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */ 197 #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880 198 #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */ 199 200 struct rcsi2_cphy_setting { 201 u16 msps; 202 u16 rx2; 203 u16 trio0; 204 u16 trio1; 205 u16 trio2; 206 u16 lane27; 207 u16 lane29; 208 }; 209 210 static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = { 211 { .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 }, 212 { .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 }, 213 { .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 }, 214 { .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 }, 215 { .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 }, 216 { .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 }, 217 { .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 }, 218 { .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 }, 219 { .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 }, 220 { .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 }, 221 { .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 }, 222 { .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 }, 223 { .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 }, 224 { .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 }, 225 { .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 226 { .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 227 { .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 228 { .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 229 { .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 230 { .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 231 { .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 232 { .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 233 { .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 234 { .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 235 { .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 236 { .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 }, 237 { .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 238 { .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 239 { .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 240 { .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 241 { .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 242 { .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 243 { .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 244 { .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 245 { .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 246 { .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 247 { /* sentinel */ }, 248 }; 249 250 /* V4M registers */ 251 #define V4M_OVR1_REG 0x0848 252 #define V4M_OVR1_FORCERXMODE_3 BIT(12) 253 #define V4M_OVR1_FORCERXMODE_2 BIT(11) 254 #define V4M_OVR1_FORCERXMODE_1 BIT(10) 255 #define V4M_OVR1_FORCERXMODE_0 BIT(9) 256 257 #define V4M_FRXM_REG 0x2004 258 #define V4M_FRXM_FORCERXMODE_3 BIT(3) 259 #define V4M_FRXM_FORCERXMODE_2 BIT(2) 260 #define V4M_FRXM_FORCERXMODE_1 BIT(1) 261 #define V4M_FRXM_FORCERXMODE_0 BIT(0) 262 263 #define V4M_PHYPLL_REG 0x02050 264 #define V4M_CSI0CLKFCPR_REG 0x02054 265 #define V4M_PHTW_REG 0x02060 266 #define V4M_PHTR_REG 0x02064 267 #define V4M_PHTC_REG 0x02068 268 269 struct phtw_value { 270 u8 data; 271 u8 code; 272 }; 273 274 struct rcsi2_mbps_info { 275 u16 mbps; 276 u8 reg; 277 u16 osc_freq; /* V4M */ 278 }; 279 280 static const struct rcsi2_mbps_info phtw_mbps_v3u[] = { 281 { .mbps = 1500, .reg = 0xcc }, 282 { .mbps = 1550, .reg = 0x1d }, 283 { .mbps = 1600, .reg = 0x27 }, 284 { .mbps = 1650, .reg = 0x30 }, 285 { .mbps = 1700, .reg = 0x39 }, 286 { .mbps = 1750, .reg = 0x42 }, 287 { .mbps = 1800, .reg = 0x4b }, 288 { .mbps = 1850, .reg = 0x55 }, 289 { .mbps = 1900, .reg = 0x5e }, 290 { .mbps = 1950, .reg = 0x67 }, 291 { .mbps = 2000, .reg = 0x71 }, 292 { .mbps = 2050, .reg = 0x79 }, 293 { .mbps = 2100, .reg = 0x83 }, 294 { .mbps = 2150, .reg = 0x8c }, 295 { .mbps = 2200, .reg = 0x95 }, 296 { .mbps = 2250, .reg = 0x9e }, 297 { .mbps = 2300, .reg = 0xa7 }, 298 { .mbps = 2350, .reg = 0xb0 }, 299 { .mbps = 2400, .reg = 0xba }, 300 { .mbps = 2450, .reg = 0xc3 }, 301 { .mbps = 2500, .reg = 0xcc }, 302 { /* sentinel */ }, 303 }; 304 305 static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = { 306 { .mbps = 80, .reg = 0x86 }, 307 { .mbps = 90, .reg = 0x86 }, 308 { .mbps = 100, .reg = 0x87 }, 309 { .mbps = 110, .reg = 0x87 }, 310 { .mbps = 120, .reg = 0x88 }, 311 { .mbps = 130, .reg = 0x88 }, 312 { .mbps = 140, .reg = 0x89 }, 313 { .mbps = 150, .reg = 0x89 }, 314 { .mbps = 160, .reg = 0x8a }, 315 { .mbps = 170, .reg = 0x8a }, 316 { .mbps = 180, .reg = 0x8b }, 317 { .mbps = 190, .reg = 0x8b }, 318 { .mbps = 205, .reg = 0x8c }, 319 { .mbps = 220, .reg = 0x8d }, 320 { .mbps = 235, .reg = 0x8e }, 321 { .mbps = 250, .reg = 0x8e }, 322 { /* sentinel */ }, 323 }; 324 325 static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = { 326 { .mbps = 80, .reg = 0x00 }, 327 { .mbps = 90, .reg = 0x20 }, 328 { .mbps = 100, .reg = 0x40 }, 329 { .mbps = 110, .reg = 0x02 }, 330 { .mbps = 130, .reg = 0x22 }, 331 { .mbps = 140, .reg = 0x42 }, 332 { .mbps = 150, .reg = 0x04 }, 333 { .mbps = 170, .reg = 0x24 }, 334 { .mbps = 180, .reg = 0x44 }, 335 { .mbps = 200, .reg = 0x06 }, 336 { .mbps = 220, .reg = 0x26 }, 337 { .mbps = 240, .reg = 0x46 }, 338 { .mbps = 250, .reg = 0x08 }, 339 { .mbps = 270, .reg = 0x28 }, 340 { .mbps = 300, .reg = 0x0a }, 341 { .mbps = 330, .reg = 0x2a }, 342 { .mbps = 360, .reg = 0x4a }, 343 { .mbps = 400, .reg = 0x0c }, 344 { .mbps = 450, .reg = 0x2c }, 345 { .mbps = 500, .reg = 0x0e }, 346 { .mbps = 550, .reg = 0x2e }, 347 { .mbps = 600, .reg = 0x10 }, 348 { .mbps = 650, .reg = 0x30 }, 349 { .mbps = 700, .reg = 0x12 }, 350 { .mbps = 750, .reg = 0x32 }, 351 { .mbps = 800, .reg = 0x52 }, 352 { .mbps = 850, .reg = 0x72 }, 353 { .mbps = 900, .reg = 0x14 }, 354 { .mbps = 950, .reg = 0x34 }, 355 { .mbps = 1000, .reg = 0x54 }, 356 { .mbps = 1050, .reg = 0x74 }, 357 { .mbps = 1125, .reg = 0x16 }, 358 { /* sentinel */ }, 359 }; 360 361 /* PHY Test Interface Clear */ 362 #define PHTC_REG 0x58 363 #define PHTC_TESTCLR BIT(0) 364 365 /* PHY Frequency Control */ 366 #define PHYPLL_REG 0x68 367 #define PHYPLL_HSFREQRANGE(n) ((n) << 16) 368 369 static const struct rcsi2_mbps_info hsfreqrange_v3u[] = { 370 { .mbps = 80, .reg = 0x00 }, 371 { .mbps = 90, .reg = 0x10 }, 372 { .mbps = 100, .reg = 0x20 }, 373 { .mbps = 110, .reg = 0x30 }, 374 { .mbps = 120, .reg = 0x01 }, 375 { .mbps = 130, .reg = 0x11 }, 376 { .mbps = 140, .reg = 0x21 }, 377 { .mbps = 150, .reg = 0x31 }, 378 { .mbps = 160, .reg = 0x02 }, 379 { .mbps = 170, .reg = 0x12 }, 380 { .mbps = 180, .reg = 0x22 }, 381 { .mbps = 190, .reg = 0x32 }, 382 { .mbps = 205, .reg = 0x03 }, 383 { .mbps = 220, .reg = 0x13 }, 384 { .mbps = 235, .reg = 0x23 }, 385 { .mbps = 250, .reg = 0x33 }, 386 { .mbps = 275, .reg = 0x04 }, 387 { .mbps = 300, .reg = 0x14 }, 388 { .mbps = 325, .reg = 0x25 }, 389 { .mbps = 350, .reg = 0x35 }, 390 { .mbps = 400, .reg = 0x05 }, 391 { .mbps = 450, .reg = 0x16 }, 392 { .mbps = 500, .reg = 0x26 }, 393 { .mbps = 550, .reg = 0x37 }, 394 { .mbps = 600, .reg = 0x07 }, 395 { .mbps = 650, .reg = 0x18 }, 396 { .mbps = 700, .reg = 0x28 }, 397 { .mbps = 750, .reg = 0x39 }, 398 { .mbps = 800, .reg = 0x09 }, 399 { .mbps = 850, .reg = 0x19 }, 400 { .mbps = 900, .reg = 0x29 }, 401 { .mbps = 950, .reg = 0x3a }, 402 { .mbps = 1000, .reg = 0x0a }, 403 { .mbps = 1050, .reg = 0x1a }, 404 { .mbps = 1100, .reg = 0x2a }, 405 { .mbps = 1150, .reg = 0x3b }, 406 { .mbps = 1200, .reg = 0x0b }, 407 { .mbps = 1250, .reg = 0x1b }, 408 { .mbps = 1300, .reg = 0x2b }, 409 { .mbps = 1350, .reg = 0x3c }, 410 { .mbps = 1400, .reg = 0x0c }, 411 { .mbps = 1450, .reg = 0x1c }, 412 { .mbps = 1500, .reg = 0x2c }, 413 { .mbps = 1550, .reg = 0x3d }, 414 { .mbps = 1600, .reg = 0x0d }, 415 { .mbps = 1650, .reg = 0x1d }, 416 { .mbps = 1700, .reg = 0x2e }, 417 { .mbps = 1750, .reg = 0x3e }, 418 { .mbps = 1800, .reg = 0x0e }, 419 { .mbps = 1850, .reg = 0x1e }, 420 { .mbps = 1900, .reg = 0x2f }, 421 { .mbps = 1950, .reg = 0x3f }, 422 { .mbps = 2000, .reg = 0x0f }, 423 { .mbps = 2050, .reg = 0x40 }, 424 { .mbps = 2100, .reg = 0x41 }, 425 { .mbps = 2150, .reg = 0x42 }, 426 { .mbps = 2200, .reg = 0x43 }, 427 { .mbps = 2300, .reg = 0x45 }, 428 { .mbps = 2350, .reg = 0x46 }, 429 { .mbps = 2400, .reg = 0x47 }, 430 { .mbps = 2450, .reg = 0x48 }, 431 { .mbps = 2500, .reg = 0x49 }, 432 { /* sentinel */ }, 433 }; 434 435 static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = { 436 { .mbps = 80, .reg = 0x00 }, 437 { .mbps = 90, .reg = 0x10 }, 438 { .mbps = 100, .reg = 0x20 }, 439 { .mbps = 110, .reg = 0x30 }, 440 { .mbps = 120, .reg = 0x01 }, 441 { .mbps = 130, .reg = 0x11 }, 442 { .mbps = 140, .reg = 0x21 }, 443 { .mbps = 150, .reg = 0x31 }, 444 { .mbps = 160, .reg = 0x02 }, 445 { .mbps = 170, .reg = 0x12 }, 446 { .mbps = 180, .reg = 0x22 }, 447 { .mbps = 190, .reg = 0x32 }, 448 { .mbps = 205, .reg = 0x03 }, 449 { .mbps = 220, .reg = 0x13 }, 450 { .mbps = 235, .reg = 0x23 }, 451 { .mbps = 250, .reg = 0x33 }, 452 { .mbps = 275, .reg = 0x04 }, 453 { .mbps = 300, .reg = 0x14 }, 454 { .mbps = 325, .reg = 0x25 }, 455 { .mbps = 350, .reg = 0x35 }, 456 { .mbps = 400, .reg = 0x05 }, 457 { .mbps = 450, .reg = 0x16 }, 458 { .mbps = 500, .reg = 0x26 }, 459 { .mbps = 550, .reg = 0x37 }, 460 { .mbps = 600, .reg = 0x07 }, 461 { .mbps = 650, .reg = 0x18 }, 462 { .mbps = 700, .reg = 0x28 }, 463 { .mbps = 750, .reg = 0x39 }, 464 { .mbps = 800, .reg = 0x09 }, 465 { .mbps = 850, .reg = 0x19 }, 466 { .mbps = 900, .reg = 0x29 }, 467 { .mbps = 950, .reg = 0x3a }, 468 { .mbps = 1000, .reg = 0x0a }, 469 { .mbps = 1050, .reg = 0x1a }, 470 { .mbps = 1100, .reg = 0x2a }, 471 { .mbps = 1150, .reg = 0x3b }, 472 { .mbps = 1200, .reg = 0x0b }, 473 { .mbps = 1250, .reg = 0x1b }, 474 { .mbps = 1300, .reg = 0x2b }, 475 { .mbps = 1350, .reg = 0x3c }, 476 { .mbps = 1400, .reg = 0x0c }, 477 { .mbps = 1450, .reg = 0x1c }, 478 { .mbps = 1500, .reg = 0x2c }, 479 { /* sentinel */ }, 480 }; 481 482 static const struct rcsi2_mbps_info hsfreqrange_m3w[] = { 483 { .mbps = 80, .reg = 0x00 }, 484 { .mbps = 90, .reg = 0x10 }, 485 { .mbps = 100, .reg = 0x20 }, 486 { .mbps = 110, .reg = 0x30 }, 487 { .mbps = 120, .reg = 0x01 }, 488 { .mbps = 130, .reg = 0x11 }, 489 { .mbps = 140, .reg = 0x21 }, 490 { .mbps = 150, .reg = 0x31 }, 491 { .mbps = 160, .reg = 0x02 }, 492 { .mbps = 170, .reg = 0x12 }, 493 { .mbps = 180, .reg = 0x22 }, 494 { .mbps = 190, .reg = 0x32 }, 495 { .mbps = 205, .reg = 0x03 }, 496 { .mbps = 220, .reg = 0x13 }, 497 { .mbps = 235, .reg = 0x23 }, 498 { .mbps = 250, .reg = 0x33 }, 499 { .mbps = 275, .reg = 0x04 }, 500 { .mbps = 300, .reg = 0x14 }, 501 { .mbps = 325, .reg = 0x05 }, 502 { .mbps = 350, .reg = 0x15 }, 503 { .mbps = 400, .reg = 0x25 }, 504 { .mbps = 450, .reg = 0x06 }, 505 { .mbps = 500, .reg = 0x16 }, 506 { .mbps = 550, .reg = 0x07 }, 507 { .mbps = 600, .reg = 0x17 }, 508 { .mbps = 650, .reg = 0x08 }, 509 { .mbps = 700, .reg = 0x18 }, 510 { .mbps = 750, .reg = 0x09 }, 511 { .mbps = 800, .reg = 0x19 }, 512 { .mbps = 850, .reg = 0x29 }, 513 { .mbps = 900, .reg = 0x39 }, 514 { .mbps = 950, .reg = 0x0a }, 515 { .mbps = 1000, .reg = 0x1a }, 516 { .mbps = 1050, .reg = 0x2a }, 517 { .mbps = 1100, .reg = 0x3a }, 518 { .mbps = 1150, .reg = 0x0b }, 519 { .mbps = 1200, .reg = 0x1b }, 520 { .mbps = 1250, .reg = 0x2b }, 521 { .mbps = 1300, .reg = 0x3b }, 522 { .mbps = 1350, .reg = 0x0c }, 523 { .mbps = 1400, .reg = 0x1c }, 524 { .mbps = 1450, .reg = 0x2c }, 525 { .mbps = 1500, .reg = 0x3c }, 526 { /* sentinel */ }, 527 }; 528 529 static const struct rcsi2_mbps_info hsfreqrange_v4m[] = { 530 { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 }, 531 { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 }, 532 { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 }, 533 { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 }, 534 { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 }, 535 { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 }, 536 { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 }, 537 { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 }, 538 { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 }, 539 { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 }, 540 { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 }, 541 { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 }, 542 { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 }, 543 { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 }, 544 { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 }, 545 { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 }, 546 { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 }, 547 { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 }, 548 { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 }, 549 { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 }, 550 { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 }, 551 { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 }, 552 { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 }, 553 { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 }, 554 { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 }, 555 { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 }, 556 { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 }, 557 { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 }, 558 { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 }, 559 { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 }, 560 { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 }, 561 { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 }, 562 { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 }, 563 { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 }, 564 { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 }, 565 { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 }, 566 { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 }, 567 { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 }, 568 { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 }, 569 { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 }, 570 { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 }, 571 { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 }, 572 { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 }, 573 { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 }, 574 { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 }, 575 { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 }, 576 { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 }, 577 { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a }, 578 { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 }, 579 { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b }, 580 { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 }, 581 { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c }, 582 { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 }, 583 { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d }, 584 { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 }, 585 { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e }, 586 { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 }, 587 { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f }, 588 { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 }, 589 { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 }, 590 { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 }, 591 { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 }, 592 { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 }, 593 { /* sentinel */ }, 594 }; 595 596 /* PHY ESC Error Monitor */ 597 #define PHEERM_REG 0x74 598 599 /* PHY Clock Lane Monitor */ 600 #define PHCLM_REG 0x78 601 #define PHCLM_STOPSTATECKL BIT(0) 602 603 /* PHY Data Lane Monitor */ 604 #define PHDLM_REG 0x7c 605 606 /* CSI0CLK Frequency Configuration Preset Register */ 607 #define CSI0CLKFCPR_REG 0x260 608 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 609 610 struct rcar_csi2_format { 611 u32 code; 612 unsigned int datatype; 613 unsigned int bpp; 614 }; 615 616 static const struct rcar_csi2_format rcar_csi2_formats[] = { 617 { 618 .code = MEDIA_BUS_FMT_RGB888_1X24, 619 .datatype = MIPI_CSI2_DT_RGB888, 620 .bpp = 24, 621 }, { 622 .code = MEDIA_BUS_FMT_UYVY8_1X16, 623 .datatype = MIPI_CSI2_DT_YUV422_8B, 624 .bpp = 16, 625 }, { 626 .code = MEDIA_BUS_FMT_YUYV8_1X16, 627 .datatype = MIPI_CSI2_DT_YUV422_8B, 628 .bpp = 16, 629 }, { 630 .code = MEDIA_BUS_FMT_UYVY8_2X8, 631 .datatype = MIPI_CSI2_DT_YUV422_8B, 632 .bpp = 16, 633 }, { 634 .code = MEDIA_BUS_FMT_YUYV10_2X10, 635 .datatype = MIPI_CSI2_DT_YUV422_8B, 636 .bpp = 20, 637 }, { 638 .code = MEDIA_BUS_FMT_Y10_1X10, 639 .datatype = MIPI_CSI2_DT_RAW10, 640 .bpp = 10, 641 }, { 642 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 643 .datatype = MIPI_CSI2_DT_RAW8, 644 .bpp = 8, 645 }, { 646 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 647 .datatype = MIPI_CSI2_DT_RAW8, 648 .bpp = 8, 649 }, { 650 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 651 .datatype = MIPI_CSI2_DT_RAW8, 652 .bpp = 8, 653 }, { 654 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 655 .datatype = MIPI_CSI2_DT_RAW8, 656 .bpp = 8, 657 }, { 658 .code = MEDIA_BUS_FMT_Y8_1X8, 659 .datatype = MIPI_CSI2_DT_RAW8, 660 .bpp = 8, 661 }, 662 }; 663 664 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 665 { 666 unsigned int i; 667 668 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 669 if (rcar_csi2_formats[i].code == code) 670 return &rcar_csi2_formats[i]; 671 672 return NULL; 673 } 674 675 enum rcar_csi2_pads { 676 RCAR_CSI2_SINK, 677 RCAR_CSI2_SOURCE_VC0, 678 RCAR_CSI2_SOURCE_VC1, 679 RCAR_CSI2_SOURCE_VC2, 680 RCAR_CSI2_SOURCE_VC3, 681 NR_OF_RCAR_CSI2_PAD, 682 }; 683 684 struct rcsi2_register_layout { 685 unsigned int phtw; 686 unsigned int phypll; 687 }; 688 689 struct rcar_csi2_info { 690 const struct rcsi2_register_layout *regs; 691 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 692 int (*phy_post_init)(struct rcar_csi2 *priv); 693 int (*start_receiver)(struct rcar_csi2 *priv, 694 struct v4l2_subdev_state *state); 695 void (*enter_standby)(struct rcar_csi2 *priv); 696 const struct rcsi2_mbps_info *hsfreqrange; 697 unsigned int csi0clkfreqrange; 698 unsigned int num_channels; 699 bool clear_ulps; 700 bool use_isp; 701 bool support_dphy; 702 bool support_cphy; 703 }; 704 705 struct rcar_csi2 { 706 struct device *dev; 707 void __iomem *base; 708 const struct rcar_csi2_info *info; 709 struct reset_control *rstc; 710 711 struct v4l2_subdev subdev; 712 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 713 714 struct v4l2_async_notifier notifier; 715 struct v4l2_subdev *remote; 716 unsigned int remote_pad; 717 718 int channel_vc[4]; 719 720 int stream_count; 721 722 bool cphy; 723 unsigned short lanes; 724 unsigned char lane_swap[4]; 725 }; 726 727 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 728 { 729 return container_of(sd, struct rcar_csi2, subdev); 730 } 731 732 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 733 { 734 return container_of(n, struct rcar_csi2, notifier); 735 } 736 737 static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv) 738 { 739 /* Used together with R-Car ISP: one sink and one source pad. */ 740 if (priv->info->use_isp) 741 return 2; 742 743 /* Used together with R-Car VIN: one sink and four source pads. */ 744 return 5; 745 } 746 747 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 748 { 749 return ioread32(priv->base + reg); 750 } 751 752 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 753 { 754 iowrite32(data, priv->base + reg); 755 } 756 757 static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) 758 { 759 iowrite16(data, priv->base + reg); 760 } 761 762 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) 763 { 764 unsigned int timeout; 765 766 rcsi2_write(priv, priv->info->regs->phtw, 767 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 768 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 769 770 /* Wait for DWEN and CWEN to be cleared by hardware. */ 771 for (timeout = 0; timeout <= 20; timeout++) { 772 if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) 773 return 0; 774 775 usleep_range(1000, 2000); 776 } 777 778 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 779 780 return -ETIMEDOUT; 781 } 782 783 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 784 const struct phtw_value *values, 785 unsigned int size) 786 { 787 int ret; 788 789 for (unsigned int i = 0; i < size; i++) { 790 ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); 791 if (ret) 792 return ret; 793 } 794 795 return 0; 796 } 797 798 static const struct rcsi2_mbps_info * 799 rcsi2_mbps_to_info(struct rcar_csi2 *priv, 800 const struct rcsi2_mbps_info *infotable, unsigned int mbps) 801 { 802 const struct rcsi2_mbps_info *info; 803 const struct rcsi2_mbps_info *prev = NULL; 804 805 if (mbps < infotable->mbps) 806 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", 807 mbps, infotable->mbps); 808 809 for (info = infotable; info->mbps != 0; info++) { 810 if (info->mbps >= mbps) 811 break; 812 prev = info; 813 } 814 815 if (!info->mbps) { 816 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 817 return NULL; 818 } 819 820 if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps))) 821 info = prev; 822 823 return info; 824 } 825 826 static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) 827 { 828 rcsi2_write(priv, PHYCNT_REG, 0); 829 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 830 } 831 832 static void rcsi2_enter_standby(struct rcar_csi2 *priv) 833 { 834 if (priv->info->enter_standby) 835 priv->info->enter_standby(priv); 836 837 reset_control_assert(priv->rstc); 838 usleep_range(100, 150); 839 pm_runtime_put(priv->dev); 840 } 841 842 static int rcsi2_exit_standby(struct rcar_csi2 *priv) 843 { 844 int ret; 845 846 ret = pm_runtime_resume_and_get(priv->dev); 847 if (ret < 0) 848 return ret; 849 850 reset_control_deassert(priv->rstc); 851 852 return 0; 853 } 854 855 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 856 unsigned int lanes) 857 { 858 unsigned int timeout; 859 860 /* Wait for the clock and data lanes to enter LP-11 state. */ 861 for (timeout = 0; timeout <= 20; timeout++) { 862 const u32 lane_mask = (1 << lanes) - 1; 863 864 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 865 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 866 return 0; 867 868 usleep_range(1000, 2000); 869 } 870 871 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 872 873 return -ETIMEDOUT; 874 } 875 876 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 877 { 878 const struct rcsi2_mbps_info *info; 879 880 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 881 if (!info) 882 return -ERANGE; 883 884 rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(info->reg)); 885 886 return 0; 887 } 888 889 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, 890 unsigned int lanes) 891 { 892 struct v4l2_subdev *source; 893 struct v4l2_ctrl *ctrl; 894 u64 mbps; 895 896 if (!priv->remote) 897 return -ENODEV; 898 899 source = priv->remote; 900 901 /* Read the pixel rate control from remote. */ 902 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE); 903 if (!ctrl) { 904 dev_err(priv->dev, "no pixel rate control in subdev %s\n", 905 source->name); 906 return -EINVAL; 907 } 908 909 /* 910 * Calculate the phypll in mbps. 911 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes) 912 * bps = link_freq * 2 913 */ 914 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp; 915 do_div(mbps, lanes * 1000000); 916 917 /* Adjust for C-PHY, divide by 2.8. */ 918 if (priv->cphy) 919 mbps = div_u64(mbps * 5, 14); 920 921 return mbps; 922 } 923 924 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 925 unsigned int *lanes) 926 { 927 struct v4l2_mbus_config mbus_config = { 0 }; 928 int ret; 929 930 *lanes = priv->lanes; 931 932 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 933 priv->remote_pad, &mbus_config); 934 if (ret == -ENOIOCTLCMD) { 935 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 936 return 0; 937 } 938 939 if (ret) { 940 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 941 return ret; 942 } 943 944 switch (mbus_config.type) { 945 case V4L2_MBUS_CSI2_CPHY: 946 if (!priv->cphy) 947 return -EINVAL; 948 break; 949 case V4L2_MBUS_CSI2_DPHY: 950 if (priv->cphy) 951 return -EINVAL; 952 break; 953 default: 954 dev_err(priv->dev, "Unsupported media bus type %u\n", 955 mbus_config.type); 956 return -EINVAL; 957 } 958 959 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) { 960 dev_err(priv->dev, 961 "Unsupported mbus config: too many data lanes %u\n", 962 mbus_config.bus.mipi_csi2.num_data_lanes); 963 return -EINVAL; 964 } 965 966 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes; 967 968 return 0; 969 } 970 971 static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv, 972 struct v4l2_subdev_state *state) 973 { 974 const struct rcar_csi2_format *format; 975 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 976 const struct v4l2_mbus_framefmt *fmt; 977 unsigned int lanes; 978 unsigned int i; 979 int mbps, ret; 980 981 /* Use the format on the sink pad to compute the receiver config. */ 982 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 983 984 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 985 fmt->width, fmt->height, 986 fmt->field == V4L2_FIELD_NONE ? 'p' : 'i'); 987 988 /* Code is validated in set_fmt. */ 989 format = rcsi2_code_to_fmt(fmt->code); 990 if (!format) 991 return -EINVAL; 992 993 /* 994 * Enable all supported CSI-2 channels with virtual channel and 995 * data type matching. 996 * 997 * NOTE: It's not possible to get individual datatype for each 998 * source virtual channel. Once this is possible in V4L2 999 * it should be used here. 1000 */ 1001 for (i = 0; i < priv->info->num_channels; i++) { 1002 u32 vcdt_part; 1003 1004 if (priv->channel_vc[i] < 0) 1005 continue; 1006 1007 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN | 1008 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype); 1009 1010 /* Store in correct reg and offset. */ 1011 if (i < 2) 1012 vcdt |= vcdt_part << ((i % 2) * 16); 1013 else 1014 vcdt2 |= vcdt_part << ((i % 2) * 16); 1015 } 1016 1017 if (fmt->field == V4L2_FIELD_ALTERNATE) { 1018 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 1019 | FLD_FLD_EN; 1020 1021 if (fmt->height == 240) 1022 fld |= FLD_FLD_NUM(0); 1023 else 1024 fld |= FLD_FLD_NUM(1); 1025 } 1026 1027 /* 1028 * Get the number of active data lanes inspecting the remote mbus 1029 * configuration. 1030 */ 1031 ret = rcsi2_get_active_lanes(priv, &lanes); 1032 if (ret) 1033 return ret; 1034 1035 phycnt = PHYCNT_ENABLECLK; 1036 phycnt |= (1 << lanes) - 1; 1037 1038 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1039 if (mbps < 0) 1040 return mbps; 1041 1042 /* Enable interrupts. */ 1043 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 1044 | INTEN_INT_ERRSOTSYNCHS); 1045 1046 /* Init */ 1047 rcsi2_write(priv, TREF_REG, TREF_TREF); 1048 rcsi2_write(priv, PHTC_REG, 0); 1049 1050 /* Configure */ 1051 if (!priv->info->use_isp) { 1052 rcsi2_write(priv, VCDT_REG, vcdt); 1053 if (vcdt2) 1054 rcsi2_write(priv, VCDT2_REG, vcdt2); 1055 } 1056 1057 /* Lanes are zero indexed. */ 1058 rcsi2_write(priv, LSWAP_REG, 1059 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 1060 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 1061 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 1062 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 1063 1064 /* Start */ 1065 if (priv->info->init_phtw) { 1066 ret = priv->info->init_phtw(priv, mbps); 1067 if (ret) 1068 return ret; 1069 } 1070 1071 if (priv->info->hsfreqrange) { 1072 ret = rcsi2_set_phypll(priv, mbps); 1073 if (ret) 1074 return ret; 1075 } 1076 1077 if (priv->info->csi0clkfreqrange) 1078 rcsi2_write(priv, CSI0CLKFCPR_REG, 1079 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1080 1081 if (priv->info->use_isp) 1082 rcsi2_write(priv, PHYFRX_REG, 1083 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 | 1084 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0); 1085 1086 rcsi2_write(priv, PHYCNT_REG, phycnt); 1087 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 1088 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 1089 rcsi2_write(priv, FLD_REG, fld); 1090 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 1091 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 1092 1093 ret = rcsi2_wait_phy_start(priv, lanes); 1094 if (ret) 1095 return ret; 1096 1097 if (priv->info->use_isp) 1098 rcsi2_write(priv, PHYFRX_REG, 0); 1099 1100 /* Run post PHY start initialization, if needed. */ 1101 if (priv->info->phy_post_init) { 1102 ret = priv->info->phy_post_init(priv); 1103 if (ret) 1104 return ret; 1105 } 1106 1107 /* Clear Ultra Low Power interrupt. */ 1108 if (priv->info->clear_ulps) 1109 rcsi2_write(priv, INTSTATE_REG, 1110 INTSTATE_INT_ULPS_START | 1111 INTSTATE_INT_ULPS_END); 1112 return 0; 1113 } 1114 1115 static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match) 1116 { 1117 unsigned int timeout; 1118 u32 status; 1119 1120 for (timeout = 0; timeout <= 10; timeout++) { 1121 status = rcsi2_read(priv, V4H_ST_PHYST_REG); 1122 if ((status & match) == match) 1123 return 0; 1124 1125 usleep_range(1000, 2000); 1126 } 1127 1128 return -ETIMEDOUT; 1129 } 1130 1131 static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps) 1132 { 1133 const struct rcsi2_cphy_setting *conf; 1134 1135 for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) { 1136 if (conf->msps > msps) 1137 break; 1138 } 1139 1140 if (!conf->msps) { 1141 dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", msps); 1142 return -ERANGE; 1143 } 1144 1145 /* C-PHY specific */ 1146 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155); 1147 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068); 1148 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010); 1149 1150 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c); 1151 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c); 1152 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c); 1153 1154 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5); 1155 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5); 1156 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5); 1157 1158 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013); 1159 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013); 1160 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013); 1161 1162 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013); 1163 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013); 1164 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013); 1165 1166 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a); 1167 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a); 1168 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a); 1169 1170 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(2), conf->rx2); 1171 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2); 1172 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2); 1173 1174 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x0001); 1175 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0); 1176 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x0001); 1177 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x0001); 1178 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0); 1179 1180 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0); 1181 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0); 1182 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0); 1183 1184 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(2), conf->trio2); 1185 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(2), conf->trio2); 1186 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(2), conf->trio2); 1187 1188 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(1), conf->trio1); 1189 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1); 1190 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1); 1191 1192 /* 1193 * Configure pin-swap. 1194 * TODO: This registers is not documented yet, the values should depend 1195 * on the 'clock-lanes' and 'data-lanes' devicetree properties. 1196 */ 1197 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, 0xf5); 1198 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000); 1199 1200 /* Leave Shutdown mode */ 1201 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1202 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1203 1204 /* Wait for calibration */ 1205 if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) { 1206 dev_err(priv->dev, "PHY calibration failed\n"); 1207 return -ETIMEDOUT; 1208 } 1209 1210 /* C-PHY setting - analog programing*/ 1211 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9), conf->lane29); 1212 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(7), conf->lane27); 1213 1214 return 0; 1215 } 1216 1217 static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, 1218 struct v4l2_subdev_state *state) 1219 { 1220 const struct rcar_csi2_format *format; 1221 const struct v4l2_mbus_framefmt *fmt; 1222 unsigned int lanes; 1223 int msps; 1224 int ret; 1225 1226 /* Use the format on the sink pad to compute the receiver config. */ 1227 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1228 format = rcsi2_code_to_fmt(fmt->code); 1229 if (!format) 1230 return -EINVAL; 1231 1232 ret = rcsi2_get_active_lanes(priv, &lanes); 1233 if (ret) 1234 return ret; 1235 1236 msps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1237 if (msps < 0) 1238 return msps; 1239 1240 /* Reset LINK and PHY*/ 1241 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1242 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1243 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1244 1245 /* PHY static setting */ 1246 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1247 rcsi2_write(priv, V4H_FLDC_REG, 0); 1248 rcsi2_write(priv, V4H_FLDD_REG, 0); 1249 rcsi2_write(priv, V4H_IDIC_REG, 0); 1250 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY); 1251 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1252 1253 /* Reset CSI2 */ 1254 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1255 1256 /* Registers static setting through APB */ 1257 /* Common setting */ 1258 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd); 1259 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233); 1260 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027); 1261 rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4); 1262 rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013); 1263 rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003); 1264 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f); 1265 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320); 1266 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f); 1267 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18); 1268 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c); 1269 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105); 1270 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000); 1271 rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); 1272 1273 /* C-PHY settings */ 1274 ret = rcsi2_c_phy_setting_v4h(priv, msps); 1275 if (ret) 1276 return ret; 1277 1278 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1279 V4H_ST_PHYST_ST_STOPSTATE_1 | 1280 V4H_ST_PHYST_ST_STOPSTATE_2); 1281 1282 return 0; 1283 } 1284 1285 static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int data_rate) 1286 { 1287 unsigned int timeout; 1288 int ret; 1289 1290 static const struct phtw_value step1[] = { 1291 { .data = 0x00, .code = 0x00 }, 1292 { .data = 0x00, .code = 0x1e }, 1293 }; 1294 1295 /* Shutdown and reset PHY. */ 1296 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1297 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1298 1299 /* Start internal calibration (POR). */ 1300 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1301 if (ret) 1302 return ret; 1303 1304 /* Wait for POR to complete. */ 1305 for (timeout = 10; timeout > 0; timeout--) { 1306 if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000) 1307 break; 1308 usleep_range(1000, 2000); 1309 } 1310 1311 if (!timeout) { 1312 dev_err(priv->dev, "D-PHY calibration failed\n"); 1313 return -ETIMEDOUT; 1314 } 1315 1316 return 0; 1317 } 1318 1319 static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps) 1320 { 1321 const struct rcsi2_mbps_info *info; 1322 struct phtw_value steps[] = { 1323 { .data = 0x00, .code = 0x00 }, 1324 { .code = 0xe2 }, /* Data filled in below. */ 1325 { .code = 0xe3 }, /* Data filled in below. */ 1326 { .data = 0x01, .code = 0xe4 }, 1327 }; 1328 1329 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 1330 if (!info) 1331 return -ERANGE; 1332 1333 /* Fill in data for command. */ 1334 steps[1].data = (info->osc_freq & 0x00ff) >> 0; 1335 steps[2].data = (info->osc_freq & 0x0f00) >> 8; 1336 1337 return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps)); 1338 } 1339 1340 static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps) 1341 { 1342 int ret; 1343 1344 static const struct phtw_value step1[] = { 1345 { .data = 0x00, .code = 0x00 }, 1346 { .data = 0x3c, .code = 0x08 }, 1347 }; 1348 1349 static const struct phtw_value step2[] = { 1350 { .data = 0x00, .code = 0x00 }, 1351 { .data = 0x80, .code = 0xe0 }, 1352 { .data = 0x01, .code = 0xe1 }, 1353 { .data = 0x06, .code = 0x00 }, 1354 { .data = 0x0f, .code = 0x11 }, 1355 { .data = 0x08, .code = 0x00 }, 1356 { .data = 0x0f, .code = 0x11 }, 1357 { .data = 0x0a, .code = 0x00 }, 1358 { .data = 0x0f, .code = 0x11 }, 1359 { .data = 0x0c, .code = 0x00 }, 1360 { .data = 0x0f, .code = 0x11 }, 1361 { .data = 0x01, .code = 0x00 }, 1362 { .data = 0x31, .code = 0xaa }, 1363 { .data = 0x05, .code = 0x00 }, 1364 { .data = 0x05, .code = 0x09 }, 1365 { .data = 0x07, .code = 0x00 }, 1366 { .data = 0x05, .code = 0x09 }, 1367 { .data = 0x09, .code = 0x00 }, 1368 { .data = 0x05, .code = 0x09 }, 1369 { .data = 0x0b, .code = 0x00 }, 1370 { .data = 0x05, .code = 0x09 }, 1371 }; 1372 1373 if (priv->info->hsfreqrange) { 1374 ret = rcsi2_set_phypll(priv, mbps); 1375 if (ret) 1376 return ret; 1377 1378 ret = rcsi2_set_osc_freq(priv, mbps); 1379 if (ret) 1380 return ret; 1381 } 1382 1383 if (mbps <= 1500) { 1384 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1385 if (ret) 1386 return ret; 1387 } 1388 1389 if (priv->info->csi0clkfreqrange) 1390 rcsi2_write(priv, V4M_CSI0CLKFCPR_REG, 1391 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1392 1393 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | 1394 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | 1395 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); 1396 1397 if (mbps > 1500) { 1398 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1399 if (ret) 1400 return ret; 1401 } 1402 1403 return ret; 1404 } 1405 1406 static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv, 1407 struct v4l2_subdev_state *state) 1408 { 1409 const struct rcar_csi2_format *format; 1410 const struct v4l2_mbus_framefmt *fmt; 1411 unsigned int lanes; 1412 int mbps; 1413 int ret; 1414 1415 /* Calculate parameters */ 1416 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1417 format = rcsi2_code_to_fmt(fmt->code); 1418 if (!format) 1419 return -EINVAL; 1420 1421 ret = rcsi2_get_active_lanes(priv, &lanes); 1422 if (ret) 1423 return ret; 1424 1425 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1426 if (mbps < 0) 1427 return mbps; 1428 1429 /* Reset LINK and PHY */ 1430 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1431 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1432 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1433 rcsi2_write(priv, V4M_PHTC_REG, PHTC_TESTCLR); 1434 1435 /* PHY static setting */ 1436 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1437 rcsi2_write(priv, V4H_FLDC_REG, 0); 1438 rcsi2_write(priv, V4H_FLDD_REG, 0); 1439 rcsi2_write(priv, V4H_IDIC_REG, 0); 1440 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_DPHY); 1441 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1442 1443 rcsi2_write(priv, V4M_FRXM_REG, 1444 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | 1445 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); 1446 rcsi2_write(priv, V4M_OVR1_REG, 1447 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | 1448 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); 1449 1450 /* Reset CSI2 */ 1451 rcsi2_write(priv, V4M_PHTC_REG, 0); 1452 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1453 1454 /* Common settings */ 1455 ret = rcsi2_init_common_v4m(priv, mbps); 1456 if (ret) 1457 return ret; 1458 1459 /* D-PHY settings */ 1460 ret = rcsi2_d_phy_setting_v4m(priv, mbps); 1461 if (ret) 1462 return ret; 1463 1464 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1465 V4H_ST_PHYST_ST_STOPSTATE_1 | 1466 V4H_ST_PHYST_ST_STOPSTATE_2 | 1467 V4H_ST_PHYST_ST_STOPSTATE_3); 1468 1469 rcsi2_write(priv, V4M_FRXM_REG, 0); 1470 1471 return 0; 1472 } 1473 1474 static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) 1475 { 1476 int ret; 1477 1478 ret = rcsi2_exit_standby(priv); 1479 if (ret < 0) 1480 return ret; 1481 1482 ret = priv->info->start_receiver(priv, state); 1483 if (ret) { 1484 rcsi2_enter_standby(priv); 1485 return ret; 1486 } 1487 1488 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1); 1489 if (ret) { 1490 rcsi2_enter_standby(priv); 1491 return ret; 1492 } 1493 1494 return 0; 1495 } 1496 1497 static void rcsi2_stop(struct rcar_csi2 *priv) 1498 { 1499 rcsi2_enter_standby(priv); 1500 v4l2_subdev_call(priv->remote, video, s_stream, 0); 1501 } 1502 1503 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable) 1504 { 1505 struct rcar_csi2 *priv = sd_to_csi2(sd); 1506 struct v4l2_subdev_state *state; 1507 int ret = 0; 1508 1509 if (!priv->remote) 1510 return -ENODEV; 1511 1512 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev); 1513 1514 if (enable && priv->stream_count == 0) { 1515 ret = rcsi2_start(priv, state); 1516 if (ret) 1517 goto out; 1518 } else if (!enable && priv->stream_count == 1) { 1519 rcsi2_stop(priv); 1520 } 1521 1522 priv->stream_count += enable ? 1 : -1; 1523 out: 1524 v4l2_subdev_unlock_state(state); 1525 1526 return ret; 1527 } 1528 1529 static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 1530 struct v4l2_subdev_state *state, 1531 struct v4l2_subdev_format *format) 1532 { 1533 struct rcar_csi2 *priv = sd_to_csi2(sd); 1534 unsigned int num_pads = rcsi2_num_pads(priv); 1535 1536 if (format->pad > RCAR_CSI2_SINK) 1537 return v4l2_subdev_get_fmt(sd, state, format); 1538 1539 if (!rcsi2_code_to_fmt(format->format.code)) 1540 format->format.code = rcar_csi2_formats[0].code; 1541 1542 *v4l2_subdev_state_get_format(state, format->pad) = format->format; 1543 1544 /* Propagate the format to the source pads. */ 1545 for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 1546 *v4l2_subdev_state_get_format(state, i) = format->format; 1547 1548 return 0; 1549 } 1550 1551 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = { 1552 .s_stream = rcsi2_s_stream, 1553 }; 1554 1555 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 1556 .set_fmt = rcsi2_set_pad_format, 1557 .get_fmt = v4l2_subdev_get_fmt, 1558 }; 1559 1560 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 1561 .video = &rcar_csi2_video_ops, 1562 .pad = &rcar_csi2_pad_ops, 1563 }; 1564 1565 static int rcsi2_init_state(struct v4l2_subdev *sd, 1566 struct v4l2_subdev_state *state) 1567 { 1568 struct rcar_csi2 *priv = sd_to_csi2(sd); 1569 unsigned int num_pads = rcsi2_num_pads(priv); 1570 1571 static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = { 1572 .width = 1920, 1573 .height = 1080, 1574 .code = MEDIA_BUS_FMT_RGB888_1X24, 1575 .colorspace = V4L2_COLORSPACE_SRGB, 1576 .field = V4L2_FIELD_NONE, 1577 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 1578 .quantization = V4L2_QUANTIZATION_DEFAULT, 1579 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 1580 }; 1581 1582 for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++) 1583 *v4l2_subdev_state_get_format(state, i) = rcar_csi2_default_fmt; 1584 1585 return 0; 1586 } 1587 1588 static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = { 1589 .init_state = rcsi2_init_state, 1590 }; 1591 1592 static irqreturn_t rcsi2_irq(int irq, void *data) 1593 { 1594 struct rcar_csi2 *priv = data; 1595 u32 status, err_status; 1596 1597 status = rcsi2_read(priv, INTSTATE_REG); 1598 err_status = rcsi2_read(priv, INTERRSTATE_REG); 1599 1600 if (!status) 1601 return IRQ_HANDLED; 1602 1603 rcsi2_write(priv, INTSTATE_REG, status); 1604 1605 if (!err_status) 1606 return IRQ_HANDLED; 1607 1608 rcsi2_write(priv, INTERRSTATE_REG, err_status); 1609 1610 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 1611 1612 return IRQ_WAKE_THREAD; 1613 } 1614 1615 static irqreturn_t rcsi2_irq_thread(int irq, void *data) 1616 { 1617 struct v4l2_subdev_state *state; 1618 struct rcar_csi2 *priv = data; 1619 1620 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev); 1621 1622 rcsi2_stop(priv); 1623 usleep_range(1000, 2000); 1624 if (rcsi2_start(priv, state)) 1625 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 1626 1627 v4l2_subdev_unlock_state(state); 1628 1629 return IRQ_HANDLED; 1630 } 1631 1632 /* ----------------------------------------------------------------------------- 1633 * Async handling and registration of subdevices and links. 1634 */ 1635 1636 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 1637 struct v4l2_subdev *subdev, 1638 struct v4l2_async_connection *asc) 1639 { 1640 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1641 int pad; 1642 1643 pad = media_entity_get_fwnode_pad(&subdev->entity, asc->match.fwnode, 1644 MEDIA_PAD_FL_SOURCE); 1645 if (pad < 0) { 1646 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 1647 return pad; 1648 } 1649 1650 priv->remote = subdev; 1651 priv->remote_pad = pad; 1652 1653 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 1654 1655 return media_create_pad_link(&subdev->entity, pad, 1656 &priv->subdev.entity, 0, 1657 MEDIA_LNK_FL_ENABLED | 1658 MEDIA_LNK_FL_IMMUTABLE); 1659 } 1660 1661 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 1662 struct v4l2_subdev *subdev, 1663 struct v4l2_async_connection *asc) 1664 { 1665 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1666 1667 priv->remote = NULL; 1668 1669 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 1670 } 1671 1672 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 1673 .bound = rcsi2_notify_bound, 1674 .unbind = rcsi2_notify_unbind, 1675 }; 1676 1677 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 1678 struct v4l2_fwnode_endpoint *vep) 1679 { 1680 unsigned int i; 1681 1682 /* Only port 0 endpoint 0 is valid. */ 1683 if (vep->base.port || vep->base.id) 1684 return -ENOTCONN; 1685 1686 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 1687 1688 switch (vep->bus_type) { 1689 case V4L2_MBUS_CSI2_DPHY: 1690 if (!priv->info->support_dphy) { 1691 dev_err(priv->dev, "D-PHY not supported\n"); 1692 return -EINVAL; 1693 } 1694 1695 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 1696 dev_err(priv->dev, 1697 "Unsupported number of data-lanes for D-PHY: %u\n", 1698 priv->lanes); 1699 return -EINVAL; 1700 } 1701 1702 priv->cphy = false; 1703 break; 1704 case V4L2_MBUS_CSI2_CPHY: 1705 if (!priv->info->support_cphy) { 1706 dev_err(priv->dev, "C-PHY not supported\n"); 1707 return -EINVAL; 1708 } 1709 1710 if (priv->lanes != 3) { 1711 dev_err(priv->dev, 1712 "Unsupported number of data-lanes for C-PHY: %u\n", 1713 priv->lanes); 1714 return -EINVAL; 1715 } 1716 1717 priv->cphy = true; 1718 break; 1719 default: 1720 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 1721 return -EINVAL; 1722 } 1723 1724 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 1725 priv->lane_swap[i] = i < priv->lanes ? 1726 vep->bus.mipi_csi2.data_lanes[i] : i; 1727 1728 /* Check for valid lane number. */ 1729 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 1730 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 1731 return -EINVAL; 1732 } 1733 } 1734 1735 return 0; 1736 } 1737 1738 static int rcsi2_parse_dt(struct rcar_csi2 *priv) 1739 { 1740 struct v4l2_async_connection *asc; 1741 struct fwnode_handle *fwnode; 1742 struct fwnode_handle *ep; 1743 struct v4l2_fwnode_endpoint v4l2_ep = { 1744 .bus_type = V4L2_MBUS_UNKNOWN, 1745 }; 1746 int ret; 1747 1748 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); 1749 if (!ep) { 1750 dev_err(priv->dev, "Not connected to subdevice\n"); 1751 return -EINVAL; 1752 } 1753 1754 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 1755 if (ret) { 1756 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 1757 fwnode_handle_put(ep); 1758 return -EINVAL; 1759 } 1760 1761 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 1762 if (ret) { 1763 fwnode_handle_put(ep); 1764 return ret; 1765 } 1766 1767 fwnode = fwnode_graph_get_remote_endpoint(ep); 1768 fwnode_handle_put(ep); 1769 1770 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 1771 1772 v4l2_async_subdev_nf_init(&priv->notifier, &priv->subdev); 1773 priv->notifier.ops = &rcar_csi2_notify_ops; 1774 1775 asc = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, 1776 struct v4l2_async_connection); 1777 fwnode_handle_put(fwnode); 1778 if (IS_ERR(asc)) 1779 return PTR_ERR(asc); 1780 1781 ret = v4l2_async_nf_register(&priv->notifier); 1782 if (ret) 1783 v4l2_async_nf_cleanup(&priv->notifier); 1784 1785 return ret; 1786 } 1787 1788 /* ----------------------------------------------------------------------------- 1789 * PHTW initialization sequences. 1790 * 1791 * NOTE: Magic values are from the datasheet and lack documentation. 1792 */ 1793 1794 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 1795 const struct rcsi2_mbps_info *values, u8 code) 1796 { 1797 const struct rcsi2_mbps_info *info; 1798 1799 info = rcsi2_mbps_to_info(priv, values, mbps); 1800 if (!info) 1801 return -ERANGE; 1802 1803 return rcsi2_phtw_write(priv, info->reg, code); 1804 } 1805 1806 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 1807 unsigned int mbps) 1808 { 1809 static const struct phtw_value step1[] = { 1810 { .data = 0xcc, .code = 0xe2 }, 1811 { .data = 0x01, .code = 0xe3 }, 1812 { .data = 0x11, .code = 0xe4 }, 1813 { .data = 0x01, .code = 0xe5 }, 1814 { .data = 0x10, .code = 0x04 }, 1815 }; 1816 1817 static const struct phtw_value step2[] = { 1818 { .data = 0x38, .code = 0x08 }, 1819 { .data = 0x01, .code = 0x00 }, 1820 { .data = 0x4b, .code = 0xac }, 1821 { .data = 0x03, .code = 0x00 }, 1822 { .data = 0x80, .code = 0x07 }, 1823 }; 1824 1825 int ret; 1826 1827 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1828 if (ret) 1829 return ret; 1830 1831 if (mbps != 0 && mbps <= 250) { 1832 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 1833 if (ret) 1834 return ret; 1835 1836 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 1837 0xf1); 1838 if (ret) 1839 return ret; 1840 } 1841 1842 return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1843 } 1844 1845 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 1846 { 1847 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 1848 } 1849 1850 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 1851 { 1852 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 1853 } 1854 1855 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 1856 { 1857 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 1858 } 1859 1860 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 1861 { 1862 static const struct phtw_value step1[] = { 1863 { .data = 0xee, .code = 0x34 }, 1864 { .data = 0xee, .code = 0x44 }, 1865 { .data = 0xee, .code = 0x54 }, 1866 { .data = 0xee, .code = 0x84 }, 1867 { .data = 0xee, .code = 0x94 }, 1868 }; 1869 1870 return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1871 } 1872 1873 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, 1874 unsigned int mbps) 1875 { 1876 /* In case of 1500Mbps or less */ 1877 static const struct phtw_value step1[] = { 1878 { .data = 0xcc, .code = 0xe2 }, 1879 }; 1880 1881 static const struct phtw_value step2[] = { 1882 { .data = 0x01, .code = 0xe3 }, 1883 { .data = 0x11, .code = 0xe4 }, 1884 { .data = 0x01, .code = 0xe5 }, 1885 }; 1886 1887 /* In case of 1500Mbps or less */ 1888 static const struct phtw_value step3[] = { 1889 { .data = 0x38, .code = 0x08 }, 1890 }; 1891 1892 static const struct phtw_value step4[] = { 1893 { .data = 0x01, .code = 0x00 }, 1894 { .data = 0x4b, .code = 0xac }, 1895 { .data = 0x03, .code = 0x00 }, 1896 { .data = 0x80, .code = 0x07 }, 1897 }; 1898 1899 int ret; 1900 1901 if (mbps != 0 && mbps <= 1500) 1902 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1903 else 1904 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); 1905 if (ret) 1906 return ret; 1907 1908 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1909 if (ret) 1910 return ret; 1911 1912 if (mbps != 0 && mbps <= 1500) { 1913 ret = rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 1914 if (ret) 1915 return ret; 1916 } 1917 1918 ret = rcsi2_phtw_write_array(priv, step4, ARRAY_SIZE(step4)); 1919 if (ret) 1920 return ret; 1921 1922 return ret; 1923 } 1924 1925 /* ----------------------------------------------------------------------------- 1926 * Platform Device Driver. 1927 */ 1928 1929 static int rcsi2_link_setup(struct media_entity *entity, 1930 const struct media_pad *local, 1931 const struct media_pad *remote, u32 flags) 1932 { 1933 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1934 struct rcar_csi2 *priv = sd_to_csi2(sd); 1935 struct video_device *vdev; 1936 int channel, vc; 1937 u32 id; 1938 1939 if (!is_media_entity_v4l2_video_device(remote->entity)) { 1940 dev_err(priv->dev, "Remote is not a video device\n"); 1941 return -EINVAL; 1942 } 1943 1944 vdev = media_entity_to_video_device(remote->entity); 1945 1946 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) { 1947 dev_err(priv->dev, "No renesas,id, can't configure routing\n"); 1948 return -EINVAL; 1949 } 1950 1951 channel = id % 4; 1952 1953 if (flags & MEDIA_LNK_FL_ENABLED) { 1954 if (media_pad_remote_pad_first(local)) { 1955 dev_dbg(priv->dev, 1956 "Each VC can only be routed to one output channel\n"); 1957 return -EINVAL; 1958 } 1959 1960 vc = local->index - 1; 1961 1962 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n", 1963 vc, id, channel); 1964 } else { 1965 vc = -1; 1966 } 1967 1968 priv->channel_vc[channel] = vc; 1969 1970 return 0; 1971 } 1972 1973 static const struct media_entity_operations rcar_csi2_entity_ops = { 1974 .link_setup = rcsi2_link_setup, 1975 .link_validate = v4l2_subdev_link_validate, 1976 }; 1977 1978 static int rcsi2_probe_resources(struct rcar_csi2 *priv, 1979 struct platform_device *pdev) 1980 { 1981 int irq, ret; 1982 1983 priv->base = devm_platform_ioremap_resource(pdev, 0); 1984 if (IS_ERR(priv->base)) 1985 return PTR_ERR(priv->base); 1986 1987 irq = platform_get_irq(pdev, 0); 1988 if (irq < 0) 1989 return irq; 1990 1991 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 1992 rcsi2_irq_thread, IRQF_SHARED, 1993 KBUILD_MODNAME, priv); 1994 if (ret) 1995 return ret; 1996 1997 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 1998 1999 return PTR_ERR_OR_ZERO(priv->rstc); 2000 } 2001 2002 static const struct rcsi2_register_layout rcsi2_registers_gen3 = { 2003 .phtw = PHTW_REG, 2004 .phypll = PHYPLL_REG, 2005 }; 2006 2007 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 2008 .regs = &rcsi2_registers_gen3, 2009 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2010 .start_receiver = rcsi2_start_receiver_gen3, 2011 .enter_standby = rcsi2_enter_standby_gen3, 2012 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2013 .csi0clkfreqrange = 0x20, 2014 .num_channels = 4, 2015 .clear_ulps = true, 2016 .support_dphy = true, 2017 }; 2018 2019 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 2020 .regs = &rcsi2_registers_gen3, 2021 .init_phtw = rcsi2_init_phtw_h3es2, 2022 .start_receiver = rcsi2_start_receiver_gen3, 2023 .enter_standby = rcsi2_enter_standby_gen3, 2024 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2025 .csi0clkfreqrange = 0x20, 2026 .num_channels = 4, 2027 .clear_ulps = true, 2028 .support_dphy = true, 2029 }; 2030 2031 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 2032 .regs = &rcsi2_registers_gen3, 2033 .start_receiver = rcsi2_start_receiver_gen3, 2034 .enter_standby = rcsi2_enter_standby_gen3, 2035 .hsfreqrange = hsfreqrange_m3w, 2036 .num_channels = 4, 2037 .support_dphy = true, 2038 }; 2039 2040 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { 2041 .regs = &rcsi2_registers_gen3, 2042 .start_receiver = rcsi2_start_receiver_gen3, 2043 .enter_standby = rcsi2_enter_standby_gen3, 2044 .hsfreqrange = hsfreqrange_m3w, 2045 .num_channels = 4, 2046 .support_dphy = true, 2047 }; 2048 2049 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 2050 .regs = &rcsi2_registers_gen3, 2051 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2052 .start_receiver = rcsi2_start_receiver_gen3, 2053 .enter_standby = rcsi2_enter_standby_gen3, 2054 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2055 .csi0clkfreqrange = 0x20, 2056 .num_channels = 4, 2057 .clear_ulps = true, 2058 .support_dphy = true, 2059 }; 2060 2061 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 2062 .regs = &rcsi2_registers_gen3, 2063 .init_phtw = rcsi2_init_phtw_v3m_e3, 2064 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2065 .start_receiver = rcsi2_start_receiver_gen3, 2066 .enter_standby = rcsi2_enter_standby_gen3, 2067 .num_channels = 4, 2068 .support_dphy = true, 2069 }; 2070 2071 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 2072 .regs = &rcsi2_registers_gen3, 2073 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2074 .start_receiver = rcsi2_start_receiver_gen3, 2075 .enter_standby = rcsi2_enter_standby_gen3, 2076 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2077 .csi0clkfreqrange = 0x20, 2078 .clear_ulps = true, 2079 .support_dphy = true, 2080 }; 2081 2082 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 2083 .regs = &rcsi2_registers_gen3, 2084 .init_phtw = rcsi2_init_phtw_v3m_e3, 2085 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2086 .start_receiver = rcsi2_start_receiver_gen3, 2087 .enter_standby = rcsi2_enter_standby_gen3, 2088 .num_channels = 2, 2089 .support_dphy = true, 2090 }; 2091 2092 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { 2093 .regs = &rcsi2_registers_gen3, 2094 .init_phtw = rcsi2_init_phtw_v3u, 2095 .start_receiver = rcsi2_start_receiver_gen3, 2096 .enter_standby = rcsi2_enter_standby_gen3, 2097 .hsfreqrange = hsfreqrange_v3u, 2098 .csi0clkfreqrange = 0x20, 2099 .clear_ulps = true, 2100 .use_isp = true, 2101 .support_dphy = true, 2102 }; 2103 2104 static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = { 2105 .regs = &rcsi2_registers_gen3, 2106 .start_receiver = rcsi2_start_receiver_v4h, 2107 .use_isp = true, 2108 .support_cphy = true, 2109 }; 2110 2111 static const struct rcsi2_register_layout rcsi2_registers_v4m = { 2112 .phtw = V4M_PHTW_REG, 2113 .phypll = V4M_PHYPLL_REG, 2114 }; 2115 2116 static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = { 2117 .regs = &rcsi2_registers_v4m, 2118 .start_receiver = rcsi2_start_receiver_v4m, 2119 .hsfreqrange = hsfreqrange_v4m, 2120 .csi0clkfreqrange = 0x0c, 2121 .use_isp = true, 2122 .support_dphy = true, 2123 }; 2124 2125 static const struct of_device_id rcar_csi2_of_table[] = { 2126 { 2127 .compatible = "renesas,r8a774a1-csi2", 2128 .data = &rcar_csi2_info_r8a7796, 2129 }, 2130 { 2131 .compatible = "renesas,r8a774b1-csi2", 2132 .data = &rcar_csi2_info_r8a77965, 2133 }, 2134 { 2135 .compatible = "renesas,r8a774c0-csi2", 2136 .data = &rcar_csi2_info_r8a77990, 2137 }, 2138 { 2139 .compatible = "renesas,r8a774e1-csi2", 2140 .data = &rcar_csi2_info_r8a7795, 2141 }, 2142 { 2143 .compatible = "renesas,r8a7795-csi2", 2144 .data = &rcar_csi2_info_r8a7795, 2145 }, 2146 { 2147 .compatible = "renesas,r8a7796-csi2", 2148 .data = &rcar_csi2_info_r8a7796, 2149 }, 2150 { 2151 .compatible = "renesas,r8a77961-csi2", 2152 .data = &rcar_csi2_info_r8a77961, 2153 }, 2154 { 2155 .compatible = "renesas,r8a77965-csi2", 2156 .data = &rcar_csi2_info_r8a77965, 2157 }, 2158 { 2159 .compatible = "renesas,r8a77970-csi2", 2160 .data = &rcar_csi2_info_r8a77970, 2161 }, 2162 { 2163 .compatible = "renesas,r8a77980-csi2", 2164 .data = &rcar_csi2_info_r8a77980, 2165 }, 2166 { 2167 .compatible = "renesas,r8a77990-csi2", 2168 .data = &rcar_csi2_info_r8a77990, 2169 }, 2170 { 2171 .compatible = "renesas,r8a779a0-csi2", 2172 .data = &rcar_csi2_info_r8a779a0, 2173 }, 2174 { 2175 .compatible = "renesas,r8a779g0-csi2", 2176 .data = &rcar_csi2_info_r8a779g0, 2177 }, 2178 { 2179 .compatible = "renesas,r8a779h0-csi2", 2180 .data = &rcar_csi2_info_r8a779h0, 2181 }, 2182 { /* sentinel */ }, 2183 }; 2184 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 2185 2186 static const struct soc_device_attribute r8a7795[] = { 2187 { 2188 .soc_id = "r8a7795", .revision = "ES2.*", 2189 .data = &rcar_csi2_info_r8a7795es2, 2190 }, 2191 { /* sentinel */ } 2192 }; 2193 2194 static int rcsi2_probe(struct platform_device *pdev) 2195 { 2196 const struct soc_device_attribute *attr; 2197 struct rcar_csi2 *priv; 2198 unsigned int i, num_pads; 2199 int ret; 2200 2201 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2202 if (!priv) 2203 return -ENOMEM; 2204 2205 priv->info = of_device_get_match_data(&pdev->dev); 2206 2207 /* 2208 * The different ES versions of r8a7795 (H3) behave differently but 2209 * share the same compatible string. 2210 */ 2211 attr = soc_device_match(r8a7795); 2212 if (attr) 2213 priv->info = attr->data; 2214 2215 priv->dev = &pdev->dev; 2216 2217 priv->stream_count = 0; 2218 2219 ret = rcsi2_probe_resources(priv, pdev); 2220 if (ret) { 2221 dev_err(priv->dev, "Failed to get resources\n"); 2222 return ret; 2223 } 2224 2225 platform_set_drvdata(pdev, priv); 2226 2227 ret = rcsi2_parse_dt(priv); 2228 if (ret) 2229 return ret; 2230 2231 priv->subdev.owner = THIS_MODULE; 2232 priv->subdev.dev = &pdev->dev; 2233 priv->subdev.internal_ops = &rcar_csi2_internal_ops; 2234 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 2235 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 2236 snprintf(priv->subdev.name, sizeof(priv->subdev.name), "%s %s", 2237 KBUILD_MODNAME, dev_name(&pdev->dev)); 2238 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 2239 2240 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 2241 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 2242 2243 num_pads = rcsi2_num_pads(priv); 2244 2245 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 2246 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 2247 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 2248 2249 ret = media_entity_pads_init(&priv->subdev.entity, num_pads, 2250 priv->pads); 2251 if (ret) 2252 goto error_async; 2253 2254 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) 2255 priv->channel_vc[i] = -1; 2256 2257 pm_runtime_enable(&pdev->dev); 2258 2259 ret = v4l2_subdev_init_finalize(&priv->subdev); 2260 if (ret) 2261 goto error_pm_runtime; 2262 2263 ret = v4l2_async_register_subdev(&priv->subdev); 2264 if (ret < 0) 2265 goto error_subdev; 2266 2267 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 2268 2269 return 0; 2270 2271 error_subdev: 2272 v4l2_subdev_cleanup(&priv->subdev); 2273 error_pm_runtime: 2274 pm_runtime_disable(&pdev->dev); 2275 error_async: 2276 v4l2_async_nf_unregister(&priv->notifier); 2277 v4l2_async_nf_cleanup(&priv->notifier); 2278 2279 return ret; 2280 } 2281 2282 static void rcsi2_remove(struct platform_device *pdev) 2283 { 2284 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 2285 2286 v4l2_async_nf_unregister(&priv->notifier); 2287 v4l2_async_nf_cleanup(&priv->notifier); 2288 v4l2_async_unregister_subdev(&priv->subdev); 2289 v4l2_subdev_cleanup(&priv->subdev); 2290 2291 pm_runtime_disable(&pdev->dev); 2292 } 2293 2294 static struct platform_driver rcar_csi2_pdrv = { 2295 .remove = rcsi2_remove, 2296 .probe = rcsi2_probe, 2297 .driver = { 2298 .name = "rcar-csi2", 2299 .suppress_bind_attrs = true, 2300 .of_match_table = rcar_csi2_of_table, 2301 }, 2302 }; 2303 2304 module_platform_driver(rcar_csi2_pdrv); 2305 2306 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 2307 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 2308 MODULE_LICENSE("GPL"); 2309