1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Linaro Ltd. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/firmware.h> 8 #include <linux/kernel.h> 9 #include <linux/iommu.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/of_reserved_mem.h> 13 #include <linux/platform_device.h> 14 #include <linux/of_device.h> 15 #include <linux/firmware/qcom/qcom_pas.h> 16 #include <linux/firmware/qcom/qcom_scm.h> 17 #include <linux/sizes.h> 18 #include <linux/soc/qcom/mdt_loader.h> 19 20 #include "core.h" 21 #include "firmware.h" 22 #include "hfi_venus_io.h" 23 24 #define VENUS_PAS_ID 9 25 #define VENUS_FW_MEM_SIZE (6 * SZ_1M) 26 #define VENUS_FW_START_ADDR 0x0 27 28 static void venus_reset_cpu(struct venus_core *core) 29 { 30 u32 fw_size = core->fw.mapped_mem_size; 31 void __iomem *wrapper_base; 32 33 if (IS_IRIS2(core) || IS_IRIS2_1(core)) 34 wrapper_base = core->wrapper_tz_base; 35 else 36 wrapper_base = core->wrapper_base; 37 38 writel(0, wrapper_base + WRAPPER_FW_START_ADDR); 39 writel(fw_size, wrapper_base + WRAPPER_FW_END_ADDR); 40 writel(0, wrapper_base + WRAPPER_CPA_START_ADDR); 41 writel(fw_size, wrapper_base + WRAPPER_CPA_END_ADDR); 42 writel(fw_size, wrapper_base + WRAPPER_NONPIX_START_ADDR); 43 writel(fw_size, wrapper_base + WRAPPER_NONPIX_END_ADDR); 44 45 if (IS_IRIS2(core) || IS_IRIS2_1(core)) { 46 /* Bring XTSS out of reset */ 47 writel(0, wrapper_base + WRAPPER_TZ_XTSS_SW_RESET); 48 } else { 49 writel(0x0, wrapper_base + WRAPPER_CPU_CGC_DIS); 50 writel(0x0, wrapper_base + WRAPPER_CPU_CLOCK_CONFIG); 51 52 /* Bring ARM9 out of reset */ 53 writel(0, wrapper_base + WRAPPER_A9SS_SW_RESET); 54 } 55 } 56 57 int venus_set_hw_state(struct venus_core *core, bool resume) 58 { 59 int ret; 60 61 if (core->use_tz) { 62 ret = qcom_pas_set_remote_state(resume, 0); 63 if (resume && ret == -EINVAL) 64 ret = 0; 65 return ret; 66 } 67 68 if (resume) { 69 venus_reset_cpu(core); 70 } else { 71 if (IS_IRIS2(core) || IS_IRIS2_1(core)) 72 writel(WRAPPER_XTSS_SW_RESET_BIT, 73 core->wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET); 74 else 75 writel(WRAPPER_A9SS_SW_RESET_BIT, 76 core->wrapper_base + WRAPPER_A9SS_SW_RESET); 77 } 78 79 return 0; 80 } 81 82 static int venus_load_fw(struct venus_core *core, const char *fwname, 83 phys_addr_t *mem_phys, size_t *mem_size) 84 { 85 const struct firmware *mdt; 86 struct resource res; 87 struct device *dev; 88 ssize_t fw_size; 89 void *mem_va; 90 int ret; 91 92 *mem_phys = 0; 93 *mem_size = 0; 94 95 dev = core->dev; 96 ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 97 if (ret) { 98 dev_err(dev, "failed to lookup reserved memory-region\n"); 99 return -EINVAL; 100 } 101 102 ret = request_firmware(&mdt, fwname, dev); 103 if (ret < 0) 104 return ret; 105 106 fw_size = qcom_mdt_get_size(mdt); 107 if (fw_size < 0) { 108 ret = fw_size; 109 goto err_release_fw; 110 } 111 112 *mem_phys = res.start; 113 *mem_size = resource_size(&res); 114 115 if (*mem_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) { 116 ret = -EINVAL; 117 goto err_release_fw; 118 } 119 120 mem_va = memremap(*mem_phys, *mem_size, MEMREMAP_WC); 121 if (!mem_va) { 122 dev_err(dev, "unable to map memory region %pa size %#zx\n", mem_phys, *mem_size); 123 ret = -ENOMEM; 124 goto err_release_fw; 125 } 126 127 if (core->use_tz) 128 ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, 129 mem_va, *mem_phys, *mem_size, NULL); 130 else 131 ret = qcom_mdt_load_no_init(dev, mdt, fwname, mem_va, 132 *mem_phys, *mem_size, NULL); 133 134 memunmap(mem_va); 135 err_release_fw: 136 release_firmware(mdt); 137 return ret; 138 } 139 140 static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys, 141 size_t mem_size) 142 { 143 struct iommu_domain *iommu; 144 struct device *dev; 145 int ret; 146 147 dev = core->fw.dev; 148 if (!dev) 149 return -EPROBE_DEFER; 150 151 iommu = core->fw.iommu_domain; 152 core->fw.mapped_mem_size = mem_size; 153 154 ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size, 155 IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); 156 if (ret) { 157 dev_err(dev, "could not map video firmware region\n"); 158 return ret; 159 } 160 161 venus_reset_cpu(core); 162 163 return 0; 164 } 165 166 static int venus_shutdown_no_tz(struct venus_core *core) 167 { 168 const size_t mapped = core->fw.mapped_mem_size; 169 struct iommu_domain *iommu; 170 size_t unmapped; 171 u32 reg; 172 struct device *dev = core->fw.dev; 173 void __iomem *wrapper_base = core->wrapper_base; 174 void __iomem *wrapper_tz_base = core->wrapper_tz_base; 175 176 if (IS_IRIS2(core) || IS_IRIS2_1(core)) { 177 /* Assert the reset to XTSS */ 178 reg = readl(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET); 179 reg |= WRAPPER_XTSS_SW_RESET_BIT; 180 writel(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET); 181 } else { 182 /* Assert the reset to ARM9 */ 183 reg = readl(wrapper_base + WRAPPER_A9SS_SW_RESET); 184 reg |= WRAPPER_A9SS_SW_RESET_BIT; 185 writel(reg, wrapper_base + WRAPPER_A9SS_SW_RESET); 186 } 187 188 iommu = core->fw.iommu_domain; 189 190 if (core->fw.mapped_mem_size && iommu) { 191 unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped); 192 193 if (unmapped != mapped) 194 dev_err(dev, "failed to unmap firmware\n"); 195 else 196 core->fw.mapped_mem_size = 0; 197 } 198 199 return 0; 200 } 201 202 int venus_firmware_cfg(struct venus_core *core) 203 { 204 void __iomem *cpu_cs_base = core->cpu_cs_base; 205 206 if (IS_AR50_LITE(core)) 207 writel(CPU_CS_VCICMD_ARP_OFF, cpu_cs_base + CPU_CS_VCICMD); 208 209 return 0; 210 } 211 212 int venus_boot(struct venus_core *core) 213 { 214 struct device *dev = core->dev; 215 const struct venus_resources *res = core->res; 216 const char *fwpath = NULL; 217 phys_addr_t mem_phys; 218 size_t mem_size; 219 int ret; 220 221 if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || 222 (core->use_tz && !qcom_pas_is_available())) 223 return -EPROBE_DEFER; 224 225 ret = of_property_read_string_index(dev->of_node, "firmware-name", 0, 226 &fwpath); 227 if (ret) 228 fwpath = core->res->fwname; 229 230 ret = venus_load_fw(core, fwpath, &mem_phys, &mem_size); 231 if (ret) { 232 dev_err(dev, "fail to load video firmware\n"); 233 return -EINVAL; 234 } 235 236 core->fw.mem_size = mem_size; 237 core->fw.mem_phys = mem_phys; 238 239 if (core->use_tz) 240 ret = qcom_pas_auth_and_reset(VENUS_PAS_ID); 241 else 242 ret = venus_boot_no_tz(core, mem_phys, mem_size); 243 244 if (ret) 245 return ret; 246 247 if (core->use_tz && res->cp_size) { 248 /* 249 * Clues for porting using downstream data: 250 * cp_start = 0 251 * cp_size = venus_ns/virtual-addr-pool[0] - yes, address and not size! 252 * This works, as the non-secure context bank is placed 253 * contiguously right after the Content Protection region. 254 * 255 * cp_nonpixel_start = venus_sec_non_pixel/virtual-addr-pool[0] 256 * cp_nonpixel_size = venus_sec_non_pixel/virtual-addr-pool[1] 257 */ 258 ret = qcom_scm_mem_protect_video_var(res->cp_start, 259 res->cp_size, 260 res->cp_nonpixel_start, 261 res->cp_nonpixel_size); 262 if (ret) { 263 qcom_pas_shutdown(VENUS_PAS_ID); 264 dev_err(dev, "set virtual address ranges fail (%d)\n", 265 ret); 266 return ret; 267 } 268 } 269 270 return 0; 271 } 272 273 int venus_shutdown(struct venus_core *core) 274 { 275 int ret; 276 277 if (core->use_tz) 278 ret = qcom_pas_shutdown(VENUS_PAS_ID); 279 else 280 ret = venus_shutdown_no_tz(core); 281 282 return ret; 283 } 284 285 int venus_firmware_check(struct venus_core *core) 286 { 287 const struct firmware_version *req = core->res->min_fw; 288 const struct firmware_version *run = &core->venus_ver; 289 290 if (!req) 291 return 0; 292 293 if (!is_fw_rev_or_newer(core, req->major, req->minor, req->rev)) 294 goto error; 295 296 return 0; 297 error: 298 dev_err(core->dev, "Firmware v%d.%d.%d < v%d.%d.%d\n", 299 run->major, run->minor, run->rev, 300 req->major, req->minor, req->rev); 301 302 return -EINVAL; 303 } 304 305 int venus_firmware_init(struct venus_core *core) 306 { 307 struct platform_device_info info; 308 struct iommu_domain *iommu_dom; 309 struct platform_device *pdev; 310 struct device_node *np; 311 int ret; 312 313 np = of_get_child_by_name(core->dev->of_node, "video-firmware"); 314 if (!np) { 315 core->use_tz = true; 316 return 0; 317 } 318 319 memset(&info, 0, sizeof(info)); 320 info.fwnode = &np->fwnode; 321 info.parent = core->dev; 322 info.name = np->name; 323 info.dma_mask = DMA_BIT_MASK(32); 324 325 pdev = platform_device_register_full(&info); 326 if (IS_ERR(pdev)) { 327 of_node_put(np); 328 return PTR_ERR(pdev); 329 } 330 331 pdev->dev.of_node = np; 332 333 ret = of_dma_configure(&pdev->dev, np, true); 334 if (ret) { 335 dev_err(core->dev, "dma configure fail\n"); 336 goto err_unregister; 337 } 338 339 core->fw.dev = &pdev->dev; 340 341 iommu_dom = iommu_paging_domain_alloc(core->fw.dev); 342 if (IS_ERR(iommu_dom)) { 343 dev_err(core->fw.dev, "Failed to allocate iommu domain\n"); 344 ret = PTR_ERR(iommu_dom); 345 goto err_unregister; 346 } 347 348 ret = iommu_attach_device(iommu_dom, core->fw.dev); 349 if (ret) { 350 dev_err(core->fw.dev, "could not attach device\n"); 351 goto err_iommu_free; 352 } 353 354 core->fw.iommu_domain = iommu_dom; 355 356 of_node_put(np); 357 358 return 0; 359 360 err_iommu_free: 361 iommu_domain_free(iommu_dom); 362 err_unregister: 363 platform_device_unregister(pdev); 364 of_node_put(np); 365 return ret; 366 } 367 368 void venus_firmware_deinit(struct venus_core *core) 369 { 370 struct iommu_domain *iommu; 371 372 if (!core->fw.dev) 373 return; 374 375 iommu = core->fw.iommu_domain; 376 377 iommu_detach_device(iommu, core->fw.dev); 378 379 if (core->fw.iommu_domain) { 380 iommu_domain_free(iommu); 381 core->fw.iommu_domain = NULL; 382 } 383 384 platform_device_unregister(to_platform_device(core->fw.dev)); 385 } 386