1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Linaro Ltd. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/firmware.h> 8 #include <linux/kernel.h> 9 #include <linux/iommu.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/platform_device.h> 14 #include <linux/of_device.h> 15 #include <linux/qcom_scm.h> 16 #include <linux/sizes.h> 17 #include <linux/soc/qcom/mdt_loader.h> 18 19 #include "core.h" 20 #include "firmware.h" 21 #include "hfi_venus_io.h" 22 23 #define VENUS_PAS_ID 9 24 #define VENUS_FW_MEM_SIZE (6 * SZ_1M) 25 #define VENUS_FW_START_ADDR 0x0 26 27 static void venus_reset_cpu(struct venus_core *core) 28 { 29 u32 fw_size = core->fw.mapped_mem_size; 30 void __iomem *base = core->base; 31 32 writel(0, base + WRAPPER_FW_START_ADDR); 33 writel(fw_size, base + WRAPPER_FW_END_ADDR); 34 writel(0, base + WRAPPER_CPA_START_ADDR); 35 writel(fw_size, base + WRAPPER_CPA_END_ADDR); 36 writel(fw_size, base + WRAPPER_NONPIX_START_ADDR); 37 writel(fw_size, base + WRAPPER_NONPIX_END_ADDR); 38 writel(0x0, base + WRAPPER_CPU_CGC_DIS); 39 writel(0x0, base + WRAPPER_CPU_CLOCK_CONFIG); 40 41 /* Bring ARM9 out of reset */ 42 writel(0, base + WRAPPER_A9SS_SW_RESET); 43 } 44 45 int venus_set_hw_state(struct venus_core *core, bool resume) 46 { 47 int ret; 48 49 if (core->use_tz) { 50 ret = qcom_scm_set_remote_state(resume, 0); 51 if (resume && ret == -EINVAL) 52 ret = 0; 53 return ret; 54 } 55 56 if (resume) 57 venus_reset_cpu(core); 58 else 59 writel(1, core->base + WRAPPER_A9SS_SW_RESET); 60 61 return 0; 62 } 63 64 static int venus_load_fw(struct venus_core *core, const char *fwname, 65 phys_addr_t *mem_phys, size_t *mem_size) 66 { 67 const struct firmware *mdt; 68 struct device_node *node; 69 struct device *dev; 70 struct resource r; 71 ssize_t fw_size; 72 void *mem_va; 73 int ret; 74 75 *mem_phys = 0; 76 *mem_size = 0; 77 78 dev = core->dev; 79 node = of_parse_phandle(dev->of_node, "memory-region", 0); 80 if (!node) { 81 dev_err(dev, "no memory-region specified\n"); 82 return -EINVAL; 83 } 84 85 ret = of_address_to_resource(node, 0, &r); 86 if (ret) 87 goto err_put_node; 88 89 ret = request_firmware(&mdt, fwname, dev); 90 if (ret < 0) 91 goto err_put_node; 92 93 fw_size = qcom_mdt_get_size(mdt); 94 if (fw_size < 0) { 95 ret = fw_size; 96 goto err_release_fw; 97 } 98 99 *mem_phys = r.start; 100 *mem_size = resource_size(&r); 101 102 if (*mem_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) { 103 ret = -EINVAL; 104 goto err_release_fw; 105 } 106 107 mem_va = memremap(r.start, *mem_size, MEMREMAP_WC); 108 if (!mem_va) { 109 dev_err(dev, "unable to map memory region: %pR\n", &r); 110 ret = -ENOMEM; 111 goto err_release_fw; 112 } 113 114 if (core->use_tz) 115 ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, 116 mem_va, *mem_phys, *mem_size, NULL); 117 else 118 ret = qcom_mdt_load_no_init(dev, mdt, fwname, VENUS_PAS_ID, 119 mem_va, *mem_phys, *mem_size, NULL); 120 121 memunmap(mem_va); 122 err_release_fw: 123 release_firmware(mdt); 124 err_put_node: 125 of_node_put(node); 126 return ret; 127 } 128 129 static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys, 130 size_t mem_size) 131 { 132 struct iommu_domain *iommu; 133 struct device *dev; 134 int ret; 135 136 dev = core->fw.dev; 137 if (!dev) 138 return -EPROBE_DEFER; 139 140 iommu = core->fw.iommu_domain; 141 core->fw.mapped_mem_size = mem_size; 142 143 ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size, 144 IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV); 145 if (ret) { 146 dev_err(dev, "could not map video firmware region\n"); 147 return ret; 148 } 149 150 venus_reset_cpu(core); 151 152 return 0; 153 } 154 155 static int venus_shutdown_no_tz(struct venus_core *core) 156 { 157 const size_t mapped = core->fw.mapped_mem_size; 158 struct iommu_domain *iommu; 159 size_t unmapped; 160 u32 reg; 161 struct device *dev = core->fw.dev; 162 void __iomem *base = core->base; 163 164 /* Assert the reset to ARM9 */ 165 reg = readl_relaxed(base + WRAPPER_A9SS_SW_RESET); 166 reg |= WRAPPER_A9SS_SW_RESET_BIT; 167 writel_relaxed(reg, base + WRAPPER_A9SS_SW_RESET); 168 169 /* Make sure reset is asserted before the mapping is removed */ 170 mb(); 171 172 iommu = core->fw.iommu_domain; 173 174 if (core->fw.mapped_mem_size && iommu) { 175 unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped); 176 177 if (unmapped != mapped) 178 dev_err(dev, "failed to unmap firmware\n"); 179 else 180 core->fw.mapped_mem_size = 0; 181 } 182 183 return 0; 184 } 185 186 int venus_boot(struct venus_core *core) 187 { 188 struct device *dev = core->dev; 189 const struct venus_resources *res = core->res; 190 phys_addr_t mem_phys; 191 size_t mem_size; 192 int ret; 193 194 if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || 195 (core->use_tz && !qcom_scm_is_available())) 196 return -EPROBE_DEFER; 197 198 ret = venus_load_fw(core, core->res->fwname, &mem_phys, &mem_size); 199 if (ret) { 200 dev_err(dev, "fail to load video firmware\n"); 201 return -EINVAL; 202 } 203 204 core->fw.mem_size = mem_size; 205 core->fw.mem_phys = mem_phys; 206 207 if (core->use_tz) 208 ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); 209 else 210 ret = venus_boot_no_tz(core, mem_phys, mem_size); 211 212 if (ret) 213 return ret; 214 215 if (core->use_tz && res->cp_size) { 216 ret = qcom_scm_mem_protect_video_var(res->cp_start, 217 res->cp_size, 218 res->cp_nonpixel_start, 219 res->cp_nonpixel_size); 220 if (ret) { 221 qcom_scm_pas_shutdown(VENUS_PAS_ID); 222 dev_err(dev, "set virtual address ranges fail (%d)\n", 223 ret); 224 return ret; 225 } 226 } 227 228 return 0; 229 } 230 231 int venus_shutdown(struct venus_core *core) 232 { 233 int ret; 234 235 if (core->use_tz) 236 ret = qcom_scm_pas_shutdown(VENUS_PAS_ID); 237 else 238 ret = venus_shutdown_no_tz(core); 239 240 return ret; 241 } 242 243 int venus_firmware_init(struct venus_core *core) 244 { 245 struct platform_device_info info; 246 struct iommu_domain *iommu_dom; 247 struct platform_device *pdev; 248 struct device_node *np; 249 int ret; 250 251 np = of_get_child_by_name(core->dev->of_node, "video-firmware"); 252 if (!np) { 253 core->use_tz = true; 254 return 0; 255 } 256 257 memset(&info, 0, sizeof(info)); 258 info.fwnode = &np->fwnode; 259 info.parent = core->dev; 260 info.name = np->name; 261 info.dma_mask = DMA_BIT_MASK(32); 262 263 pdev = platform_device_register_full(&info); 264 if (IS_ERR(pdev)) { 265 of_node_put(np); 266 return PTR_ERR(pdev); 267 } 268 269 pdev->dev.of_node = np; 270 271 ret = of_dma_configure(&pdev->dev, np, true); 272 if (ret) { 273 dev_err(core->dev, "dma configure fail\n"); 274 goto err_unregister; 275 } 276 277 core->fw.dev = &pdev->dev; 278 279 iommu_dom = iommu_domain_alloc(&platform_bus_type); 280 if (!iommu_dom) { 281 dev_err(core->fw.dev, "Failed to allocate iommu domain\n"); 282 ret = -ENOMEM; 283 goto err_unregister; 284 } 285 286 ret = iommu_attach_device(iommu_dom, core->fw.dev); 287 if (ret) { 288 dev_err(core->fw.dev, "could not attach device\n"); 289 goto err_iommu_free; 290 } 291 292 core->fw.iommu_domain = iommu_dom; 293 294 of_node_put(np); 295 296 return 0; 297 298 err_iommu_free: 299 iommu_domain_free(iommu_dom); 300 err_unregister: 301 platform_device_unregister(pdev); 302 of_node_put(np); 303 return ret; 304 } 305 306 void venus_firmware_deinit(struct venus_core *core) 307 { 308 struct iommu_domain *iommu; 309 310 if (!core->fw.dev) 311 return; 312 313 iommu = core->fw.iommu_domain; 314 315 iommu_detach_device(iommu, core->fw.dev); 316 317 if (core->fw.iommu_domain) { 318 iommu_domain_free(iommu); 319 core->fw.iommu_domain = NULL; 320 } 321 322 platform_device_unregister(to_platform_device(core->fw.dev)); 323 } 324