1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Linaro Ltd. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/firmware.h> 8 #include <linux/kernel.h> 9 #include <linux/iommu.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_reserved_mem.h> 14 #include <linux/platform_device.h> 15 #include <linux/of_device.h> 16 #include <linux/firmware/qcom/qcom_scm.h> 17 #include <linux/sizes.h> 18 #include <linux/soc/qcom/mdt_loader.h> 19 20 #include "core.h" 21 #include "firmware.h" 22 #include "hfi_venus_io.h" 23 24 #define VENUS_PAS_ID 9 25 #define VENUS_FW_MEM_SIZE (6 * SZ_1M) 26 #define VENUS_FW_START_ADDR 0x0 27 28 static void venus_reset_cpu(struct venus_core *core) 29 { 30 u32 fw_size = core->fw.mapped_mem_size; 31 void __iomem *wrapper_base; 32 33 if (IS_IRIS2(core) || IS_IRIS2_1(core)) 34 wrapper_base = core->wrapper_tz_base; 35 else 36 wrapper_base = core->wrapper_base; 37 38 writel(0, wrapper_base + WRAPPER_FW_START_ADDR); 39 writel(fw_size, wrapper_base + WRAPPER_FW_END_ADDR); 40 writel(0, wrapper_base + WRAPPER_CPA_START_ADDR); 41 writel(fw_size, wrapper_base + WRAPPER_CPA_END_ADDR); 42 writel(fw_size, wrapper_base + WRAPPER_NONPIX_START_ADDR); 43 writel(fw_size, wrapper_base + WRAPPER_NONPIX_END_ADDR); 44 45 if (IS_IRIS2(core) || IS_IRIS2_1(core)) { 46 /* Bring XTSS out of reset */ 47 writel(0, wrapper_base + WRAPPER_TZ_XTSS_SW_RESET); 48 } else { 49 writel(0x0, wrapper_base + WRAPPER_CPU_CGC_DIS); 50 writel(0x0, wrapper_base + WRAPPER_CPU_CLOCK_CONFIG); 51 52 /* Bring ARM9 out of reset */ 53 writel(0, wrapper_base + WRAPPER_A9SS_SW_RESET); 54 } 55 } 56 57 int venus_set_hw_state(struct venus_core *core, bool resume) 58 { 59 int ret; 60 61 if (core->use_tz) { 62 ret = qcom_scm_set_remote_state(resume, 0); 63 if (resume && ret == -EINVAL) 64 ret = 0; 65 return ret; 66 } 67 68 if (resume) { 69 venus_reset_cpu(core); 70 } else { 71 if (IS_IRIS2(core) || IS_IRIS2_1(core)) 72 writel(WRAPPER_XTSS_SW_RESET_BIT, 73 core->wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET); 74 else 75 writel(WRAPPER_A9SS_SW_RESET_BIT, 76 core->wrapper_base + WRAPPER_A9SS_SW_RESET); 77 } 78 79 return 0; 80 } 81 82 static int venus_load_fw(struct venus_core *core, const char *fwname, 83 phys_addr_t *mem_phys, size_t *mem_size) 84 { 85 const struct firmware *mdt; 86 struct reserved_mem *rmem; 87 struct device_node *node; 88 struct device *dev; 89 ssize_t fw_size; 90 void *mem_va; 91 int ret; 92 93 *mem_phys = 0; 94 *mem_size = 0; 95 96 dev = core->dev; 97 node = of_parse_phandle(dev->of_node, "memory-region", 0); 98 if (!node) { 99 dev_err(dev, "no memory-region specified\n"); 100 return -EINVAL; 101 } 102 103 rmem = of_reserved_mem_lookup(node); 104 of_node_put(node); 105 if (!rmem) { 106 dev_err(dev, "failed to lookup reserved memory-region\n"); 107 return -EINVAL; 108 } 109 110 ret = request_firmware(&mdt, fwname, dev); 111 if (ret < 0) 112 return ret; 113 114 fw_size = qcom_mdt_get_size(mdt); 115 if (fw_size < 0) { 116 ret = fw_size; 117 goto err_release_fw; 118 } 119 120 *mem_phys = rmem->base; 121 *mem_size = rmem->size; 122 123 if (*mem_size < fw_size || fw_size > VENUS_FW_MEM_SIZE) { 124 ret = -EINVAL; 125 goto err_release_fw; 126 } 127 128 mem_va = memremap(*mem_phys, *mem_size, MEMREMAP_WC); 129 if (!mem_va) { 130 dev_err(dev, "unable to map memory region %pa size %#zx\n", mem_phys, *mem_size); 131 ret = -ENOMEM; 132 goto err_release_fw; 133 } 134 135 if (core->use_tz) 136 ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, 137 mem_va, *mem_phys, *mem_size, NULL); 138 else 139 ret = qcom_mdt_load_no_init(dev, mdt, fwname, mem_va, 140 *mem_phys, *mem_size, NULL); 141 142 memunmap(mem_va); 143 err_release_fw: 144 release_firmware(mdt); 145 return ret; 146 } 147 148 static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys, 149 size_t mem_size) 150 { 151 struct iommu_domain *iommu; 152 struct device *dev; 153 int ret; 154 155 dev = core->fw.dev; 156 if (!dev) 157 return -EPROBE_DEFER; 158 159 iommu = core->fw.iommu_domain; 160 core->fw.mapped_mem_size = mem_size; 161 162 ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size, 163 IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); 164 if (ret) { 165 dev_err(dev, "could not map video firmware region\n"); 166 return ret; 167 } 168 169 venus_reset_cpu(core); 170 171 return 0; 172 } 173 174 static int venus_shutdown_no_tz(struct venus_core *core) 175 { 176 const size_t mapped = core->fw.mapped_mem_size; 177 struct iommu_domain *iommu; 178 size_t unmapped; 179 u32 reg; 180 struct device *dev = core->fw.dev; 181 void __iomem *wrapper_base = core->wrapper_base; 182 void __iomem *wrapper_tz_base = core->wrapper_tz_base; 183 184 if (IS_IRIS2(core) || IS_IRIS2_1(core)) { 185 /* Assert the reset to XTSS */ 186 reg = readl(wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET); 187 reg |= WRAPPER_XTSS_SW_RESET_BIT; 188 writel(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET); 189 } else { 190 /* Assert the reset to ARM9 */ 191 reg = readl(wrapper_base + WRAPPER_A9SS_SW_RESET); 192 reg |= WRAPPER_A9SS_SW_RESET_BIT; 193 writel(reg, wrapper_base + WRAPPER_A9SS_SW_RESET); 194 } 195 196 iommu = core->fw.iommu_domain; 197 198 if (core->fw.mapped_mem_size && iommu) { 199 unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped); 200 201 if (unmapped != mapped) 202 dev_err(dev, "failed to unmap firmware\n"); 203 else 204 core->fw.mapped_mem_size = 0; 205 } 206 207 return 0; 208 } 209 210 int venus_firmware_cfg(struct venus_core *core) 211 { 212 void __iomem *cpu_cs_base = core->cpu_cs_base; 213 214 if (IS_AR50_LITE(core)) 215 writel(CPU_CS_VCICMD_ARP_OFF, cpu_cs_base + CPU_CS_VCICMD); 216 217 return 0; 218 } 219 220 int venus_boot(struct venus_core *core) 221 { 222 struct device *dev = core->dev; 223 const struct venus_resources *res = core->res; 224 const char *fwpath = NULL; 225 phys_addr_t mem_phys; 226 size_t mem_size; 227 int ret; 228 229 if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || 230 (core->use_tz && !qcom_scm_is_available())) 231 return -EPROBE_DEFER; 232 233 ret = of_property_read_string_index(dev->of_node, "firmware-name", 0, 234 &fwpath); 235 if (ret) 236 fwpath = core->res->fwname; 237 238 ret = venus_load_fw(core, fwpath, &mem_phys, &mem_size); 239 if (ret) { 240 dev_err(dev, "fail to load video firmware\n"); 241 return -EINVAL; 242 } 243 244 core->fw.mem_size = mem_size; 245 core->fw.mem_phys = mem_phys; 246 247 if (core->use_tz) 248 ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); 249 else 250 ret = venus_boot_no_tz(core, mem_phys, mem_size); 251 252 if (ret) 253 return ret; 254 255 if (core->use_tz && res->cp_size) { 256 /* 257 * Clues for porting using downstream data: 258 * cp_start = 0 259 * cp_size = venus_ns/virtual-addr-pool[0] - yes, address and not size! 260 * This works, as the non-secure context bank is placed 261 * contiguously right after the Content Protection region. 262 * 263 * cp_nonpixel_start = venus_sec_non_pixel/virtual-addr-pool[0] 264 * cp_nonpixel_size = venus_sec_non_pixel/virtual-addr-pool[1] 265 */ 266 ret = qcom_scm_mem_protect_video_var(res->cp_start, 267 res->cp_size, 268 res->cp_nonpixel_start, 269 res->cp_nonpixel_size); 270 if (ret) { 271 qcom_scm_pas_shutdown(VENUS_PAS_ID); 272 dev_err(dev, "set virtual address ranges fail (%d)\n", 273 ret); 274 return ret; 275 } 276 } 277 278 return 0; 279 } 280 281 int venus_shutdown(struct venus_core *core) 282 { 283 int ret; 284 285 if (core->use_tz) 286 ret = qcom_scm_pas_shutdown(VENUS_PAS_ID); 287 else 288 ret = venus_shutdown_no_tz(core); 289 290 return ret; 291 } 292 293 int venus_firmware_check(struct venus_core *core) 294 { 295 const struct firmware_version *req = core->res->min_fw; 296 const struct firmware_version *run = &core->venus_ver; 297 298 if (!req) 299 return 0; 300 301 if (!is_fw_rev_or_newer(core, req->major, req->minor, req->rev)) 302 goto error; 303 304 return 0; 305 error: 306 dev_err(core->dev, "Firmware v%d.%d.%d < v%d.%d.%d\n", 307 run->major, run->minor, run->rev, 308 req->major, req->minor, req->rev); 309 310 return -EINVAL; 311 } 312 313 int venus_firmware_init(struct venus_core *core) 314 { 315 struct platform_device_info info; 316 struct iommu_domain *iommu_dom; 317 struct platform_device *pdev; 318 struct device_node *np; 319 int ret; 320 321 np = of_get_child_by_name(core->dev->of_node, "video-firmware"); 322 if (!np) { 323 core->use_tz = true; 324 return 0; 325 } 326 327 memset(&info, 0, sizeof(info)); 328 info.fwnode = &np->fwnode; 329 info.parent = core->dev; 330 info.name = np->name; 331 info.dma_mask = DMA_BIT_MASK(32); 332 333 pdev = platform_device_register_full(&info); 334 if (IS_ERR(pdev)) { 335 of_node_put(np); 336 return PTR_ERR(pdev); 337 } 338 339 pdev->dev.of_node = np; 340 341 ret = of_dma_configure(&pdev->dev, np, true); 342 if (ret) { 343 dev_err(core->dev, "dma configure fail\n"); 344 goto err_unregister; 345 } 346 347 core->fw.dev = &pdev->dev; 348 349 iommu_dom = iommu_paging_domain_alloc(core->fw.dev); 350 if (IS_ERR(iommu_dom)) { 351 dev_err(core->fw.dev, "Failed to allocate iommu domain\n"); 352 ret = PTR_ERR(iommu_dom); 353 goto err_unregister; 354 } 355 356 ret = iommu_attach_device(iommu_dom, core->fw.dev); 357 if (ret) { 358 dev_err(core->fw.dev, "could not attach device\n"); 359 goto err_iommu_free; 360 } 361 362 core->fw.iommu_domain = iommu_dom; 363 364 of_node_put(np); 365 366 return 0; 367 368 err_iommu_free: 369 iommu_domain_free(iommu_dom); 370 err_unregister: 371 platform_device_unregister(pdev); 372 of_node_put(np); 373 return ret; 374 } 375 376 void venus_firmware_deinit(struct venus_core *core) 377 { 378 struct iommu_domain *iommu; 379 380 if (!core->fw.dev) 381 return; 382 383 iommu = core->fw.iommu_domain; 384 385 iommu_detach_device(iommu, core->fw.dev); 386 387 if (core->fw.iommu_domain) { 388 iommu_domain_free(iommu); 389 core->fw.iommu_domain = NULL; 390 } 391 392 platform_device_unregister(to_platform_device(core->fw.dev)); 393 } 394