1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/iopoll.h> 7 #include <linux/pm_opp.h> 8 #include <linux/reset.h> 9 10 #include "iris_core.h" 11 #include "iris_instance.h" 12 #include "iris_vpu_common.h" 13 #include "iris_vpu_register_defines.h" 14 15 #define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C) 16 #define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30) 17 18 #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) 19 #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) 20 21 #define CTRL_INIT_IDLE_MSG_BMSK 0x40000000 22 #define CTRL_ERROR_STATUS__M 0xfe 23 #define CTRL_STATUS_PC_READY 0x100 24 25 #define QTBL_INFO (CPU_CS_BASE_OFFS + 0x50) 26 #define QTBL_ENABLE BIT(0) 27 28 #define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54) 29 #define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58) 30 #define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C) 31 #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) 32 #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) 33 34 static void iris_vpu_interrupt_init(struct iris_core *core) 35 { 36 u32 mask_val; 37 38 mask_val = readl(core->reg_base + WRAPPER_INTR_MASK); 39 mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BMSK | 40 WRAPPER_INTR_MASK_A2HCPU_BMSK); 41 writel(mask_val, core->reg_base + WRAPPER_INTR_MASK); 42 } 43 44 static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core) 45 { 46 u32 queue_size, value; 47 const struct vpu_ops *vpu_ops = core->iris_platform_data->vpu_ops; 48 49 /* Iris hardware requires 4K queue alignment */ 50 queue_size = ALIGN(sizeof(struct iris_hfi_queue_table_header) + 51 (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); 52 53 value = (u32)core->iface_q_table_daddr; 54 writel(value, core->reg_base + UC_REGION_ADDR); 55 56 /* Iris hardware requires 1M queue alignment */ 57 value = ALIGN(SFR_SIZE + queue_size, SZ_1M); 58 writel(value, core->reg_base + UC_REGION_SIZE); 59 60 value = (u32)core->iface_q_table_daddr; 61 writel(value, core->reg_base + QTBL_ADDR); 62 63 writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); 64 65 if (core->sfr_daddr) { 66 value = (u32)core->sfr_daddr + core->iris_firmware_data->core_arch; 67 writel(value, core->reg_base + SFR_ADDR); 68 } 69 70 if (vpu_ops->program_bootup_registers) 71 vpu_ops->program_bootup_registers(core); 72 } 73 74 int iris_vpu_boot_firmware(struct iris_core *core) 75 { 76 u32 ctrl_init = BIT(0), ctrl_status = 0, count = 0, max_tries = 1000; 77 78 iris_vpu_setup_ucregion_memory_map(core); 79 80 writel(ctrl_init, core->reg_base + CTRL_INIT); 81 writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); 82 83 while (!ctrl_status && count < max_tries) { 84 ctrl_status = readl(core->reg_base + CTRL_STATUS); 85 if ((ctrl_status & CTRL_ERROR_STATUS__M) == 0x4) { 86 dev_err(core->dev, "invalid setting for uc_region\n"); 87 break; 88 } 89 90 usleep_range(50, 100); 91 count++; 92 } 93 94 if (count >= max_tries) { 95 dev_err(core->dev, "error booting up iris firmware\n"); 96 return -ETIME; 97 } 98 99 writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); 100 writel(0x0, core->reg_base + CPU_CS_X2RPMH); 101 102 return 0; 103 } 104 105 void iris_vpu_raise_interrupt(struct iris_core *core) 106 { 107 writel(1 << CPU_IC_SOFTINT_H2A_SHFT, core->reg_base + CPU_IC_SOFTINT); 108 } 109 110 void iris_vpu_clear_interrupt(struct iris_core *core) 111 { 112 u32 intr_status, mask; 113 114 intr_status = readl(core->reg_base + WRAPPER_INTR_STATUS); 115 mask = (WRAPPER_INTR_STATUS_A2H_BMSK | 116 WRAPPER_INTR_STATUS_A2HWD_BMSK | 117 CTRL_INIT_IDLE_MSG_BMSK); 118 119 if (intr_status & mask) 120 core->intr_status |= intr_status; 121 122 writel(CLEAR_XTENSA2HOST_INTR, core->reg_base + CPU_CS_A2HSOFTINTCLR); 123 } 124 125 int iris_vpu_watchdog(struct iris_core *core, u32 intr_status) 126 { 127 if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK) { 128 dev_err(core->dev, "received watchdog interrupt\n"); 129 return -ETIME; 130 } 131 132 return 0; 133 } 134 135 int iris_vpu_prepare_pc(struct iris_core *core) 136 { 137 u32 wfi_status, idle_status, pc_ready; 138 u32 ctrl_status, val = 0; 139 int ret; 140 141 ctrl_status = readl(core->reg_base + CTRL_STATUS); 142 pc_ready = ctrl_status & CTRL_STATUS_PC_READY; 143 idle_status = ctrl_status & BIT(30); 144 if (pc_ready) 145 return 0; 146 147 wfi_status = readl(core->reg_base + WRAPPER_TZ_CPU_STATUS); 148 wfi_status &= BIT(0); 149 if (!wfi_status || !idle_status) 150 goto skip_power_off; 151 152 ret = core->hfi_sys_ops->sys_pc_prep(core); 153 if (ret) 154 goto skip_power_off; 155 156 ret = readl_poll_timeout(core->reg_base + CTRL_STATUS, val, 157 val & CTRL_STATUS_PC_READY, 250, 2500); 158 if (ret) 159 goto skip_power_off; 160 161 ret = readl_poll_timeout(core->reg_base + WRAPPER_TZ_CPU_STATUS, 162 val, val & BIT(0), 250, 2500); 163 if (ret) 164 goto skip_power_off; 165 166 return 0; 167 168 skip_power_off: 169 ctrl_status = readl(core->reg_base + CTRL_STATUS); 170 wfi_status = readl(core->reg_base + WRAPPER_TZ_CPU_STATUS); 171 wfi_status &= BIT(0); 172 dev_err(core->dev, "skip power collapse, wfi=%#x, idle=%#x, pcr=%#x, ctrl=%#x)\n", 173 wfi_status, idle_status, pc_ready, ctrl_status); 174 175 return -EAGAIN; 176 } 177 178 int iris_vpu_power_off_controller(struct iris_core *core) 179 { 180 u32 val = 0; 181 int ret; 182 183 writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); 184 185 if (!core->iris_platform_data->no_aon) { 186 writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); 187 188 ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, 189 val, val & BIT(0), 200, 2000); 190 if (ret) 191 goto disable_power; 192 } 193 194 writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); 195 196 ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, 197 val, val & BIT(0), 200, 2000); 198 if (ret) 199 goto disable_power; 200 201 writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); 202 203 ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, 204 val, val == 0, 200, 2000); 205 if (ret) 206 goto disable_power; 207 208 writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, 209 core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); 210 writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); 211 writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); 212 writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); 213 214 disable_power: 215 iris_disable_unprepare_clock(core, IRIS_AHB_CLK); 216 iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); 217 iris_disable_unprepare_clock(core, IRIS_AXI_CLK); 218 iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); 219 220 return 0; 221 } 222 223 void iris_vpu_power_off_hw(struct iris_core *core) 224 { 225 dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); 226 iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); 227 iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); 228 iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); 229 iris_disable_unprepare_clock(core, IRIS_HW_CLK); 230 } 231 232 void iris_vpu_power_off(struct iris_core *core) 233 { 234 iris_opp_set_rate(core->dev, 0); 235 core->iris_platform_data->vpu_ops->power_off_hw(core); 236 core->iris_platform_data->vpu_ops->power_off_controller(core); 237 iris_unset_icc_bw(core); 238 239 if (!iris_vpu_watchdog(core, core->intr_status)) 240 disable_irq_nosync(core->irq); 241 } 242 243 int iris_vpu_power_on_controller(struct iris_core *core) 244 { 245 u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; 246 int ret; 247 248 ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); 249 if (ret) 250 return ret; 251 252 ret = reset_control_bulk_reset(rst_tbl_size, core->resets); 253 if (ret) 254 goto err_disable_power; 255 256 ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); 257 if (ret) 258 goto err_disable_power; 259 260 ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK); 261 if (ret) 262 goto err_disable_axi_clock; 263 264 ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK); 265 if (ret && ret != -ENOENT) 266 goto err_disable_ctrl_clock; 267 268 return 0; 269 270 err_disable_ctrl_clock: 271 iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); 272 err_disable_axi_clock: 273 iris_disable_unprepare_clock(core, IRIS_AXI_CLK); 274 err_disable_power: 275 iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); 276 277 return ret; 278 } 279 280 int iris_vpu_power_on_hw(struct iris_core *core) 281 { 282 int ret; 283 284 ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); 285 if (ret) 286 return ret; 287 288 ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); 289 if (ret) 290 goto err_disable_power; 291 292 ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); 293 if (ret && ret != -ENOENT) 294 goto err_disable_hw_clock; 295 296 ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); 297 if (ret && ret != -ENOENT) 298 goto err_disable_hw_ahb_clock; 299 300 return 0; 301 302 err_disable_hw_ahb_clock: 303 iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); 304 err_disable_hw_clock: 305 iris_disable_unprepare_clock(core, IRIS_HW_CLK); 306 err_disable_power: 307 iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); 308 309 return ret; 310 } 311 312 int iris_vpu_set_hwmode(struct iris_core *core) 313 { 314 return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); 315 } 316 317 int iris_vpu_switch_to_hwmode(struct iris_core *core) 318 { 319 return core->iris_platform_data->vpu_ops->set_hwmode(core); 320 } 321 322 int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) 323 { 324 u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size; 325 bool handshake_done, handshake_busy; 326 u32 count = 0, val = 0; 327 int ret; 328 329 writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); 330 331 writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); 332 333 ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, 334 val, val & BIT(0), 200, 2000); 335 if (ret) 336 goto disable_power; 337 338 writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); 339 340 /* Retry up to 1000 times as recommended by hardware documentation */ 341 do { 342 /* set MNoC to low power */ 343 writel(REQ_POWER_DOWN_PREP, core->reg_base + 344 AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); 345 usleep_range(10, 20); 346 val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS); 347 348 handshake_done = val & NOC_LPI_STATUS_DONE; 349 handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); 350 351 if (handshake_done || !handshake_busy) 352 break; 353 354 writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); 355 usleep_range(10, 20); 356 357 } while (++count < 1000); 358 359 if (!handshake_done && handshake_busy) 360 dev_err(core->dev, "LPI handshake timeout\n"); 361 362 ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS, 363 val, val & BIT(0), 200, 2000); 364 if (ret) 365 goto disable_power; 366 367 writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL); 368 369 writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); 370 371 readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, 372 val, val == 0, 200, 2000); 373 374 disable_power: 375 iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); 376 iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); 377 iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); 378 379 iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); 380 381 reset_control_bulk_reset(clk_rst_tbl_size, core->resets); 382 383 return 0; 384 } 385 386 int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) 387 { 388 int ret; 389 390 ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); 391 if (ret) 392 return ret; 393 394 ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK); 395 if (ret) 396 goto err_disable_power; 397 398 ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK); 399 if (ret) 400 goto err_disable_axi1_clk; 401 402 ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK); 403 if (ret) 404 goto err_disable_ctrl_free_clk; 405 406 return 0; 407 408 err_disable_ctrl_free_clk: 409 iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); 410 err_disable_axi1_clk: 411 iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); 412 err_disable_power: 413 iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); 414 415 return ret; 416 } 417 418 void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core) 419 { 420 writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0); 421 } 422 423 u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size) 424 { 425 struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; 426 struct v4l2_format *inp_f = inst->fmt_src; 427 u32 height, width, mbs_per_second, mbpf; 428 u64 fw_cycles, fw_vpp_cycles; 429 u64 vsp_cycles, vpp_cycles; 430 u32 fps = inst->frame_rate; 431 432 width = max(inp_f->fmt.pix_mp.width, inst->crop.width); 433 height = max(inp_f->fmt.pix_mp.height, inst->crop.height); 434 435 mbpf = NUM_MBS_PER_FRAME(height, width); 436 mbs_per_second = mbpf * fps; 437 438 fw_cycles = fps * caps->mb_cycles_fw; 439 fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp; 440 441 vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value); 442 /* 21 / 20 is minimum overhead factor */ 443 vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles); 444 445 /* 1.059 is multi-pipe overhead */ 446 if (inst->fw_caps[PIPE].value > 1) 447 vpp_cycles += div_u64(vpp_cycles * 59, 1000); 448 449 /* 1.05 is VPP FW overhead */ 450 if (inst->fw_caps[STAGE].value == STAGE_2) 451 vpp_cycles += div_u64(vpp_cycles * 5, 100); 452 453 vsp_cycles = fps * data_size * 8; 454 vsp_cycles = div_u64(vsp_cycles, 2); 455 /* VSP FW overhead 1.05 */ 456 vsp_cycles = div_u64(vsp_cycles * 21, 20); 457 458 if (inst->fw_caps[STAGE].value == STAGE_1) 459 vsp_cycles = vsp_cycles * 3; 460 461 return max3(vpp_cycles, vsp_cycles, fw_cycles); 462 } 463 464 int iris_vpu_power_on(struct iris_core *core) 465 { 466 u32 freq; 467 int ret; 468 469 ret = iris_set_icc_bw(core, INT_MAX); 470 if (ret) 471 goto err; 472 473 ret = core->iris_platform_data->vpu_ops->power_on_controller(core); 474 if (ret) 475 goto err_unvote_icc; 476 477 ret = core->iris_platform_data->vpu_ops->power_on_hw(core); 478 if (ret) 479 goto err_power_off_ctrl; 480 481 freq = core->power.clk_freq ? core->power.clk_freq : 482 (u32)ULONG_MAX; 483 484 iris_opp_set_rate(core->dev, freq); 485 486 iris_vpu_set_preset_registers(core); 487 488 iris_vpu_interrupt_init(core); 489 core->intr_status = 0; 490 enable_irq(core->irq); 491 492 return 0; 493 494 err_power_off_ctrl: 495 core->iris_platform_data->vpu_ops->power_off_controller(core); 496 err_unvote_icc: 497 iris_unset_icc_bw(core); 498 err: 499 dev_err(core->dev, "power on failed\n"); 500 501 return ret; 502 } 503 504 void iris_vpu_set_preset_registers(struct iris_core *core) 505 { 506 writel(0x0, core->reg_base + 0xb0088); 507 } 508