1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_VPU_BUFFER_H__ 7 #define __IRIS_VPU_BUFFER_H__ 8 9 struct iris_inst; 10 11 #define MIN_BUFFERS 4 12 13 #define DMA_ALIGNMENT 256 14 #define HFI_ALIGNMENT_4096 4096 15 16 #define NUM_HW_PIC_BUF 32 17 #define LCU_MAX_SIZE_PELS 64 18 #define LCU_MIN_SIZE_PELS 16 19 #define HDR10_HIST_EXTRADATA_SIZE (4 * 1024) 20 21 #define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf)) 22 23 #define MAX_TILE_COLUMNS 32 24 #define BIN_BUFFER_THRESHOLD (1280 * 736) 25 #define VPP_CMD_MAX_SIZE (BIT(20)) 26 #define H264D_MAX_SLICE 1800 27 28 #define SIZE_H264D_BUFTAB_T 256 29 #define SIZE_H264D_BSE_CMD_PER_BUF (32 * 4) 30 #define SIZE_H264D_VPP_CMD_PER_BUF 512 31 32 #define NUM_SLIST_BUF_H264 (256 + 32) 33 #define SIZE_SLIST_BUF_H264 512 34 #define H264_DISPLAY_BUF_SIZE 3328 35 #define H264_NUM_FRM_INFO 66 36 #define H265_NUM_TILE_COL 32 37 #define H265_NUM_TILE_ROW 128 38 #define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1) 39 #define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32)) 40 41 #define NUM_SLIST_BUF_H265 (80 + 20) 42 #define SIZE_SLIST_BUF_H265 (BIT(10)) 43 #define H265_DISPLAY_BUF_SIZE (3072) 44 #define H265_NUM_FRM_INFO (48) 45 #define SIZE_ONE_SLICE_BUF 256 46 47 #define VP9_NUM_FRAME_INFO_BUF 32 48 #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) 49 #define VP9_PROB_TABLE_SIZE (3840) 50 #define VP9_FRAME_INFO_BUF_SIZE (6144) 51 #define BUFFER_ALIGNMENT_32_BYTES 32 52 #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES) 53 #define MAX_SUPERFRAME_HEADER_LEN (34) 54 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 55 #define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64 56 #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 57 #define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) 58 #define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) 59 #define VP9_UDC_HEADER_BUF_SIZE (3 * 128) 60 61 #define SIZE_SEI_USERDATA 4096 62 #define SIZE_DOLBY_RPU_METADATA (41 * 1024) 63 #define H264_CABAC_HDR_RATIO_HD_TOT 1 64 #define H264_CABAC_RES_RATIO_HD_TOT 3 65 #define H265D_MAX_SLICE 1200 66 #define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T 67 #define H265_CABAC_HDR_RATIO_HD_TOT 2 68 #define H265_CABAC_RES_RATIO_HD_TOT 2 69 #define SIZE_H265D_VPP_CMD_PER_BUF (256) 70 71 #define VPX_DECODER_FRAME_CONCURENCY_LVL (2) 72 #define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1 73 #define VPX_DECODER_FRAME_BIN_RES_BUDGET 3 74 #define VPX_DECODER_FRAME_BIN_DENOMINATOR 2 75 76 #define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2) 77 78 #define SIZE_H264D_HW_PIC_T (BIT(11)) 79 80 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 81 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 82 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 83 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 84 85 #define AV1_CABAC_HDR_RATIO_HD_TOT 2 86 #define AV1_CABAC_RES_RATIO_HD_TOT 2 87 #define AV1D_LCU_MAX_SIZE_PELS 128 88 #define AV1D_LCU_MIN_SIZE_PELS 64 89 #define AV1D_MAX_TILE_COLS 64 90 #define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 91 #define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 92 #define AV1D_NUM_HW_PIC_BUF 16 93 #define AV1D_NUM_FRAME_HEADERS 16 94 #define SIZE_AV1D_SEQUENCE_HEADER 768 95 #define SIZE_AV1D_METADATA 512 96 #define SIZE_AV1D_FRAME_HEADER 1280 97 #define SIZE_AV1D_TILE_OFFSET 65536 98 #define SIZE_AV1D_QM 3328 99 #define SIZE_AV1D_PROB_TABLE 22784 100 101 #define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256)) 102 #define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096) 103 #define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3) 104 #define SIZE_LAMBDA_LUT (256 * 11) 105 106 #define HFI_COL_FMT_NV12C_Y_TILE_HEIGHT (8) 107 #define HFI_COL_FMT_NV12C_Y_TILE_WIDTH (32) 108 #define HFI_COL_FMT_TP10C_Y_TILE_HEIGHT (4) 109 #define HFI_COL_FMT_TP10C_Y_TILE_WIDTH (48) 110 111 #define IRIS_METADATA_STRIDE_MULTIPLE 64 112 #define IRIS_METADATA_HEIGHT_MULTIPLE 16 113 114 #define HFI_BUFFER_ARP_ENC 204800 115 116 #define MAX_WIDTH 4096 117 #define MAX_HEIGHT 2304 118 #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16)) 119 #define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4)) 120 121 #define BITS_PER_PIX 16 122 #define NUM_LINES_LUMA 10 123 #define NUM_LINES_CHROMA 6 124 #define AV1D_LCU_MAX_SIZE_PELS 128 125 #define AV1D_LCU_MIN_SIZE_PELS 64 126 #define AV1D_MAX_TILE_COLS 64 127 #define BITS_PER_CTRL_PACK 128 128 #define NUM_CTRL_PACK_LCU 10 129 130 static inline u32 size_h264d_lb_fe_top_data(u32 frame_width) 131 { 132 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; 133 } 134 135 static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width) 136 { 137 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 138 } 139 140 static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height) 141 { 142 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16); 143 } 144 145 static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width) 146 { 147 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 148 } 149 150 static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height) 151 { 152 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16); 153 } 154 155 static inline u32 size_h264d_lb_pe_top_data(u32 frame_width) 156 { 157 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 158 } 159 160 static inline u32 size_h264d_lb_vsp_top(u32 frame_width) 161 { 162 return (DIV_ROUND_UP(frame_width, 16) << 7); 163 } 164 165 static inline u32 size_h264d_lb_recon_dma_metadata_wr(u32 frame_height) 166 { 167 return ALIGN(frame_height, 16) * 32; 168 } 169 170 static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height) 171 { 172 return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128; 173 } 174 175 static inline u32 size_av1d_lb_fe_top_data(u32 frame_width, u32 frame_height) 176 { 177 return (ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * 178 ((BITS_PER_PIX * NUM_LINES_LUMA) >> 3) + 179 ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * 180 ((BITS_PER_PIX * NUM_LINES_CHROMA) >> 3) * 2); 181 } 182 183 static inline u32 size_av1d_lb_fe_left_data(u32 frame_width, u32 frame_height) 184 { 185 return (32 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 186 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 187 AV1D_LCU_MIN_SIZE_PELS * 16) + 188 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + 189 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 190 AV1D_LCU_MIN_SIZE_PELS * 8) * 2 + 191 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 192 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 193 AV1D_LCU_MIN_SIZE_PELS * 16) + 194 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + 195 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 196 AV1D_LCU_MIN_SIZE_PELS * 12) * 2 + 197 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 198 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 199 AV1D_LCU_MIN_SIZE_PELS * 16) + 200 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 201 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 202 AV1D_LCU_MIN_SIZE_PELS * 16) + 203 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + 204 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 205 AV1D_LCU_MIN_SIZE_PELS * 12) * 2); 206 } 207 208 static inline u32 size_av1d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) 209 { 210 return (NUM_CTRL_PACK_LCU * ((frame_width + AV1D_LCU_MIN_SIZE_PELS - 1) / 211 AV1D_LCU_MIN_SIZE_PELS) * BITS_PER_CTRL_PACK / 8); 212 } 213 214 static inline u32 size_av1d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) 215 { 216 return (16 * ((ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 16) + 217 (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 218 AV1D_LCU_MIN_SIZE_PELS)) + 219 3 * 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 220 AV1D_LCU_MIN_SIZE_PELS)); 221 } 222 223 static inline u32 size_av1d_lb_se_top_ctrl(u32 frame_width, u32 frame_height) 224 { 225 return (((frame_width + 7) / 8) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE); 226 } 227 228 static inline u32 size_av1d_lb_se_left_ctrl(u32 frame_width, u32 frame_height) 229 { 230 return (max(((frame_height + 15) / 16) * 231 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 232 max(((frame_height + 31) / 32) * 233 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 234 ((frame_height + 63) / 64) * 235 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE))); 236 } 237 238 static inline u32 size_av1d_lb_pe_top_data(u32 frame_width, u32 frame_height) 239 { 240 return (max(((frame_width + 15) / 16) * 241 MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, 242 max(((frame_width + 31) / 32) * 243 MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, 244 ((frame_width + 63) / 64) * 245 MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE))); 246 } 247 248 static inline u32 size_av1d_lb_vsp_top(u32 frame_width, u32 frame_height) 249 { 250 return (max(((frame_width + 63) / 64) * 1280, 251 ((frame_width + 127) / 128) * MAX_HEIGHT)); 252 } 253 254 static inline u32 size_av1d_lb_recon_dma_metadata_wr(u32 frame_width, 255 u32 frame_height) 256 { 257 return ((ALIGN(frame_height, 8) / (4 / 2)) * 64); 258 } 259 260 static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height) 261 { 262 return size_h264d_qp(frame_width, frame_height); 263 } 264 265 u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); 266 u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); 267 int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type); 268 269 #endif 270