1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_VPU_BUFFER_H__ 7 #define __IRIS_VPU_BUFFER_H__ 8 9 struct iris_inst; 10 11 #define MIN_BUFFERS 4 12 13 #define DMA_ALIGNMENT 256 14 #define HFI_ALIGNMENT_4096 4096 15 16 #define NUM_HW_PIC_BUF 32 17 #define LCU_MAX_SIZE_PELS 64 18 #define LCU_MIN_SIZE_PELS 16 19 #define HDR10_HIST_EXTRADATA_SIZE (4 * 1024) 20 21 #define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf)) 22 23 #define MAX_TILE_COLUMNS 32 24 #define BIN_BUFFER_THRESHOLD (1280 * 736) 25 #define VPP_CMD_MAX_SIZE (BIT(20)) 26 #define H264D_MAX_SLICE 1800 27 28 #define SIZE_H264D_BUFTAB_T 256 29 #define SIZE_H264D_BSE_CMD_PER_BUF (32 * 4) 30 #define SIZE_H264D_VPP_CMD_PER_BUF 512 31 32 #define NUM_SLIST_BUF_H264 (256 + 32) 33 #define SIZE_SLIST_BUF_H264 512 34 #define H264_DISPLAY_BUF_SIZE 3328 35 #define H264_NUM_FRM_INFO 66 36 #define H265_NUM_TILE_COL 32 37 #define H265_NUM_TILE_ROW 128 38 #define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1) 39 #define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32)) 40 41 #define NUM_SLIST_BUF_H265 (80 + 20) 42 #define SIZE_SLIST_BUF_H265 (BIT(10)) 43 #define H265_DISPLAY_BUF_SIZE (3072) 44 #define H265_NUM_FRM_INFO (48) 45 #define SIZE_ONE_SLICE_BUF 256 46 47 #define VP9_NUM_FRAME_INFO_BUF 32 48 #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) 49 #define VP9_PROB_TABLE_SIZE (3840) 50 #define VP9_FRAME_INFO_BUF_SIZE (6144) 51 #define VP9_FRAME_INFO_BUF_SIZE_VPU4X (6400) 52 #define BUFFER_ALIGNMENT_16_BYTES 16 53 #define BUFFER_ALIGNMENT_32_BYTES 32 54 #define BUFFER_ALIGNMENT_64_BYTES 64 55 #define BUFFER_ALIGNMENT_256_BYTES 256 56 #define BUFFER_ALIGNMENT_512_BYTES 512 57 #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES) 58 #define MAX_SUPERFRAME_HEADER_LEN (34) 59 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 60 #define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64 61 #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 62 #define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) 63 #define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) 64 #define VP9_UDC_HEADER_BUF_SIZE (3 * 128) 65 66 #define SIZE_SEI_USERDATA 4096 67 #define SIZE_DOLBY_RPU_METADATA (41 * 1024) 68 #define H264_CABAC_HDR_RATIO_HD_TOT 1 69 #define H264_CABAC_RES_RATIO_HD_TOT 3 70 #define H265D_MAX_SLICE 1200 71 #define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T 72 #define H265_CABAC_HDR_RATIO_HD_TOT 2 73 #define H265_CABAC_RES_RATIO_HD_TOT 2 74 #define SIZE_H265D_VPP_CMD_PER_BUF (256) 75 #define SIZE_THREE_DIMENSION_USERDATA 768 76 #define SIZE_H265D_ARP 9728 77 78 #define VPX_DECODER_FRAME_CONCURENCY_LVL (2) 79 #define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1 80 #define VPX_DECODER_FRAME_BIN_RES_BUDGET 3 81 #define VPX_DECODER_FRAME_BIN_DENOMINATOR 2 82 83 #define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2) 84 85 #define SIZE_H264D_HW_PIC_T (BIT(11)) 86 87 #define FE_LFT_CTRL_LINE_NUMBERS 4 88 #define FE_LFT_DB_DATA_LINE_NUMBERS 2 89 #define FE_LFT_LR_DATA_LINE_NUMBERS 4 90 #define FE_TOP_CTRL_LINE_NUMBERS 3 91 #define FE_TOP_DATA_LUMA_LINE_NUMBERS 2 92 #define FE_TOP_DATA_CHROMA_LINE_NUMBERS 3 93 #define FE_SDC_DATA_PER_BLOCK 16 94 #define SE_CTRL_DATA_PER_BLOCK 2020 95 96 #define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 97 #define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 98 99 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 100 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 101 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 102 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 103 104 #define AV1_CABAC_HDR_RATIO_HD_TOT 2 105 #define AV1_CABAC_RES_RATIO_HD_TOT 2 106 #define AV1D_LCU_MAX_SIZE_PELS 128 107 #define AV1D_LCU_MIN_SIZE_PELS 64 108 #define AV1D_MAX_TILE_COLS 64 109 #define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 110 #define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 111 #define AV1D_NUM_HW_PIC_BUF 16 112 #define AV1D_NUM_FRAME_HEADERS 16 113 #define SIZE_AV1D_SEQUENCE_HEADER 768 114 #define SIZE_AV1D_METADATA 512 115 #define SIZE_AV1D_FRAME_HEADER 1280 116 #define SIZE_AV1D_TILE_OFFSET 65536 117 #define SIZE_AV1D_QM 3328 118 #define SIZE_AV1D_PROB_TABLE 22784 119 120 #define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256)) 121 #define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096) 122 #define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3) 123 #define SIZE_LAMBDA_LUT (256 * 11) 124 125 #define HFI_COL_FMT_NV12C_Y_TILE_HEIGHT (8) 126 #define HFI_COL_FMT_NV12C_Y_TILE_WIDTH (32) 127 #define HFI_COL_FMT_TP10C_Y_TILE_HEIGHT (4) 128 #define HFI_COL_FMT_TP10C_Y_TILE_WIDTH (48) 129 130 #define IRIS_METADATA_STRIDE_MULTIPLE 64 131 #define IRIS_METADATA_HEIGHT_MULTIPLE 16 132 133 #define HFI_BUFFER_ARP_ENC 204800 134 135 #define LOG2_16 4 136 #define LOG2_32 5 137 #define LLB_UNIT_SIZE 16 138 139 #define MAX_WIDTH 4096 140 #define MAX_HEIGHT 2304 141 #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16)) 142 #define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4)) 143 144 #define BITS_PER_PIX 16 145 #define NUM_LINES_LUMA 10 146 #define NUM_LINES_CHROMA 6 147 #define AV1D_LCU_MAX_SIZE_PELS 128 148 #define AV1D_LCU_MIN_SIZE_PELS 64 149 #define AV1D_MAX_TILE_COLS 64 150 #define BITS_PER_CTRL_PACK 128 151 #define NUM_CTRL_PACK_LCU 10 152 153 static inline u32 size_h264d_lb_fe_top_data(u32 frame_width) 154 { 155 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; 156 } 157 158 static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width) 159 { 160 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 161 } 162 163 static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height) 164 { 165 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16); 166 } 167 168 static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width) 169 { 170 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 171 } 172 173 static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height) 174 { 175 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16); 176 } 177 178 static inline u32 size_h264d_lb_pe_top_data(u32 frame_width) 179 { 180 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 181 } 182 183 static inline u32 size_h264d_lb_vsp_top(u32 frame_width) 184 { 185 return (DIV_ROUND_UP(frame_width, 16) << 7); 186 } 187 188 static inline u32 size_h264d_lb_recon_dma_metadata_wr(u32 frame_height) 189 { 190 return ALIGN(frame_height, 16) * 32; 191 } 192 193 static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height) 194 { 195 return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128; 196 } 197 198 static inline u32 size_av1d_lb_fe_top_data(u32 frame_width, u32 frame_height) 199 { 200 return (ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * 201 ((BITS_PER_PIX * NUM_LINES_LUMA) >> 3) + 202 ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * 203 ((BITS_PER_PIX * NUM_LINES_CHROMA) >> 3) * 2); 204 } 205 206 static inline u32 size_av1d_lb_fe_left_data(u32 frame_width, u32 frame_height) 207 { 208 return (32 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 209 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 210 AV1D_LCU_MIN_SIZE_PELS * 16) + 211 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + 212 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 213 AV1D_LCU_MIN_SIZE_PELS * 8) * 2 + 214 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 215 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 216 AV1D_LCU_MIN_SIZE_PELS * 16) + 217 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + 218 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 219 AV1D_LCU_MIN_SIZE_PELS * 12) * 2 + 220 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 221 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 222 AV1D_LCU_MIN_SIZE_PELS * 16) + 223 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + 224 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 225 AV1D_LCU_MIN_SIZE_PELS * 16) + 226 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + 227 ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 228 AV1D_LCU_MIN_SIZE_PELS * 12) * 2); 229 } 230 231 static inline u32 size_av1d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) 232 { 233 return (NUM_CTRL_PACK_LCU * ((frame_width + AV1D_LCU_MIN_SIZE_PELS - 1) / 234 AV1D_LCU_MIN_SIZE_PELS) * BITS_PER_CTRL_PACK / 8); 235 } 236 237 static inline u32 size_av1d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) 238 { 239 return (16 * ((ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 16) + 240 (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 241 AV1D_LCU_MIN_SIZE_PELS)) + 242 3 * 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 243 AV1D_LCU_MIN_SIZE_PELS)); 244 } 245 246 static inline u32 size_av1d_lb_se_top_ctrl(u32 frame_width, u32 frame_height) 247 { 248 return (((frame_width + 7) / 8) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE); 249 } 250 251 static inline u32 size_av1d_lb_se_left_ctrl(u32 frame_width, u32 frame_height) 252 { 253 return (max(((frame_height + 15) / 16) * 254 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 255 max(((frame_height + 31) / 32) * 256 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 257 ((frame_height + 63) / 64) * 258 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE))); 259 } 260 261 static inline u32 size_av1d_lb_pe_top_data(u32 frame_width, u32 frame_height) 262 { 263 return (max(((frame_width + 15) / 16) * 264 MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, 265 max(((frame_width + 31) / 32) * 266 MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, 267 ((frame_width + 63) / 64) * 268 MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE))); 269 } 270 271 static inline u32 size_av1d_lb_vsp_top(u32 frame_width, u32 frame_height) 272 { 273 return (max(((frame_width + 63) / 64) * 1280, 274 ((frame_width + 127) / 128) * MAX_HEIGHT)); 275 } 276 277 static inline u32 size_av1d_lb_recon_dma_metadata_wr(u32 frame_width, 278 u32 frame_height) 279 { 280 return ((ALIGN(frame_height, 8) / (4 / 2)) * 64); 281 } 282 283 static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height) 284 { 285 return size_h264d_qp(frame_width, frame_height); 286 } 287 288 u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); 289 u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); 290 u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); 291 int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type); 292 293 #endif 294