1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef __IRIS_VPU_BUFFER_H__ 7 #define __IRIS_VPU_BUFFER_H__ 8 9 struct iris_inst; 10 11 #define MIN_BUFFERS 4 12 13 #define DMA_ALIGNMENT 256 14 15 #define NUM_HW_PIC_BUF 32 16 #define LCU_MAX_SIZE_PELS 64 17 #define LCU_MIN_SIZE_PELS 16 18 #define HDR10_HIST_EXTRADATA_SIZE (4 * 1024) 19 20 #define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf)) 21 22 #define MAX_TILE_COLUMNS 32 23 #define BIN_BUFFER_THRESHOLD (1280 * 736) 24 #define VPP_CMD_MAX_SIZE (BIT(20)) 25 #define H264D_MAX_SLICE 1800 26 27 #define SIZE_H264D_BUFTAB_T 256 28 #define SIZE_H264D_BSE_CMD_PER_BUF (32 * 4) 29 #define SIZE_H264D_VPP_CMD_PER_BUF 512 30 31 #define NUM_SLIST_BUF_H264 (256 + 32) 32 #define SIZE_SLIST_BUF_H264 512 33 #define H264_DISPLAY_BUF_SIZE 3328 34 #define H264_NUM_FRM_INFO 66 35 #define H265_NUM_TILE_COL 32 36 #define H265_NUM_TILE_ROW 128 37 #define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1) 38 #define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32)) 39 40 #define NUM_SLIST_BUF_H265 (80 + 20) 41 #define SIZE_SLIST_BUF_H265 (BIT(10)) 42 #define H265_DISPLAY_BUF_SIZE (3072) 43 #define H265_NUM_FRM_INFO (48) 44 45 #define VP9_NUM_FRAME_INFO_BUF 32 46 #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) 47 #define VP9_PROB_TABLE_SIZE (3840) 48 #define VP9_FRAME_INFO_BUF_SIZE (6144) 49 #define BUFFER_ALIGNMENT_32_BYTES 32 50 #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES) 51 #define MAX_SUPERFRAME_HEADER_LEN (34) 52 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 53 #define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64 54 #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 55 #define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) 56 #define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) 57 #define VP9_UDC_HEADER_BUF_SIZE (3 * 128) 58 59 #define SIZE_SEI_USERDATA 4096 60 #define SIZE_DOLBY_RPU_METADATA (41 * 1024) 61 #define H264_CABAC_HDR_RATIO_HD_TOT 1 62 #define H264_CABAC_RES_RATIO_HD_TOT 3 63 #define H265D_MAX_SLICE 1200 64 #define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T 65 #define H265_CABAC_HDR_RATIO_HD_TOT 2 66 #define H265_CABAC_RES_RATIO_HD_TOT 2 67 #define SIZE_H265D_VPP_CMD_PER_BUF (256) 68 69 #define VPX_DECODER_FRAME_CONCURENCY_LVL (2) 70 #define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1 71 #define VPX_DECODER_FRAME_BIN_RES_BUDGET 3 72 #define VPX_DECODER_FRAME_BIN_DENOMINATOR 2 73 74 #define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2) 75 76 #define SIZE_H264D_HW_PIC_T (BIT(11)) 77 78 #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 79 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 80 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 81 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 82 83 static inline u32 size_h264d_lb_fe_top_data(u32 frame_width) 84 { 85 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; 86 } 87 88 static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width) 89 { 90 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 91 } 92 93 static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height) 94 { 95 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16); 96 } 97 98 static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width) 99 { 100 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 101 } 102 103 static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height) 104 { 105 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16); 106 } 107 108 static inline u32 size_h264d_lb_pe_top_data(u32 frame_width) 109 { 110 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16); 111 } 112 113 static inline u32 size_h264d_lb_vsp_top(u32 frame_width) 114 { 115 return (DIV_ROUND_UP(frame_width, 16) << 7); 116 } 117 118 static inline u32 size_h264d_lb_recon_dma_metadata_wr(u32 frame_height) 119 { 120 return ALIGN(frame_height, 16) * 32; 121 } 122 123 static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height) 124 { 125 return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128; 126 } 127 128 int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); 129 int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type); 130 131 #endif 132