1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include "iris_instance.h" 7 #include "iris_vpu_buffer.h" 8 #include "iris_hfi_gen1_defines.h" 9 #include "iris_hfi_gen2_defines.h" 10 11 #define HFI_MAX_COL_FRAME 6 12 13 #ifndef SYSTEM_LAL_TILE10 14 #define SYSTEM_LAL_TILE10 192 15 #endif 16 17 static u32 size_h264d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 18 { 19 u32 size_yuv, size_bin_hdr, size_bin_res; 20 21 size_yuv = ((frame_width * frame_height) <= BIN_BUFFER_THRESHOLD) ? 22 ((BIN_BUFFER_THRESHOLD * 3) >> 1) : 23 ((frame_width * frame_height * 3) >> 1); 24 size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT; 25 size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT; 26 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes, 27 DMA_ALIGNMENT) * num_vpp_pipes; 28 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes, 29 DMA_ALIGNMENT) * num_vpp_pipes; 30 31 return size_bin_hdr + size_bin_res; 32 } 33 34 static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 35 { 36 u32 n_aligned_h = ALIGN(frame_height, 16); 37 u32 n_aligned_w = ALIGN(frame_width, 16); 38 39 return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); 40 } 41 42 static u32 size_h265d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 43 { 44 u32 product = frame_width * frame_height; 45 u32 size_yuv, size_bin_hdr, size_bin_res; 46 47 size_yuv = (product <= BIN_BUFFER_THRESHOLD) ? 48 ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); 49 size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT; 50 size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT; 51 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes, DMA_ALIGNMENT) * num_vpp_pipes; 52 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes, DMA_ALIGNMENT) * num_vpp_pipes; 53 54 return size_bin_hdr + size_bin_res; 55 } 56 57 static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 58 { 59 u32 _size_yuv = ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2; 60 u32 _size = ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) * 61 VPX_DECODER_FRAME_BIN_HDR_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR * 62 VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT) + 63 ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) * 64 VPX_DECODER_FRAME_BIN_RES_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR * 65 VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT); 66 67 return _size * num_vpp_pipes; 68 } 69 70 static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 71 { 72 u32 n_aligned_w = ALIGN(frame_width, 16); 73 u32 n_aligned_h = ALIGN(frame_height, 16); 74 75 return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); 76 } 77 78 static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _comv_bufcount) 79 { 80 u32 frame_height_in_mbs = DIV_ROUND_UP(frame_height, 16); 81 u32 frame_width_in_mbs = DIV_ROUND_UP(frame_width, 16); 82 u32 col_zero_aligned_width = (frame_width_in_mbs << 2); 83 u32 col_mv_aligned_width = (frame_width_in_mbs << 7); 84 u32 col_zero_size, size_colloc; 85 86 col_mv_aligned_width = ALIGN(col_mv_aligned_width, 16); 87 col_zero_aligned_width = ALIGN(col_zero_aligned_width, 16); 88 col_zero_size = col_zero_aligned_width * 89 ((frame_height_in_mbs + 1) >> 1); 90 col_zero_size = ALIGN(col_zero_size, 64); 91 col_zero_size <<= 1; 92 col_zero_size = ALIGN(col_zero_size, 512); 93 size_colloc = col_mv_aligned_width * ((frame_height_in_mbs + 1) >> 1); 94 size_colloc = ALIGN(size_colloc, 64); 95 size_colloc <<= 1; 96 size_colloc = ALIGN(size_colloc, 512); 97 size_colloc += (col_zero_size + SIZE_H264D_BUFTAB_T * 2); 98 99 return (size_colloc * (_comv_bufcount)) + 512; 100 } 101 102 static u32 hfi_buffer_comv_h265d(u32 frame_width, u32 frame_height, u32 _comv_bufcount) 103 { 104 u32 frame_height_in_mbs = (frame_height + 15) >> 4; 105 u32 frame_width_in_mbs = (frame_width + 15) >> 4; 106 u32 _size; 107 108 _size = ALIGN(((frame_width_in_mbs * frame_height_in_mbs) << 8), 512); 109 110 return (_size * (_comv_bufcount)) + 512; 111 } 112 113 static u32 size_h264d_bse_cmd_buf(u32 frame_height) 114 { 115 u32 height = ALIGN(frame_height, 32); 116 117 return min_t(u32, (DIV_ROUND_UP(height, 16) * 48), H264D_MAX_SLICE) * 118 SIZE_H264D_BSE_CMD_PER_BUF; 119 } 120 121 static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height) 122 { 123 u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * 124 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * 125 NUM_HW_PIC_BUF, DMA_ALIGNMENT); 126 _size = min_t(u32, _size, H265D_MAX_SLICE + 1); 127 _size = 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF; 128 129 return _size; 130 } 131 132 static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) 133 { 134 return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + 135 H265_NUM_FRM_INFO * H265_DISPLAY_BUF_SIZE + 136 H265_NUM_TILE * sizeof(u32) + 137 NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + 138 rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), 139 DMA_ALIGNMENT); 140 } 141 142 static inline 143 u32 hfi_iris3_vp9d_comv_size(void) 144 { 145 return (((8192 + 63) >> 6) * ((4320 + 63) >> 6) * 8 * 8 * 2 * 8); 146 } 147 148 static u32 hfi_buffer_persist_vp9d(void) 149 { 150 return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) + 151 ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) + 152 ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) + 153 ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) + 154 ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) + 155 ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, DMA_ALIGNMENT) + 156 HDR10_HIST_EXTRADATA_SIZE; 157 } 158 159 static u32 size_h264d_vpp_cmd_buf(u32 frame_height) 160 { 161 u32 size, height = ALIGN(frame_height, 32); 162 163 size = min_t(u32, (DIV_ROUND_UP(height, 16) * 48), H264D_MAX_SLICE) * 164 SIZE_H264D_VPP_CMD_PER_BUF; 165 166 return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size; 167 } 168 169 static u32 hfi_buffer_persist_h264d(void) 170 { 171 return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + 172 H264_DISPLAY_BUF_SIZE * H264_NUM_FRM_INFO + 173 NUM_HW_PIC_BUF * SIZE_SEI_USERDATA, 174 DMA_ALIGNMENT); 175 } 176 177 static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 178 { 179 u32 size_bse = size_h264d_bse_cmd_buf(frame_height); 180 u32 size_vpp = size_h264d_vpp_cmd_buf(frame_height); 181 u32 size = ALIGN(size_bse, DMA_ALIGNMENT) + 182 ALIGN(size_vpp, DMA_ALIGNMENT) + 183 ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT); 184 185 return ALIGN(size, DMA_ALIGNMENT); 186 } 187 188 static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height) 189 { 190 u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * 191 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * 192 NUM_HW_PIC_BUF, DMA_ALIGNMENT); 193 _size = min_t(u32, _size, H265D_MAX_SLICE + 1); 194 _size = ALIGN(_size, 4); 195 _size = 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF; 196 if (_size > VPP_CMD_MAX_SIZE) 197 _size = VPP_CMD_MAX_SIZE; 198 199 return _size; 200 } 201 202 static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 203 { 204 u32 _size_bse = size_h265d_bse_cmd_buf(frame_width, frame_height); 205 u32 _size_vpp = size_h265d_vpp_cmd_buf(frame_width, frame_height); 206 u32 _size = ALIGN(_size_bse, DMA_ALIGNMENT) + 207 ALIGN(_size_vpp, DMA_ALIGNMENT) + 208 ALIGN(NUM_HW_PIC_BUF * 20 * 22 * 4, DMA_ALIGNMENT) + 209 ALIGN(2 * sizeof(u16) * 210 (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * 211 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNMENT) + 212 ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT) + 213 HDR10_HIST_EXTRADATA_SIZE; 214 215 return ALIGN(_size, DMA_ALIGNMENT); 216 } 217 218 static u32 size_vpss_lb(u32 frame_width, u32 frame_height) 219 { 220 u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size; 221 u32 opb_wr_top_line_chroma_buffer_size; 222 u32 opb_wr_top_line_luma_buffer_size; 223 u32 macrotiling_size = 32; 224 225 opb_wr_top_line_luma_buffer_size = 226 ALIGN(frame_width, macrotiling_size) / macrotiling_size * 256; 227 opb_wr_top_line_luma_buffer_size = 228 ALIGN(opb_wr_top_line_luma_buffer_size, DMA_ALIGNMENT) + 229 (MAX_TILE_COLUMNS - 1) * 256; 230 opb_wr_top_line_luma_buffer_size = 231 max_t(u32, opb_wr_top_line_luma_buffer_size, (32 * ALIGN(frame_height, 8))); 232 opb_wr_top_line_chroma_buffer_size = opb_wr_top_line_luma_buffer_size; 233 opb_lb_wr_llb_uv_buffer_size = 234 ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 32); 235 opb_lb_wr_llb_y_buffer_size = 236 ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 32); 237 return opb_wr_top_line_luma_buffer_size + 238 opb_wr_top_line_chroma_buffer_size + 239 opb_lb_wr_llb_uv_buffer_size + 240 opb_lb_wr_llb_y_buffer_size; 241 } 242 243 static inline 244 u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 frame_height) 245 { 246 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * 247 (ALIGN(frame_width, 64) + 8) * 2; 248 } 249 250 static inline 251 u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) 252 { 253 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * 254 (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS); 255 } 256 257 static inline 258 u32 size_h265d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) 259 { 260 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * 261 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS); 262 } 263 264 static inline 265 u32 size_h265d_lb_se_top_ctrl(u32 frame_width, u32 frame_height) 266 { 267 return (LCU_MAX_SIZE_PELS / 8 * (128 / 8)) * ((frame_width + 15) >> 4); 268 } 269 270 static inline 271 u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 frame_height) 272 { 273 return max_t(u32, ((frame_height + 16 - 1) / 8) * 274 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 275 max_t(u32, ((frame_height + 32 - 1) / 8) * 276 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 277 ((frame_height + 64 - 1) / 8) * 278 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); 279 } 280 281 static inline 282 u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height) 283 { 284 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * 285 (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); 286 } 287 288 static inline 289 u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height) 290 { 291 return ((frame_width + 63) >> 6) * 128; 292 } 293 294 static inline 295 u32 size_h265d_lb_vsp_left(u32 frame_width, u32 frame_height) 296 { 297 return ((frame_height + 63) >> 6) * 128; 298 } 299 300 static inline 301 u32 size_h265d_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) 302 { 303 return size_h264d_lb_recon_dma_metadata_wr(frame_height); 304 } 305 306 static inline 307 u32 size_h265d_qp(u32 frame_width, u32 frame_height) 308 { 309 return size_h264d_qp(frame_width, frame_height); 310 } 311 312 static inline 313 u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes) 314 { 315 u32 vpss_lb_size = 0, _size; 316 317 _size = ALIGN(size_h265d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 318 ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 319 ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height), 320 DMA_ALIGNMENT) * num_vpp_pipes + 321 ALIGN(size_h265d_lb_se_left_ctrl(frame_width, frame_height), 322 DMA_ALIGNMENT) * num_vpp_pipes + 323 ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 324 ALIGN(size_h265d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 325 ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + 326 ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height), 327 DMA_ALIGNMENT) * num_vpp_pipes + 328 ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height), 329 DMA_ALIGNMENT) * 4 + 330 ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT); 331 if (is_opb) 332 vpss_lb_size = size_vpss_lb(frame_width, frame_height); 333 334 return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT); 335 } 336 337 static inline 338 u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) 339 { 340 return max_t(u32, ((frame_height + 15) >> 4) * 341 MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 342 max_t(u32, ((frame_height + 31) >> 5) * 343 MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 344 ((frame_height + 63) >> 6) * 345 MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); 346 } 347 348 static inline 349 u32 size_vpxd_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) 350 { 351 return ((ALIGN(frame_width, 64) + 8) * 10 * 2); 352 } 353 354 static inline 355 u32 size_vpxd_lb_se_top_ctrl(u32 frame_width, u32 frame_height) 356 { 357 return ((frame_width + 15) >> 4) * MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE; 358 } 359 360 static inline 361 u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 frame_height) 362 { 363 return max_t(u32, ((frame_height + 15) >> 4) * 364 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 365 max_t(u32, ((frame_height + 31) >> 5) * 366 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 367 ((frame_height + 63) >> 6) * 368 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); 369 } 370 371 static inline 372 u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) 373 { 374 return ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 375 BUFFER_ALIGNMENT_32_BYTES); 376 } 377 378 static inline __maybe_unused 379 u32 size_mp2d_lb_fe_top_data(u32 frame_width, u32 frame_height) 380 { 381 return ((ALIGN(frame_width, 16) + 8) * 10 * 2); 382 } 383 384 static inline 385 u32 size_vp9d_lb_fe_top_data(u32 frame_width, u32 frame_height) 386 { 387 return (ALIGN(ALIGN(frame_width, 8), 64) + 8) * 10 * 2; 388 } 389 390 static inline 391 u32 size_vp9d_lb_pe_top_data(u32 frame_width, u32 frame_height) 392 { 393 return ((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 176); 394 } 395 396 static inline 397 u32 size_vp9d_lb_vsp_top(u32 frame_width, u32 frame_height) 398 { 399 return (((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 64 * 8) + 256); 400 } 401 402 static inline 403 u32 size_vp9d_qp(u32 frame_width, u32 frame_height) 404 { 405 return size_h264d_qp(frame_width, frame_height); 406 } 407 408 static inline 409 u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 410 { 411 return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) * 412 num_vpp_pipes + 413 ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) * 414 num_vpp_pipes + 415 ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + 416 ALIGN(size_vpxd_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 417 2 * ALIGN(size_vpxd_lb_recon_dma_metadata_wr(frame_width, frame_height), 418 DMA_ALIGNMENT) + 419 ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 420 ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 421 ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 422 ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); 423 } 424 425 static inline 426 u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min, bool is_opb, 427 u32 num_vpp_pipes) 428 { 429 u32 vpss_lb_size = 0; 430 u32 _lb_size; 431 432 _lb_size = hfi_iris3_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes); 433 434 if (is_opb) 435 vpss_lb_size = size_vpss_lb(frame_width, frame_height); 436 437 return _lb_size + vpss_lb_size + 4096; 438 } 439 440 static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height, 441 bool is_opb, u32 num_vpp_pipes) 442 { 443 u32 vpss_lb_size = 0; 444 u32 size; 445 446 size = ALIGN(size_h264d_lb_fe_top_data(frame_width), DMA_ALIGNMENT) + 447 ALIGN(size_h264d_lb_fe_top_ctrl(frame_width), DMA_ALIGNMENT) + 448 ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes + 449 ALIGN(size_h264d_lb_se_top_ctrl(frame_width), DMA_ALIGNMENT) + 450 ALIGN(size_h264d_lb_se_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes + 451 ALIGN(size_h264d_lb_pe_top_data(frame_width), DMA_ALIGNMENT) + 452 ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) + 453 ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) * 2 + 454 ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT); 455 size = ALIGN(size, DMA_ALIGNMENT); 456 if (is_opb) 457 vpss_lb_size = size_vpss_lb(frame_width, frame_height); 458 459 return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT); 460 } 461 462 static u32 iris_vpu_dec_bin_size(struct iris_inst *inst) 463 { 464 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 465 struct v4l2_format *f = inst->fmt_src; 466 u32 height = f->fmt.pix_mp.height; 467 u32 width = f->fmt.pix_mp.width; 468 469 if (inst->codec == V4L2_PIX_FMT_H264) 470 return hfi_buffer_bin_h264d(width, height, num_vpp_pipes); 471 else if (inst->codec == V4L2_PIX_FMT_HEVC) 472 return hfi_buffer_bin_h265d(width, height, num_vpp_pipes); 473 else if (inst->codec == V4L2_PIX_FMT_VP9) 474 return hfi_buffer_bin_vp9d(width, height, num_vpp_pipes); 475 476 return 0; 477 } 478 479 static u32 iris_vpu_dec_comv_size(struct iris_inst *inst) 480 { 481 u32 num_comv = VIDEO_MAX_FRAME; 482 struct v4l2_format *f = inst->fmt_src; 483 u32 height = f->fmt.pix_mp.height; 484 u32 width = f->fmt.pix_mp.width; 485 486 if (inst->codec == V4L2_PIX_FMT_H264) 487 return hfi_buffer_comv_h264d(width, height, num_comv); 488 else if (inst->codec == V4L2_PIX_FMT_HEVC) 489 return hfi_buffer_comv_h265d(width, height, num_comv); 490 491 return 0; 492 } 493 494 static u32 iris_vpu_dec_persist_size(struct iris_inst *inst) 495 { 496 if (inst->codec == V4L2_PIX_FMT_H264) 497 return hfi_buffer_persist_h264d(); 498 else if (inst->codec == V4L2_PIX_FMT_HEVC) 499 return hfi_buffer_persist_h265d(0); 500 else if (inst->codec == V4L2_PIX_FMT_VP9) 501 return hfi_buffer_persist_vp9d(); 502 503 return 0; 504 } 505 506 static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst) 507 { 508 if (iris_split_mode_enabled(inst)) 509 return iris_get_buffer_size(inst, BUF_DPB); 510 else 511 return 0; 512 } 513 514 static u32 iris_vpu_dec_non_comv_size(struct iris_inst *inst) 515 { 516 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 517 struct v4l2_format *f = inst->fmt_src; 518 u32 height = f->fmt.pix_mp.height; 519 u32 width = f->fmt.pix_mp.width; 520 521 if (inst->codec == V4L2_PIX_FMT_H264) 522 return hfi_buffer_non_comv_h264d(width, height, num_vpp_pipes); 523 else if (inst->codec == V4L2_PIX_FMT_HEVC) 524 return hfi_buffer_non_comv_h265d(width, height, num_vpp_pipes); 525 526 return 0; 527 } 528 529 static u32 iris_vpu_dec_line_size(struct iris_inst *inst) 530 { 531 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 532 struct v4l2_format *f = inst->fmt_src; 533 u32 height = f->fmt.pix_mp.height; 534 u32 width = f->fmt.pix_mp.width; 535 bool is_opb = false; 536 u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count; 537 538 if (iris_split_mode_enabled(inst)) 539 is_opb = true; 540 541 if (inst->codec == V4L2_PIX_FMT_H264) 542 return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); 543 else if (inst->codec == V4L2_PIX_FMT_HEVC) 544 return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); 545 else if (inst->codec == V4L2_PIX_FMT_VP9) 546 return hfi_buffer_line_vp9d(width, height, out_min_count, is_opb, 547 num_vpp_pipes); 548 549 return 0; 550 } 551 552 static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst) 553 { 554 return iris_vpu_dec_comv_size(inst) + 555 iris_vpu_dec_non_comv_size(inst) + 556 iris_vpu_dec_line_size(inst); 557 } 558 559 static inline 560 u32 size_enc_single_pipe(u32 rc_type, u32 bitbin_size, u32 num_vpp_pipes, 561 u32 frame_width, u32 frame_height, u32 lcu_size) 562 { 563 u32 size_aligned_height = ALIGN((frame_height), lcu_size); 564 u32 size_aligned_width = ALIGN((frame_width), lcu_size); 565 u32 size_single_pipe_eval = 0, sao_bin_buffer_size = 0; 566 u32 padded_bin_sz; 567 568 if ((size_aligned_width * size_aligned_height) > (3840 * 2160)) 569 size_single_pipe_eval = (bitbin_size / num_vpp_pipes); 570 else if (num_vpp_pipes > 2) 571 size_single_pipe_eval = bitbin_size / 2; 572 else 573 size_single_pipe_eval = bitbin_size; 574 575 sao_bin_buffer_size = (64 * ((((frame_width) + 32) * ((frame_height) + 32)) >> 10)) + 384; 576 padded_bin_sz = ALIGN(size_single_pipe_eval, 256); 577 size_single_pipe_eval = sao_bin_buffer_size + padded_bin_sz; 578 579 return ALIGN(size_single_pipe_eval, 256); 580 } 581 582 static inline u32 size_bin_bitstream_enc(u32 width, u32 height, 583 u32 rc_type) 584 { 585 u32 aligned_height = ALIGN(height, 32); 586 u32 aligned_width = ALIGN(width, 32); 587 u32 frame_size = width * height * 3; 588 u32 mbs_per_frame; 589 590 /* 591 * Encoder output size calculation: 32 Align width/height 592 * For resolution < 720p : YUVsize * 4 593 * For resolution > 720p & <= 4K : YUVsize / 2 594 * For resolution > 4k : YUVsize / 4 595 * Initially frame_size = YUVsize * 2; 596 */ 597 598 mbs_per_frame = (ALIGN(aligned_height, 16) * ALIGN(aligned_width, 16)) / 256; 599 600 if (mbs_per_frame < NUM_MBS_720P) 601 frame_size = frame_size << 1; 602 else if (mbs_per_frame <= NUM_MBS_4K) 603 frame_size = frame_size >> 2; 604 else 605 frame_size = frame_size >> 3; 606 607 if (rc_type == HFI_RATE_CONTROL_OFF || rc_type == HFI_RATE_CONTROL_CQ || 608 rc_type == HFI_RC_OFF || rc_type == HFI_RC_CQ) 609 frame_size = frame_size << 1; 610 611 /* 612 * In case of opaque color format bitdepth will be known 613 * with first ETB, buffers allocated already with 8 bit 614 * won't be sufficient for 10 bit 615 * calculate size considering 10-bit by default 616 * For 10-bit cases size = size * 1.25 617 */ 618 frame_size *= 5; 619 frame_size /= 4; 620 621 return ALIGN(frame_size, SZ_4K); 622 } 623 624 static inline u32 hfi_buffer_bin_enc(u32 width, u32 height, 625 u32 work_mode, u32 lcu_size, 626 u32 num_vpp_pipes, u32 rc_type) 627 { 628 u32 sao_bin_buffer_size, padded_bin_size, bitstream_size; 629 u32 total_bitbin_buffers, size_single_pipe, bitbin_size; 630 u32 aligned_height = ALIGN(height, lcu_size); 631 u32 aligned_width = ALIGN(width, lcu_size); 632 633 bitstream_size = size_bin_bitstream_enc(width, height, rc_type); 634 bitstream_size = ALIGN(bitstream_size, 256); 635 636 if (work_mode == STAGE_2) { 637 total_bitbin_buffers = 3; 638 bitbin_size = bitstream_size * 17 / 10; 639 bitbin_size = ALIGN(bitbin_size, 256); 640 } else { 641 total_bitbin_buffers = 1; 642 bitstream_size = aligned_width * aligned_height * 3; 643 bitbin_size = ALIGN(bitstream_size, 256); 644 } 645 646 if (num_vpp_pipes > 2) 647 size_single_pipe = bitbin_size / 2; 648 else 649 size_single_pipe = bitbin_size; 650 651 size_single_pipe = ALIGN(size_single_pipe, 256); 652 sao_bin_buffer_size = (64 * (((width + 32) * (height + 32)) >> 10)) + 384; 653 padded_bin_size = ALIGN(size_single_pipe, 256); 654 size_single_pipe = sao_bin_buffer_size + padded_bin_size; 655 size_single_pipe = ALIGN(size_single_pipe, 256); 656 bitbin_size = size_single_pipe * num_vpp_pipes; 657 658 return ALIGN(bitbin_size, 256) * total_bitbin_buffers + 512; 659 } 660 661 static u32 iris_vpu_enc_bin_size(struct iris_inst *inst) 662 { 663 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 664 u32 stage = inst->fw_caps[STAGE].value; 665 struct v4l2_format *f = inst->fmt_dst; 666 u32 height = f->fmt.pix_mp.height; 667 u32 width = f->fmt.pix_mp.width; 668 u32 lcu_size; 669 670 if (inst->codec == V4L2_PIX_FMT_HEVC) 671 lcu_size = 32; 672 else 673 lcu_size = 16; 674 675 return hfi_buffer_bin_enc(width, height, stage, lcu_size, 676 num_vpp_pipes, inst->hfi_rc_type); 677 } 678 679 static inline 680 u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_height, u32 lcu_size, 681 u32 num_recon, u32 standard) 682 { 683 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 684 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 685 u32 num_lcu_in_frame = width_in_lcus * height_in_lcus; 686 u32 mb_height = ((frame_height) + 15) >> 4; 687 u32 mb_width = ((frame_width) + 15) >> 4; 688 u32 size_colloc_mv, size_colloc_rc; 689 690 size_colloc_mv = (standard == HFI_CODEC_ENCODE_HEVC) ? 691 (16 * ((num_lcu_in_frame << 2) + 32)) : 692 (3 * 16 * (width_in_lcus * height_in_lcus + 32)); 693 size_colloc_mv = ALIGN(size_colloc_mv, 256) * num_recon; 694 size_colloc_rc = (((mb_width + 7) >> 3) * 16 * 2 * mb_height); 695 size_colloc_rc = ALIGN(size_colloc_rc, 256) * HFI_MAX_COL_FRAME; 696 697 return size_colloc_mv + size_colloc_rc; 698 } 699 700 static u32 iris_vpu_enc_comv_size(struct iris_inst *inst) 701 { 702 struct v4l2_format *f = inst->fmt_dst; 703 u32 height = f->fmt.pix_mp.height; 704 u32 width = f->fmt.pix_mp.width; 705 u32 num_recon = 1; 706 u32 lcu_size = 16; 707 708 if (inst->codec == V4L2_PIX_FMT_HEVC) { 709 lcu_size = 32; 710 return hfi_buffer_comv_enc(width, height, lcu_size, 711 num_recon + 1, HFI_CODEC_ENCODE_HEVC); 712 } 713 714 return hfi_buffer_comv_enc(width, height, lcu_size, 715 num_recon + 1, HFI_CODEC_ENCODE_AVC); 716 } 717 718 static inline 719 u32 size_frame_rc_buf_size(u32 standard, u32 frame_height_coded, 720 u32 num_vpp_pipes_enc) 721 { 722 u32 size = 0; 723 724 size = (standard == HFI_CODEC_ENCODE_HEVC) ? 725 (256 + 16 * (14 + ((((frame_height_coded) >> 5) + 7) >> 3))) : 726 (256 + 16 * (14 + ((((frame_height_coded) >> 4) + 7) >> 3))); 727 size *= 11; 728 729 if (num_vpp_pipes_enc > 1) 730 size = ALIGN(size, 256) * num_vpp_pipes_enc; 731 732 return ALIGN(size, 512) * HFI_MAX_COL_FRAME; 733 } 734 735 static inline 736 u32 size_enc_slice_info_buf(u32 num_lcu_in_frame) 737 { 738 return ALIGN((256 + (num_lcu_in_frame << 4)), 256); 739 } 740 741 static inline u32 enc_bitcnt_buf_size(u32 num_lcu_in_frame) 742 { 743 return ALIGN((256 + (4 * (num_lcu_in_frame))), 256); 744 } 745 746 static inline u32 enc_bitmap_buf_size(u32 num_lcu_in_frame) 747 { 748 return ALIGN((256 + ((num_lcu_in_frame) >> 3)), 256); 749 } 750 751 static inline u32 size_override_buf(u32 num_lcumb) 752 { 753 return ALIGN(((16 * (((num_lcumb) + 7) >> 3))), 256) * 2; 754 } 755 756 static inline u32 size_ir_buf(u32 num_lcu_in_frame) 757 { 758 return ALIGN((((((num_lcu_in_frame) << 1) + 7) & (~7)) * 3), 256); 759 } 760 761 static inline 762 u32 size_linebuff_data(bool is_ten_bit, u32 frame_width_coded) 763 { 764 return is_ten_bit ? 765 (((((10 * (frame_width_coded) + 1024) + (256 - 1)) & 766 (~(256 - 1))) * 1) + 767 (((((10 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & 768 (~(256 - 1))) * 2)) : 769 (((((8 * (frame_width_coded) + 1024) + (256 - 1)) & 770 (~(256 - 1))) * 1) + 771 (((((8 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & 772 (~(256 - 1))) * 2)); 773 } 774 775 static inline 776 u32 size_left_linebuff_ctrl(u32 standard, u32 frame_height_coded, 777 u32 num_vpp_pipes_enc) 778 { 779 u32 size = 0; 780 781 size = standard == HFI_CODEC_ENCODE_HEVC ? 782 (((frame_height_coded) + 783 (32)) / 32 * 4 * 16) : 784 (((frame_height_coded) + 15) / 16 * 5 * 16); 785 786 if ((num_vpp_pipes_enc) > 1) { 787 size += 512; 788 size = ALIGN(size, 512) * 789 num_vpp_pipes_enc; 790 } 791 792 return ALIGN(size, 256); 793 } 794 795 static inline 796 u32 size_left_linebuff_recon_pix(bool is_ten_bit, u32 frame_height_coded, 797 u32 num_vpp_pipes_enc) 798 { 799 return (((is_ten_bit + 1) * 2 * (frame_height_coded) + 256) + 800 (256 << (num_vpp_pipes_enc - 1)) - 1) & 801 (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1; 802 } 803 804 static inline 805 u32 size_top_linebuff_ctrl_fe(u32 frame_width_coded, u32 standard) 806 { 807 return standard == HFI_CODEC_ENCODE_HEVC ? 808 ALIGN((64 * ((frame_width_coded) >> 5)), 256) : 809 ALIGN((256 + 16 * ((frame_width_coded) >> 4)), 256); 810 } 811 812 static inline 813 u32 size_left_linebuff_ctrl_fe(u32 frame_height_coded, u32 num_vpp_pipes_enc) 814 { 815 return (((256 + 64 * ((frame_height_coded) >> 4)) + 816 (256 << (num_vpp_pipes_enc - 1)) - 1) & 817 (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1) * 818 num_vpp_pipes_enc; 819 } 820 821 static inline 822 u32 size_left_linebuff_metadata_recon_y(u32 frame_height_coded, 823 bool is_ten_bit, 824 u32 num_vpp_pipes_enc) 825 { 826 return ALIGN(((256 + 64 * ((frame_height_coded) / 827 (8 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; 828 } 829 830 static inline 831 u32 size_left_linebuff_metadata_recon_uv(u32 frame_height_coded, 832 bool is_ten_bit, 833 u32 num_vpp_pipes_enc) 834 { 835 return ALIGN(((256 + 64 * ((frame_height_coded) / 836 (4 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; 837 } 838 839 static inline 840 u32 size_linebuff_recon_pix(bool is_ten_bit, u32 frame_width_coded) 841 { 842 return ALIGN(((is_ten_bit ? 3 : 2) * (frame_width_coded)), 256); 843 } 844 845 static inline 846 u32 size_line_buf_ctrl(u32 frame_width_coded) 847 { 848 return ALIGN(frame_width_coded, 256); 849 } 850 851 static inline 852 u32 size_line_buf_ctrl_id2(u32 frame_width_coded) 853 { 854 return ALIGN(frame_width_coded, 256); 855 } 856 857 static inline u32 size_line_buf_sde(u32 frame_width_coded) 858 { 859 return ALIGN((256 + (16 * ((frame_width_coded) >> 4))), 256); 860 } 861 862 static inline 863 u32 size_vpss_line_buf(u32 num_vpp_pipes_enc, u32 frame_height_coded, 864 u32 frame_width_coded) 865 { 866 return ALIGN(((((((8192) >> 2) << 5) * (num_vpp_pipes_enc)) + 64) + 867 (((((max_t(u32, (frame_width_coded), 868 (frame_height_coded)) + 3) >> 2) << 5) + 256) * 16)), 256); 869 } 870 871 static inline 872 u32 size_top_line_buf_first_stg_sao(u32 frame_width_coded) 873 { 874 return ALIGN((16 * ((frame_width_coded) >> 5)), 256); 875 } 876 877 static inline 878 u32 size_enc_ref_buffer(u32 frame_width, u32 frame_height) 879 { 880 u32 u_chroma_buffer_height = ALIGN(frame_height >> 1, 32); 881 u32 u_buffer_height = ALIGN(frame_height, 32); 882 u32 u_buffer_width = ALIGN(frame_width, 32); 883 884 return (u_buffer_height + u_chroma_buffer_height) * u_buffer_width; 885 } 886 887 static inline 888 u32 size_enc_ten_bit_ref_buffer(u32 frame_width, u32 frame_height) 889 { 890 u32 ref_luma_stride_in_bytes = ((frame_width + SYSTEM_LAL_TILE10 - 1) / SYSTEM_LAL_TILE10) * 891 SYSTEM_LAL_TILE10; 892 u32 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1)); 893 u32 u_ref_stride, luma_size; 894 u32 ref_chrm_height_in_bytes; 895 u32 chroma_size; 896 897 u_ref_stride = 4 * (ref_luma_stride_in_bytes / 3); 898 u_ref_stride = (u_ref_stride + (128 - 1)) & (~(128 - 1)); 899 luma_size = ref_buf_height * u_ref_stride; 900 luma_size = (luma_size + (4096 - 1)) & (~(4096 - 1)); 901 902 ref_chrm_height_in_bytes = (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); 903 chroma_size = u_ref_stride * ref_chrm_height_in_bytes; 904 chroma_size = (chroma_size + (4096 - 1)) & (~(4096 - 1)); 905 906 return luma_size + chroma_size; 907 } 908 909 static inline 910 u32 hfi_ubwc_calc_metadata_plane_stride(u32 frame_width, 911 u32 metadata_stride_multiple, 912 u32 tile_width_in_pels) 913 { 914 return ALIGN(((frame_width + (tile_width_in_pels - 1)) / tile_width_in_pels), 915 metadata_stride_multiple); 916 } 917 918 static inline 919 u32 hfi_ubwc_metadata_plane_bufheight(u32 frame_height, 920 u32 metadata_height_multiple, 921 u32 tile_height_in_pels) 922 { 923 return ALIGN(((frame_height + (tile_height_in_pels - 1)) / tile_height_in_pels), 924 metadata_height_multiple); 925 } 926 927 static inline 928 u32 hfi_ubwc_metadata_plane_buffer_size(u32 _metadata_tride, u32 _metadata_buf_height) 929 { 930 return ALIGN(_metadata_tride * _metadata_buf_height, 4096); 931 } 932 933 static inline 934 u32 hfi_buffer_non_comv_enc(u32 frame_width, u32 frame_height, 935 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 936 { 937 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 938 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 939 u32 num_lcu_in_frame = width_in_lcus * height_in_lcus; 940 u32 frame_height_coded = height_in_lcus * (lcu_size); 941 u32 frame_width_coded = width_in_lcus * (lcu_size); 942 u32 num_lcumb, frame_rc_buf_size; 943 944 num_lcumb = (frame_height_coded / lcu_size) * 945 ((frame_width_coded + lcu_size * 8) / lcu_size); 946 frame_rc_buf_size = size_frame_rc_buf_size(standard, frame_height_coded, 947 num_vpp_pipes_enc); 948 return size_enc_slice_info_buf(num_lcu_in_frame) + 949 SIZE_SLICE_CMD_BUFFER + 950 SIZE_SPS_PPS_SLICE_HDR + 951 frame_rc_buf_size + 952 enc_bitcnt_buf_size(num_lcu_in_frame) + 953 enc_bitmap_buf_size(num_lcu_in_frame) + 954 SIZE_BSE_SLICE_CMD_BUF + 955 SIZE_LAMBDA_LUT + 956 size_override_buf(num_lcumb) + 957 size_ir_buf(num_lcu_in_frame); 958 } 959 960 static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst) 961 { 962 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 963 struct v4l2_format *f = inst->fmt_dst; 964 u32 height = f->fmt.pix_mp.height; 965 u32 width = f->fmt.pix_mp.width; 966 u32 lcu_size = 16; 967 968 if (inst->codec == V4L2_PIX_FMT_HEVC) { 969 lcu_size = 32; 970 return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, 971 lcu_size, HFI_CODEC_ENCODE_HEVC) + 972 SIZE_ONE_SLICE_BUF; 973 } 974 975 return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, 976 lcu_size, HFI_CODEC_ENCODE_AVC); 977 } 978 979 static inline 980 u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit, 981 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 982 { 983 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 984 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 985 u32 frame_height_coded = height_in_lcus * (lcu_size); 986 u32 frame_width_coded = width_in_lcus * (lcu_size); 987 u32 line_buff_data_size, left_line_buff_ctrl_size; 988 u32 left_line_buff_metadata_recon__uv__size; 989 u32 left_line_buff_metadata_recon__y__size; 990 u32 left_line_buff_recon_pix_size; 991 u32 top_line_buff_ctrl_fe_size; 992 u32 line_buff_recon_pix_size; 993 994 line_buff_data_size = size_linebuff_data(is_ten_bit, frame_width_coded); 995 left_line_buff_ctrl_size = 996 size_left_linebuff_ctrl(standard, frame_height_coded, num_vpp_pipes_enc); 997 left_line_buff_recon_pix_size = 998 size_left_linebuff_recon_pix(is_ten_bit, frame_height_coded, 999 num_vpp_pipes_enc); 1000 top_line_buff_ctrl_fe_size = 1001 size_top_linebuff_ctrl_fe(frame_width_coded, standard); 1002 left_line_buff_metadata_recon__y__size = 1003 size_left_linebuff_metadata_recon_y(frame_height_coded, is_ten_bit, 1004 num_vpp_pipes_enc); 1005 left_line_buff_metadata_recon__uv__size = 1006 size_left_linebuff_metadata_recon_uv(frame_height_coded, is_ten_bit, 1007 num_vpp_pipes_enc); 1008 line_buff_recon_pix_size = size_linebuff_recon_pix(is_ten_bit, frame_width_coded); 1009 1010 return size_line_buf_ctrl(frame_width_coded) + 1011 size_line_buf_ctrl_id2(frame_width_coded) + 1012 line_buff_data_size + 1013 left_line_buff_ctrl_size + 1014 left_line_buff_recon_pix_size + 1015 top_line_buff_ctrl_fe_size + 1016 left_line_buff_metadata_recon__y__size + 1017 left_line_buff_metadata_recon__uv__size + 1018 line_buff_recon_pix_size + 1019 size_left_linebuff_ctrl_fe(frame_height_coded, num_vpp_pipes_enc) + 1020 size_line_buf_sde(frame_width_coded) + 1021 size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_coded) + 1022 size_top_line_buf_first_stg_sao(frame_width_coded); 1023 } 1024 1025 static u32 iris_vpu_enc_line_size(struct iris_inst *inst) 1026 { 1027 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1028 struct v4l2_format *f = inst->fmt_dst; 1029 u32 height = f->fmt.pix_mp.height; 1030 u32 width = f->fmt.pix_mp.width; 1031 u32 lcu_size = 16; 1032 1033 if (inst->codec == V4L2_PIX_FMT_HEVC) { 1034 lcu_size = 32; 1035 return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, 1036 lcu_size, HFI_CODEC_ENCODE_HEVC); 1037 } 1038 1039 return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, 1040 lcu_size, HFI_CODEC_ENCODE_AVC); 1041 } 1042 1043 static inline 1044 u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit) 1045 { 1046 u32 metadata_stride, metadata_buf_height, meta_size_y, meta_size_c; 1047 u32 ten_bit_ref_buf_size = 0, ref_buf_size = 0; 1048 u32 size; 1049 1050 if (!is_ten_bit) { 1051 ref_buf_size = size_enc_ref_buffer(frame_width, frame_height); 1052 metadata_stride = 1053 hfi_ubwc_calc_metadata_plane_stride(frame_width, 64, 1054 HFI_COL_FMT_NV12C_Y_TILE_WIDTH); 1055 metadata_buf_height = 1056 hfi_ubwc_metadata_plane_bufheight(frame_height, 16, 1057 HFI_COL_FMT_NV12C_Y_TILE_HEIGHT); 1058 meta_size_y = 1059 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1060 meta_size_c = 1061 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1062 size = ref_buf_size + meta_size_y + meta_size_c; 1063 } else { 1064 ten_bit_ref_buf_size = size_enc_ten_bit_ref_buffer(frame_width, frame_height); 1065 metadata_stride = 1066 hfi_ubwc_calc_metadata_plane_stride(frame_width, 1067 IRIS_METADATA_STRIDE_MULTIPLE, 1068 HFI_COL_FMT_TP10C_Y_TILE_WIDTH); 1069 metadata_buf_height = 1070 hfi_ubwc_metadata_plane_bufheight(frame_height, 1071 IRIS_METADATA_HEIGHT_MULTIPLE, 1072 HFI_COL_FMT_TP10C_Y_TILE_HEIGHT); 1073 meta_size_y = 1074 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1075 meta_size_c = 1076 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1077 size = ten_bit_ref_buf_size + meta_size_y + meta_size_c; 1078 } 1079 1080 return size; 1081 } 1082 1083 static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) 1084 { 1085 return HFI_BUFFER_ARP_ENC; 1086 } 1087 1088 inline bool is_scaling_enabled(struct iris_inst *inst) 1089 { 1090 return inst->crop.left != inst->compose.left || 1091 inst->crop.top != inst->compose.top || 1092 inst->crop.width != inst->compose.width || 1093 inst->crop.height != inst->compose.height; 1094 } 1095 1096 static inline 1097 u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable, 1098 u32 blur, bool is_ten_bit) 1099 { 1100 if (ds_enable || blur) 1101 return hfi_buffer_dpb_enc(dswidth, dsheight, is_ten_bit); 1102 1103 return 0; 1104 } 1105 1106 static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_height, 1107 u32 lcu_size, u32 num_ref, 1108 bool ten_bit, u32 num_vpp_pipes, 1109 bool is_h265) 1110 { 1111 u32 line_buf_ctrl_size, line_buf_data_size, leftline_buf_ctrl_size; 1112 u32 line_buf_sde_size, sps_pps_slice_hdr, topline_buf_ctrl_size_FE; 1113 u32 leftline_buf_ctrl_size_FE, line_buf_recon_pix_size; 1114 u32 leftline_buf_recon_pix_size, lambda_lut_size, override_buffer_size; 1115 u32 col_mv_buf_size, vpp_reg_buffer_size, ir_buffer_size; 1116 u32 vpss_line_buf, leftline_buf_meta_recony, h265e_colrcbuf_size; 1117 u32 h265e_framerc_bufsize, h265e_lcubitcnt_bufsize; 1118 u32 h265e_lcubitmap_bufsize, se_stats_bufsize; 1119 u32 bse_reg_buffer_size, bse_slice_cmd_buffer_size, slice_info_bufsize; 1120 u32 line_buf_ctrl_size_buffid2, slice_cmd_buffer_size; 1121 u32 width_lcu_num, height_lcu_num, width_coded, height_coded; 1122 u32 frame_num_lcu, linebuf_meta_recon_uv, topline_bufsize_fe_1stg_sao; 1123 u32 vpss_line_buffer_size_1; 1124 u32 bit_depth, num_lcu_mb; 1125 1126 width_lcu_num = (frame_width + lcu_size - 1) / lcu_size; 1127 height_lcu_num = (frame_height + lcu_size - 1) / lcu_size; 1128 frame_num_lcu = width_lcu_num * height_lcu_num; 1129 width_coded = width_lcu_num * lcu_size; 1130 height_coded = height_lcu_num * lcu_size; 1131 num_lcu_mb = (height_coded / lcu_size) * 1132 ((width_coded + lcu_size * 8) / lcu_size); 1133 slice_info_bufsize = 256 + (frame_num_lcu << 4); 1134 slice_info_bufsize = ALIGN(slice_info_bufsize, 256); 1135 line_buf_ctrl_size = ALIGN(width_coded, 256); 1136 line_buf_ctrl_size_buffid2 = ALIGN(width_coded, 256); 1137 1138 bit_depth = ten_bit ? 10 : 8; 1139 line_buf_data_size = 1140 (((((bit_depth * width_coded + 1024) + (256 - 1)) & 1141 (~(256 - 1))) * 1) + 1142 (((((bit_depth * width_coded + 1024) >> 1) + (256 - 1)) & 1143 (~(256 - 1))) * 2)); 1144 1145 leftline_buf_ctrl_size = is_h265 ? ((height_coded + 32) / 32 * 4 * 16) : 1146 ((height_coded + 15) / 16 * 5 * 16); 1147 1148 if (num_vpp_pipes > 1) { 1149 leftline_buf_ctrl_size += 512; 1150 leftline_buf_ctrl_size = 1151 ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes; 1152 } 1153 1154 leftline_buf_ctrl_size = ALIGN(leftline_buf_ctrl_size, 256); 1155 leftline_buf_recon_pix_size = 1156 (((ten_bit + 1) * 2 * (height_coded) + 256) + 1157 (256 << (num_vpp_pipes - 1)) - 1) & 1158 (~((256 << (num_vpp_pipes - 1)) - 1)) * 1; 1159 1160 topline_buf_ctrl_size_FE = is_h265 ? (64 * (width_coded >> 5)) : 1161 (256 + 16 * (width_coded >> 4)); 1162 topline_buf_ctrl_size_FE = ALIGN(topline_buf_ctrl_size_FE, 256); 1163 leftline_buf_ctrl_size_FE = 1164 (((256 + 64 * (height_coded >> 4)) + 1165 (256 << (num_vpp_pipes - 1)) - 1) & 1166 (~((256 << (num_vpp_pipes - 1)) - 1)) * 1) * 1167 num_vpp_pipes; 1168 leftline_buf_meta_recony = 1169 (256 + 64 * ((height_coded) / (8 * (ten_bit ? 4 : 8)))); 1170 leftline_buf_meta_recony = ALIGN(leftline_buf_meta_recony, 256); 1171 leftline_buf_meta_recony = leftline_buf_meta_recony * num_vpp_pipes; 1172 linebuf_meta_recon_uv = 1173 (256 + 64 * ((height_coded) / (4 * (ten_bit ? 4 : 8)))); 1174 linebuf_meta_recon_uv = ALIGN(linebuf_meta_recon_uv, 256); 1175 linebuf_meta_recon_uv = linebuf_meta_recon_uv * num_vpp_pipes; 1176 line_buf_recon_pix_size = ((ten_bit ? 3 : 2) * width_coded); 1177 line_buf_recon_pix_size = ALIGN(line_buf_recon_pix_size, 256); 1178 slice_cmd_buffer_size = ALIGN(20480, 256); 1179 sps_pps_slice_hdr = 2048 + 4096; 1180 col_mv_buf_size = 1181 is_h265 ? (16 * ((frame_num_lcu << 2) + 32)) : 1182 (3 * 16 * (width_lcu_num * height_lcu_num + 32)); 1183 col_mv_buf_size = ALIGN(col_mv_buf_size, 256) * (num_ref + 1); 1184 h265e_colrcbuf_size = 1185 (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); 1186 if (num_vpp_pipes > 1) 1187 h265e_colrcbuf_size = 1188 ALIGN(h265e_colrcbuf_size, 256) * num_vpp_pipes; 1189 1190 h265e_colrcbuf_size = 1191 ALIGN(h265e_colrcbuf_size, 256) * HFI_MAX_COL_FRAME; 1192 h265e_framerc_bufsize = 1193 (is_h265) ? 1194 (256 + 16 * (14 + (((height_coded >> 5) + 7) >> 3))) : 1195 (256 + 16 * (14 + (((height_coded >> 4) + 7) >> 3))); 1196 h265e_framerc_bufsize *= 6; 1197 if (num_vpp_pipes > 1) 1198 h265e_framerc_bufsize = 1199 ALIGN(h265e_framerc_bufsize, 256) * num_vpp_pipes; 1200 1201 h265e_framerc_bufsize = 1202 ALIGN(h265e_framerc_bufsize, 512) * HFI_MAX_COL_FRAME; 1203 h265e_lcubitcnt_bufsize = 256 + 4 * frame_num_lcu; 1204 h265e_lcubitcnt_bufsize = ALIGN(h265e_lcubitcnt_bufsize, 256); 1205 h265e_lcubitmap_bufsize = 256 + (frame_num_lcu >> 3); 1206 h265e_lcubitmap_bufsize = ALIGN(h265e_lcubitmap_bufsize, 256); 1207 line_buf_sde_size = 256 + 16 * (width_coded >> 4); 1208 line_buf_sde_size = ALIGN(line_buf_sde_size, 256); 1209 if ((width_coded * height_coded) > (4096 * 2160)) 1210 se_stats_bufsize = 0; 1211 else if ((width_coded * height_coded) > (1920 * 1088)) 1212 se_stats_bufsize = (40 * 4 * frame_num_lcu + 256 + 256); 1213 else 1214 se_stats_bufsize = (1024 * frame_num_lcu + 256 + 256); 1215 1216 se_stats_bufsize = ALIGN(se_stats_bufsize, 256) * 2; 1217 bse_slice_cmd_buffer_size = (((8192 << 2) + 7) & (~7)) * 6; 1218 bse_reg_buffer_size = (((512 << 3) + 7) & (~7)) * 4; 1219 vpp_reg_buffer_size = (((2048 << 3) + 31) & (~31)) * 10; 1220 lambda_lut_size = 256 * 11; 1221 override_buffer_size = 16 * ((num_lcu_mb + 7) >> 3); 1222 override_buffer_size = ALIGN(override_buffer_size, 256) * 2; 1223 ir_buffer_size = (((frame_num_lcu << 1) + 7) & (~7)) * 3; 1224 vpss_line_buffer_size_1 = (((8192 >> 2) << 5) * num_vpp_pipes) + 64; 1225 vpss_line_buf = 1226 (((((max(width_coded, height_coded) + 3) >> 2) << 5) + 256) * 1227 16) + 1228 vpss_line_buffer_size_1; 1229 topline_bufsize_fe_1stg_sao = 16 * (width_coded >> 5); 1230 topline_bufsize_fe_1stg_sao = ALIGN(topline_bufsize_fe_1stg_sao, 256); 1231 1232 return line_buf_ctrl_size + line_buf_data_size + 1233 line_buf_ctrl_size_buffid2 + leftline_buf_ctrl_size + 1234 vpss_line_buf + col_mv_buf_size + topline_buf_ctrl_size_FE + 1235 leftline_buf_ctrl_size_FE + line_buf_recon_pix_size + 1236 leftline_buf_recon_pix_size + leftline_buf_meta_recony + 1237 linebuf_meta_recon_uv + h265e_colrcbuf_size + 1238 h265e_framerc_bufsize + h265e_lcubitcnt_bufsize + 1239 h265e_lcubitmap_bufsize + line_buf_sde_size + 1240 topline_bufsize_fe_1stg_sao + override_buffer_size + 1241 bse_reg_buffer_size + vpp_reg_buffer_size + sps_pps_slice_hdr + 1242 slice_cmd_buffer_size + bse_slice_cmd_buffer_size + 1243 ir_buffer_size + slice_info_bufsize + lambda_lut_size + 1244 se_stats_bufsize + 1024; 1245 } 1246 1247 static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst) 1248 { 1249 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1250 struct v4l2_format *f = inst->fmt_dst; 1251 u32 frame_height = f->fmt.pix_mp.height; 1252 u32 frame_width = f->fmt.pix_mp.width; 1253 u32 num_ref = 1; 1254 u32 lcu_size; 1255 bool is_h265; 1256 1257 if (inst->codec == V4L2_PIX_FMT_H264) { 1258 lcu_size = 16; 1259 is_h265 = false; 1260 } else if (inst->codec == V4L2_PIX_FMT_HEVC) { 1261 lcu_size = 32; 1262 is_h265 = true; 1263 } else { 1264 return 0; 1265 } 1266 1267 return hfi_buffer_scratch1_enc(frame_width, frame_height, lcu_size, 1268 num_ref, false, num_vpp_pipes, is_h265); 1269 } 1270 1271 static inline u32 ubwc_metadata_plane_stride(u32 width, 1272 u32 metadata_stride_multi, 1273 u32 tile_width_pels) 1274 { 1275 return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels), 1276 metadata_stride_multi); 1277 } 1278 1279 static inline u32 ubwc_metadata_plane_bufheight(u32 height, 1280 u32 metadata_height_multi, 1281 u32 tile_height_pels) 1282 { 1283 return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels), 1284 metadata_height_multi); 1285 } 1286 1287 static inline u32 ubwc_metadata_plane_buffer_size(u32 metadata_stride, 1288 u32 metadata_buf_height) 1289 { 1290 return ALIGN(metadata_stride * metadata_buf_height, SZ_4K); 1291 } 1292 1293 static inline u32 hfi_buffer_scratch2_enc(u32 frame_width, u32 frame_height, 1294 u32 num_ref, bool ten_bit) 1295 { 1296 u32 aligned_width, aligned_height, chroma_height, ref_buf_height; 1297 u32 metadata_stride, meta_buf_height, meta_size_y, meta_size_c; 1298 u32 ref_luma_stride_bytes, ref_chroma_height_bytes; 1299 u32 ref_buf_size, ref_stride; 1300 u32 luma_size, chroma_size; 1301 u32 size; 1302 1303 if (!ten_bit) { 1304 aligned_height = ALIGN(frame_height, 32); 1305 chroma_height = frame_height >> 1; 1306 chroma_height = ALIGN(chroma_height, 32); 1307 aligned_width = ALIGN(frame_width, 128); 1308 metadata_stride = 1309 ubwc_metadata_plane_stride(frame_width, 64, 32); 1310 meta_buf_height = 1311 ubwc_metadata_plane_bufheight(frame_height, 16, 8); 1312 meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, 1313 meta_buf_height); 1314 meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, 1315 meta_buf_height); 1316 size = (aligned_height + chroma_height) * aligned_width + 1317 meta_size_y + meta_size_c; 1318 size = (size * (num_ref + 3)) + 4096; 1319 } else { 1320 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1)); 1321 ref_luma_stride_bytes = ((frame_width + 192 - 1) / 192) * 192; 1322 ref_stride = 4 * (ref_luma_stride_bytes / 3); 1323 ref_stride = (ref_stride + (128 - 1)) & (~(128 - 1)); 1324 luma_size = ref_buf_height * ref_stride; 1325 ref_chroma_height_bytes = 1326 (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); 1327 chroma_size = ref_stride * ref_chroma_height_bytes; 1328 luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); 1329 chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); 1330 ref_buf_size = luma_size + chroma_size; 1331 metadata_stride = 1332 ubwc_metadata_plane_stride(frame_width, 64, 48); 1333 meta_buf_height = 1334 ubwc_metadata_plane_bufheight(frame_height, 16, 4); 1335 meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, 1336 meta_buf_height); 1337 meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, 1338 meta_buf_height); 1339 size = ref_buf_size + meta_size_y + meta_size_c; 1340 size = (size * (num_ref + 3)) + 4096; 1341 } 1342 1343 return size; 1344 } 1345 1346 static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst) 1347 { 1348 struct v4l2_format *f = inst->fmt_dst; 1349 u32 frame_width = f->fmt.pix_mp.width; 1350 u32 frame_height = f->fmt.pix_mp.height; 1351 u32 num_ref = 1; 1352 1353 return hfi_buffer_scratch2_enc(frame_width, frame_height, num_ref, 1354 false); 1355 } 1356 1357 static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst) 1358 { 1359 u32 ds_enable = is_scaling_enabled(inst); 1360 struct v4l2_format *f = inst->fmt_dst; 1361 u32 height = f->fmt.pix_mp.height; 1362 u32 width = f->fmt.pix_mp.width; 1363 1364 return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); 1365 } 1366 1367 static int output_min_count(struct iris_inst *inst) 1368 { 1369 int output_min_count = 4; 1370 1371 /* fw_min_count > 0 indicates reconfig event has already arrived */ 1372 if (inst->fw_min_count) { 1373 if (iris_split_mode_enabled(inst) && inst->codec == V4L2_PIX_FMT_VP9) 1374 return min_t(u32, 4, inst->fw_min_count); 1375 else 1376 return inst->fw_min_count; 1377 } 1378 1379 if (inst->codec == V4L2_PIX_FMT_VP9) 1380 output_min_count = 9; 1381 1382 return output_min_count; 1383 } 1384 1385 struct iris_vpu_buf_type_handle { 1386 enum iris_buffer_type type; 1387 u32 (*handle)(struct iris_inst *inst); 1388 }; 1389 1390 int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) 1391 { 1392 const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL; 1393 u32 size = 0, buf_type_handle_size = 0, i; 1394 1395 static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = { 1396 {BUF_BIN, iris_vpu_dec_bin_size }, 1397 {BUF_COMV, iris_vpu_dec_comv_size }, 1398 {BUF_NON_COMV, iris_vpu_dec_non_comv_size }, 1399 {BUF_LINE, iris_vpu_dec_line_size }, 1400 {BUF_PERSIST, iris_vpu_dec_persist_size }, 1401 {BUF_DPB, iris_vpu_dec_dpb_size }, 1402 {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, 1403 }; 1404 1405 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = { 1406 {BUF_BIN, iris_vpu_enc_bin_size }, 1407 {BUF_COMV, iris_vpu_enc_comv_size }, 1408 {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, 1409 {BUF_LINE, iris_vpu_enc_line_size }, 1410 {BUF_ARP, iris_vpu_enc_arp_size }, 1411 {BUF_VPSS, iris_vpu_enc_vpss_size }, 1412 {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, 1413 {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, 1414 }; 1415 1416 if (inst->domain == DECODER) { 1417 buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle); 1418 buf_type_handle_arr = dec_internal_buf_type_handle; 1419 } else if (inst->domain == ENCODER) { 1420 buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle); 1421 buf_type_handle_arr = enc_internal_buf_type_handle; 1422 } 1423 1424 for (i = 0; i < buf_type_handle_size; i++) { 1425 if (buf_type_handle_arr[i].type == buffer_type) { 1426 size = buf_type_handle_arr[i].handle(inst); 1427 break; 1428 } 1429 } 1430 1431 return size; 1432 } 1433 1434 static u32 internal_buffer_count(struct iris_inst *inst, 1435 enum iris_buffer_type buffer_type) 1436 { 1437 if (buffer_type == BUF_BIN || buffer_type == BUF_LINE || 1438 buffer_type == BUF_PERSIST) { 1439 return 1; 1440 } else if (buffer_type == BUF_COMV || buffer_type == BUF_NON_COMV) { 1441 if (inst->codec == V4L2_PIX_FMT_H264 || inst->codec == V4L2_PIX_FMT_HEVC) 1442 return 1; 1443 } 1444 return 0; 1445 } 1446 1447 static inline int iris_vpu_dpb_count(struct iris_inst *inst) 1448 { 1449 if (iris_split_mode_enabled(inst)) { 1450 return inst->fw_min_count ? 1451 inst->fw_min_count : inst->buffers[BUF_OUTPUT].min_count; 1452 } 1453 1454 return 0; 1455 } 1456 1457 int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) 1458 { 1459 switch (buffer_type) { 1460 case BUF_INPUT: 1461 return MIN_BUFFERS; 1462 case BUF_OUTPUT: 1463 if (inst->domain == ENCODER) 1464 return MIN_BUFFERS; 1465 else 1466 return output_min_count(inst); 1467 case BUF_BIN: 1468 case BUF_COMV: 1469 case BUF_NON_COMV: 1470 case BUF_LINE: 1471 case BUF_PERSIST: 1472 return internal_buffer_count(inst, buffer_type); 1473 case BUF_SCRATCH_1: 1474 case BUF_SCRATCH_2: 1475 case BUF_VPSS: 1476 case BUF_ARP: 1477 return 1; /* internal buffer count needed by firmware is 1 */ 1478 case BUF_DPB: 1479 return iris_vpu_dpb_count(inst); 1480 default: 1481 return 0; 1482 } 1483 } 1484