1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include "iris_instance.h" 7 #include "iris_vpu_buffer.h" 8 #include "iris_hfi_gen1_defines.h" 9 #include "iris_hfi_gen2_defines.h" 10 11 #define HFI_MAX_COL_FRAME 6 12 13 #ifndef SYSTEM_LAL_TILE10 14 #define SYSTEM_LAL_TILE10 192 15 #endif 16 17 static u32 size_h264d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 18 { 19 u32 size_yuv, size_bin_hdr, size_bin_res; 20 21 size_yuv = ((frame_width * frame_height) <= BIN_BUFFER_THRESHOLD) ? 22 ((BIN_BUFFER_THRESHOLD * 3) >> 1) : 23 ((frame_width * frame_height * 3) >> 1); 24 size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT; 25 size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT; 26 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes, 27 DMA_ALIGNMENT) * num_vpp_pipes; 28 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes, 29 DMA_ALIGNMENT) * num_vpp_pipes; 30 31 return size_bin_hdr + size_bin_res; 32 } 33 34 static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 35 { 36 u32 n_aligned_h = ALIGN(frame_height, 16); 37 u32 n_aligned_w = ALIGN(frame_width, 16); 38 39 return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); 40 } 41 42 static u32 size_h265d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 43 { 44 u32 product = frame_width * frame_height; 45 u32 size_yuv, size_bin_hdr, size_bin_res; 46 47 size_yuv = (product <= BIN_BUFFER_THRESHOLD) ? 48 ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); 49 size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT; 50 size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT; 51 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes, DMA_ALIGNMENT) * num_vpp_pipes; 52 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes, DMA_ALIGNMENT) * num_vpp_pipes; 53 54 return size_bin_hdr + size_bin_res; 55 } 56 57 static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 58 { 59 u32 _size_yuv = ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2; 60 u32 _size = ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) * 61 VPX_DECODER_FRAME_BIN_HDR_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR * 62 VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT) + 63 ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) * 64 VPX_DECODER_FRAME_BIN_RES_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR * 65 VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT); 66 67 return _size * num_vpp_pipes; 68 } 69 70 static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 71 { 72 u32 n_aligned_w = ALIGN(frame_width, 16); 73 u32 n_aligned_h = ALIGN(frame_height, 16); 74 75 return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); 76 } 77 78 static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _comv_bufcount) 79 { 80 u32 frame_height_in_mbs = DIV_ROUND_UP(frame_height, 16); 81 u32 frame_width_in_mbs = DIV_ROUND_UP(frame_width, 16); 82 u32 col_zero_aligned_width = (frame_width_in_mbs << 2); 83 u32 col_mv_aligned_width = (frame_width_in_mbs << 7); 84 u32 col_zero_size, size_colloc; 85 86 col_mv_aligned_width = ALIGN(col_mv_aligned_width, 16); 87 col_zero_aligned_width = ALIGN(col_zero_aligned_width, 16); 88 col_zero_size = col_zero_aligned_width * 89 ((frame_height_in_mbs + 1) >> 1); 90 col_zero_size = ALIGN(col_zero_size, 64); 91 col_zero_size <<= 1; 92 col_zero_size = ALIGN(col_zero_size, 512); 93 size_colloc = col_mv_aligned_width * ((frame_height_in_mbs + 1) >> 1); 94 size_colloc = ALIGN(size_colloc, 64); 95 size_colloc <<= 1; 96 size_colloc = ALIGN(size_colloc, 512); 97 size_colloc += (col_zero_size + SIZE_H264D_BUFTAB_T * 2); 98 99 return (size_colloc * (_comv_bufcount)) + 512; 100 } 101 102 static u32 hfi_buffer_comv_h265d(u32 frame_width, u32 frame_height, u32 _comv_bufcount) 103 { 104 u32 frame_height_in_mbs = (frame_height + 15) >> 4; 105 u32 frame_width_in_mbs = (frame_width + 15) >> 4; 106 u32 _size; 107 108 _size = ALIGN(((frame_width_in_mbs * frame_height_in_mbs) << 8), 512); 109 110 return (_size * (_comv_bufcount)) + 512; 111 } 112 113 static u32 size_h264d_bse_cmd_buf(u32 frame_height) 114 { 115 u32 height = ALIGN(frame_height, 32); 116 117 return min_t(u32, (DIV_ROUND_UP(height, 16) * 48), H264D_MAX_SLICE) * 118 SIZE_H264D_BSE_CMD_PER_BUF; 119 } 120 121 static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height) 122 { 123 u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * 124 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * 125 NUM_HW_PIC_BUF, DMA_ALIGNMENT); 126 _size = min_t(u32, _size, H265D_MAX_SLICE + 1); 127 _size = 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF; 128 129 return _size; 130 } 131 132 static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) 133 { 134 return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + 135 H265_NUM_FRM_INFO * H265_DISPLAY_BUF_SIZE + 136 H265_NUM_TILE * sizeof(u32) + 137 NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + 138 rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), 139 DMA_ALIGNMENT); 140 } 141 142 static inline 143 u32 hfi_iris3_vp9d_comv_size(void) 144 { 145 return (((8192 + 63) >> 6) * ((4320 + 63) >> 6) * 8 * 8 * 2 * 8); 146 } 147 148 static u32 hfi_buffer_persist_vp9d(void) 149 { 150 return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) + 151 ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) + 152 ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) + 153 ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) + 154 ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) + 155 ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, DMA_ALIGNMENT) + 156 HDR10_HIST_EXTRADATA_SIZE; 157 } 158 159 static u32 size_h264d_vpp_cmd_buf(u32 frame_height) 160 { 161 u32 size, height = ALIGN(frame_height, 32); 162 163 size = min_t(u32, (DIV_ROUND_UP(height, 16) * 48), H264D_MAX_SLICE) * 164 SIZE_H264D_VPP_CMD_PER_BUF; 165 166 return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size; 167 } 168 169 static u32 hfi_buffer_persist_h264d(void) 170 { 171 return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + 172 H264_DISPLAY_BUF_SIZE * H264_NUM_FRM_INFO + 173 NUM_HW_PIC_BUF * SIZE_SEI_USERDATA, 174 DMA_ALIGNMENT); 175 } 176 177 static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 178 { 179 u32 size_bse = size_h264d_bse_cmd_buf(frame_height); 180 u32 size_vpp = size_h264d_vpp_cmd_buf(frame_height); 181 u32 size = ALIGN(size_bse, DMA_ALIGNMENT) + 182 ALIGN(size_vpp, DMA_ALIGNMENT) + 183 ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT); 184 185 return ALIGN(size, DMA_ALIGNMENT); 186 } 187 188 static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height) 189 { 190 u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * 191 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * 192 NUM_HW_PIC_BUF, DMA_ALIGNMENT); 193 _size = min_t(u32, _size, H265D_MAX_SLICE + 1); 194 _size = ALIGN(_size, 4); 195 _size = 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF; 196 if (_size > VPP_CMD_MAX_SIZE) 197 _size = VPP_CMD_MAX_SIZE; 198 199 return _size; 200 } 201 202 static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 203 { 204 u32 _size_bse = size_h265d_bse_cmd_buf(frame_width, frame_height); 205 u32 _size_vpp = size_h265d_vpp_cmd_buf(frame_width, frame_height); 206 u32 _size = ALIGN(_size_bse, DMA_ALIGNMENT) + 207 ALIGN(_size_vpp, DMA_ALIGNMENT) + 208 ALIGN(NUM_HW_PIC_BUF * 20 * 22 * 4, DMA_ALIGNMENT) + 209 ALIGN(2 * sizeof(u16) * 210 (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * 211 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNMENT) + 212 ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT) + 213 HDR10_HIST_EXTRADATA_SIZE; 214 215 return ALIGN(_size, DMA_ALIGNMENT); 216 } 217 218 static u32 size_vpss_lb(u32 frame_width, u32 frame_height) 219 { 220 u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size; 221 u32 opb_wr_top_line_chroma_buffer_size; 222 u32 opb_wr_top_line_luma_buffer_size; 223 u32 macrotiling_size = 32; 224 225 opb_wr_top_line_luma_buffer_size = 226 ALIGN(frame_width, macrotiling_size) / macrotiling_size * 256; 227 opb_wr_top_line_luma_buffer_size = 228 ALIGN(opb_wr_top_line_luma_buffer_size, DMA_ALIGNMENT) + 229 (MAX_TILE_COLUMNS - 1) * 256; 230 opb_wr_top_line_luma_buffer_size = 231 max_t(u32, opb_wr_top_line_luma_buffer_size, (32 * ALIGN(frame_height, 8))); 232 opb_wr_top_line_chroma_buffer_size = opb_wr_top_line_luma_buffer_size; 233 opb_lb_wr_llb_uv_buffer_size = 234 ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 32); 235 opb_lb_wr_llb_y_buffer_size = 236 ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 32); 237 return opb_wr_top_line_luma_buffer_size + 238 opb_wr_top_line_chroma_buffer_size + 239 opb_lb_wr_llb_uv_buffer_size + 240 opb_lb_wr_llb_y_buffer_size; 241 } 242 243 static inline 244 u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 frame_height) 245 { 246 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * 247 (ALIGN(frame_width, 64) + 8) * 2; 248 } 249 250 static inline 251 u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) 252 { 253 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * 254 (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS); 255 } 256 257 static inline 258 u32 size_h265d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) 259 { 260 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * 261 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS); 262 } 263 264 static inline 265 u32 size_h265d_lb_se_top_ctrl(u32 frame_width, u32 frame_height) 266 { 267 return (LCU_MAX_SIZE_PELS / 8 * (128 / 8)) * ((frame_width + 15) >> 4); 268 } 269 270 static inline 271 u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 frame_height) 272 { 273 return max_t(u32, ((frame_height + 16 - 1) / 8) * 274 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 275 max_t(u32, ((frame_height + 32 - 1) / 8) * 276 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 277 ((frame_height + 64 - 1) / 8) * 278 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); 279 } 280 281 static inline 282 u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height) 283 { 284 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * 285 (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); 286 } 287 288 static inline 289 u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height) 290 { 291 return ((frame_width + 63) >> 6) * 128; 292 } 293 294 static inline 295 u32 size_h265d_lb_vsp_left(u32 frame_width, u32 frame_height) 296 { 297 return ((frame_height + 63) >> 6) * 128; 298 } 299 300 static inline 301 u32 size_h265d_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) 302 { 303 return size_h264d_lb_recon_dma_metadata_wr(frame_height); 304 } 305 306 static inline 307 u32 size_h265d_qp(u32 frame_width, u32 frame_height) 308 { 309 return size_h264d_qp(frame_width, frame_height); 310 } 311 312 static inline 313 u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes) 314 { 315 u32 vpss_lb_size = 0, _size; 316 317 _size = ALIGN(size_h265d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 318 ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 319 ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height), 320 DMA_ALIGNMENT) * num_vpp_pipes + 321 ALIGN(size_h265d_lb_se_left_ctrl(frame_width, frame_height), 322 DMA_ALIGNMENT) * num_vpp_pipes + 323 ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 324 ALIGN(size_h265d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 325 ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + 326 ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height), 327 DMA_ALIGNMENT) * num_vpp_pipes + 328 ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height), 329 DMA_ALIGNMENT) * 4 + 330 ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT); 331 if (is_opb) 332 vpss_lb_size = size_vpss_lb(frame_width, frame_height); 333 334 return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT); 335 } 336 337 static inline 338 u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) 339 { 340 return max_t(u32, ((frame_height + 15) >> 4) * 341 MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 342 max_t(u32, ((frame_height + 31) >> 5) * 343 MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 344 ((frame_height + 63) >> 6) * 345 MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); 346 } 347 348 static inline 349 u32 size_vpxd_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) 350 { 351 return ((ALIGN(frame_width, 64) + 8) * 10 * 2); 352 } 353 354 static inline 355 u32 size_vpxd_lb_se_top_ctrl(u32 frame_width, u32 frame_height) 356 { 357 return ((frame_width + 15) >> 4) * MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE; 358 } 359 360 static inline 361 u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 frame_height) 362 { 363 return max_t(u32, ((frame_height + 15) >> 4) * 364 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, 365 max_t(u32, ((frame_height + 31) >> 5) * 366 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, 367 ((frame_height + 63) >> 6) * 368 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); 369 } 370 371 static inline 372 u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) 373 { 374 return ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 375 BUFFER_ALIGNMENT_32_BYTES); 376 } 377 378 static inline __maybe_unused 379 u32 size_mp2d_lb_fe_top_data(u32 frame_width, u32 frame_height) 380 { 381 return ((ALIGN(frame_width, 16) + 8) * 10 * 2); 382 } 383 384 static inline 385 u32 size_vp9d_lb_fe_top_data(u32 frame_width, u32 frame_height) 386 { 387 return (ALIGN(ALIGN(frame_width, 8), 64) + 8) * 10 * 2; 388 } 389 390 static inline 391 u32 size_vp9d_lb_pe_top_data(u32 frame_width, u32 frame_height) 392 { 393 return ((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 176); 394 } 395 396 static inline 397 u32 size_vp9d_lb_vsp_top(u32 frame_width, u32 frame_height) 398 { 399 return (((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 64 * 8) + 256); 400 } 401 402 static inline 403 u32 size_vp9d_qp(u32 frame_width, u32 frame_height) 404 { 405 return size_h264d_qp(frame_width, frame_height); 406 } 407 408 static inline 409 u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes) 410 { 411 return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) * 412 num_vpp_pipes + 413 ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) * 414 num_vpp_pipes + 415 ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + 416 ALIGN(size_vpxd_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 417 2 * ALIGN(size_vpxd_lb_recon_dma_metadata_wr(frame_width, frame_height), 418 DMA_ALIGNMENT) + 419 ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) + 420 ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 421 ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT) + 422 ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); 423 } 424 425 static inline 426 u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min, bool is_opb, 427 u32 num_vpp_pipes) 428 { 429 u32 vpss_lb_size = 0; 430 u32 _lb_size; 431 432 _lb_size = hfi_iris3_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes); 433 434 if (is_opb) 435 vpss_lb_size = size_vpss_lb(frame_width, frame_height); 436 437 return _lb_size + vpss_lb_size + 4096; 438 } 439 440 static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height, 441 bool is_opb, u32 num_vpp_pipes) 442 { 443 u32 vpss_lb_size = 0; 444 u32 size; 445 446 size = ALIGN(size_h264d_lb_fe_top_data(frame_width), DMA_ALIGNMENT) + 447 ALIGN(size_h264d_lb_fe_top_ctrl(frame_width), DMA_ALIGNMENT) + 448 ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes + 449 ALIGN(size_h264d_lb_se_top_ctrl(frame_width), DMA_ALIGNMENT) + 450 ALIGN(size_h264d_lb_se_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes + 451 ALIGN(size_h264d_lb_pe_top_data(frame_width), DMA_ALIGNMENT) + 452 ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) + 453 ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) * 2 + 454 ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT); 455 size = ALIGN(size, DMA_ALIGNMENT); 456 if (is_opb) 457 vpss_lb_size = size_vpss_lb(frame_width, frame_height); 458 459 return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT); 460 } 461 462 static u32 iris_vpu_dec_bin_size(struct iris_inst *inst) 463 { 464 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 465 struct v4l2_format *f = inst->fmt_src; 466 u32 height = f->fmt.pix_mp.height; 467 u32 width = f->fmt.pix_mp.width; 468 469 if (inst->codec == V4L2_PIX_FMT_H264) 470 return hfi_buffer_bin_h264d(width, height, num_vpp_pipes); 471 else if (inst->codec == V4L2_PIX_FMT_HEVC) 472 return hfi_buffer_bin_h265d(width, height, num_vpp_pipes); 473 else if (inst->codec == V4L2_PIX_FMT_VP9) 474 return hfi_buffer_bin_vp9d(width, height, num_vpp_pipes); 475 476 return 0; 477 } 478 479 static u32 iris_vpu_dec_comv_size(struct iris_inst *inst) 480 { 481 u32 num_comv = VIDEO_MAX_FRAME; 482 struct v4l2_format *f = inst->fmt_src; 483 u32 height = f->fmt.pix_mp.height; 484 u32 width = f->fmt.pix_mp.width; 485 486 if (inst->codec == V4L2_PIX_FMT_H264) 487 return hfi_buffer_comv_h264d(width, height, num_comv); 488 else if (inst->codec == V4L2_PIX_FMT_HEVC) 489 return hfi_buffer_comv_h265d(width, height, num_comv); 490 491 return 0; 492 } 493 494 static u32 iris_vpu_dec_persist_size(struct iris_inst *inst) 495 { 496 if (inst->codec == V4L2_PIX_FMT_H264) 497 return hfi_buffer_persist_h264d(); 498 else if (inst->codec == V4L2_PIX_FMT_HEVC) 499 return hfi_buffer_persist_h265d(0); 500 else if (inst->codec == V4L2_PIX_FMT_VP9) 501 return hfi_buffer_persist_vp9d(); 502 503 return 0; 504 } 505 506 static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst) 507 { 508 if (iris_split_mode_enabled(inst)) 509 return iris_get_buffer_size(inst, BUF_DPB); 510 else 511 return 0; 512 } 513 514 static u32 iris_vpu_dec_non_comv_size(struct iris_inst *inst) 515 { 516 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 517 struct v4l2_format *f = inst->fmt_src; 518 u32 height = f->fmt.pix_mp.height; 519 u32 width = f->fmt.pix_mp.width; 520 521 if (inst->codec == V4L2_PIX_FMT_H264) 522 return hfi_buffer_non_comv_h264d(width, height, num_vpp_pipes); 523 else if (inst->codec == V4L2_PIX_FMT_HEVC) 524 return hfi_buffer_non_comv_h265d(width, height, num_vpp_pipes); 525 526 return 0; 527 } 528 529 static u32 iris_vpu_dec_line_size(struct iris_inst *inst) 530 { 531 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 532 struct v4l2_format *f = inst->fmt_src; 533 u32 height = f->fmt.pix_mp.height; 534 u32 width = f->fmt.pix_mp.width; 535 bool is_opb = false; 536 u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count; 537 538 if (iris_split_mode_enabled(inst)) 539 is_opb = true; 540 541 if (inst->codec == V4L2_PIX_FMT_H264) 542 return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); 543 else if (inst->codec == V4L2_PIX_FMT_HEVC) 544 return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); 545 else if (inst->codec == V4L2_PIX_FMT_VP9) 546 return hfi_buffer_line_vp9d(width, height, out_min_count, is_opb, 547 num_vpp_pipes); 548 549 return 0; 550 } 551 552 static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst) 553 { 554 return iris_vpu_dec_comv_size(inst) + 555 iris_vpu_dec_non_comv_size(inst) + 556 iris_vpu_dec_line_size(inst); 557 } 558 559 static inline u32 size_bin_bitstream_enc(u32 width, u32 height, 560 u32 rc_type) 561 { 562 u32 aligned_height = ALIGN(height, 32); 563 u32 aligned_width = ALIGN(width, 32); 564 u32 frame_size = width * height * 3; 565 u32 mbs_per_frame; 566 567 /* 568 * Encoder output size calculation: 32 Align width/height 569 * For resolution < 720p : YUVsize * 4 570 * For resolution > 720p & <= 4K : YUVsize / 2 571 * For resolution > 4k : YUVsize / 4 572 * Initially frame_size = YUVsize * 2; 573 */ 574 575 mbs_per_frame = (ALIGN(aligned_height, 16) * ALIGN(aligned_width, 16)) / 256; 576 577 if (mbs_per_frame < NUM_MBS_720P) 578 frame_size = frame_size << 1; 579 else if (mbs_per_frame <= NUM_MBS_4K) 580 frame_size = frame_size >> 2; 581 else 582 frame_size = frame_size >> 3; 583 584 if (rc_type == HFI_RATE_CONTROL_OFF || rc_type == HFI_RATE_CONTROL_CQ || 585 rc_type == HFI_RC_OFF || rc_type == HFI_RC_CQ) 586 frame_size = frame_size << 1; 587 588 /* 589 * In case of opaque color format bitdepth will be known 590 * with first ETB, buffers allocated already with 8 bit 591 * won't be sufficient for 10 bit 592 * calculate size considering 10-bit by default 593 * For 10-bit cases size = size * 1.25 594 */ 595 frame_size *= 5; 596 frame_size /= 4; 597 598 return ALIGN(frame_size, SZ_4K); 599 } 600 601 static inline u32 hfi_buffer_bin_enc(u32 width, u32 height, 602 u32 work_mode, u32 lcu_size, 603 u32 num_vpp_pipes, u32 rc_type) 604 { 605 u32 sao_bin_buffer_size, padded_bin_size, bitstream_size; 606 u32 total_bitbin_buffers, size_single_pipe, bitbin_size; 607 u32 aligned_height = ALIGN(height, lcu_size); 608 u32 aligned_width = ALIGN(width, lcu_size); 609 610 bitstream_size = size_bin_bitstream_enc(width, height, rc_type); 611 bitstream_size = ALIGN(bitstream_size, 256); 612 613 if (work_mode == STAGE_2) { 614 total_bitbin_buffers = 3; 615 bitbin_size = bitstream_size * 17 / 10; 616 bitbin_size = ALIGN(bitbin_size, 256); 617 } else { 618 total_bitbin_buffers = 1; 619 bitstream_size = aligned_width * aligned_height * 3; 620 bitbin_size = ALIGN(bitstream_size, 256); 621 } 622 623 if (num_vpp_pipes > 2) 624 size_single_pipe = bitbin_size / 2; 625 else 626 size_single_pipe = bitbin_size; 627 628 size_single_pipe = ALIGN(size_single_pipe, 256); 629 sao_bin_buffer_size = (64 * (((width + 32) * (height + 32)) >> 10)) + 384; 630 padded_bin_size = ALIGN(size_single_pipe, 256); 631 size_single_pipe = sao_bin_buffer_size + padded_bin_size; 632 size_single_pipe = ALIGN(size_single_pipe, 256); 633 bitbin_size = size_single_pipe * num_vpp_pipes; 634 635 return ALIGN(bitbin_size, 256) * total_bitbin_buffers + 512; 636 } 637 638 static u32 iris_vpu_enc_bin_size(struct iris_inst *inst) 639 { 640 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 641 u32 stage = inst->fw_caps[STAGE].value; 642 struct v4l2_format *f = inst->fmt_dst; 643 u32 height = f->fmt.pix_mp.height; 644 u32 width = f->fmt.pix_mp.width; 645 u32 lcu_size; 646 647 if (inst->codec == V4L2_PIX_FMT_HEVC) 648 lcu_size = 32; 649 else 650 lcu_size = 16; 651 652 return hfi_buffer_bin_enc(width, height, stage, lcu_size, 653 num_vpp_pipes, inst->hfi_rc_type); 654 } 655 656 static inline 657 u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_height, u32 lcu_size, 658 u32 num_recon, u32 standard) 659 { 660 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 661 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 662 u32 num_lcu_in_frame = width_in_lcus * height_in_lcus; 663 u32 mb_height = ((frame_height) + 15) >> 4; 664 u32 mb_width = ((frame_width) + 15) >> 4; 665 u32 size_colloc_mv, size_colloc_rc; 666 667 size_colloc_mv = (standard == HFI_CODEC_ENCODE_HEVC) ? 668 (16 * ((num_lcu_in_frame << 2) + 32)) : 669 (3 * 16 * (width_in_lcus * height_in_lcus + 32)); 670 size_colloc_mv = ALIGN(size_colloc_mv, 256) * num_recon; 671 size_colloc_rc = (((mb_width + 7) >> 3) * 16 * 2 * mb_height); 672 size_colloc_rc = ALIGN(size_colloc_rc, 256) * HFI_MAX_COL_FRAME; 673 674 return size_colloc_mv + size_colloc_rc; 675 } 676 677 static u32 iris_vpu_enc_comv_size(struct iris_inst *inst) 678 { 679 struct v4l2_format *f = inst->fmt_dst; 680 u32 height = f->fmt.pix_mp.height; 681 u32 width = f->fmt.pix_mp.width; 682 u32 num_recon = 1; 683 u32 lcu_size = 16; 684 685 if (inst->codec == V4L2_PIX_FMT_HEVC) { 686 lcu_size = 32; 687 return hfi_buffer_comv_enc(width, height, lcu_size, 688 num_recon + 1, HFI_CODEC_ENCODE_HEVC); 689 } 690 691 return hfi_buffer_comv_enc(width, height, lcu_size, 692 num_recon + 1, HFI_CODEC_ENCODE_AVC); 693 } 694 695 static inline 696 u32 size_frame_rc_buf_size(u32 standard, u32 frame_height_coded, 697 u32 num_vpp_pipes_enc) 698 { 699 u32 size = 0; 700 701 size = (standard == HFI_CODEC_ENCODE_HEVC) ? 702 (256 + 16 * (14 + ((((frame_height_coded) >> 5) + 7) >> 3))) : 703 (256 + 16 * (14 + ((((frame_height_coded) >> 4) + 7) >> 3))); 704 size *= 11; 705 706 if (num_vpp_pipes_enc > 1) 707 size = ALIGN(size, 256) * num_vpp_pipes_enc; 708 709 return ALIGN(size, 512) * HFI_MAX_COL_FRAME; 710 } 711 712 static inline 713 u32 size_enc_slice_info_buf(u32 num_lcu_in_frame) 714 { 715 return ALIGN((256 + (num_lcu_in_frame << 4)), 256); 716 } 717 718 static inline u32 enc_bitcnt_buf_size(u32 num_lcu_in_frame) 719 { 720 return ALIGN((256 + (4 * (num_lcu_in_frame))), 256); 721 } 722 723 static inline u32 enc_bitmap_buf_size(u32 num_lcu_in_frame) 724 { 725 return ALIGN((256 + ((num_lcu_in_frame) >> 3)), 256); 726 } 727 728 static inline u32 size_override_buf(u32 num_lcumb) 729 { 730 return ALIGN(((16 * (((num_lcumb) + 7) >> 3))), 256) * 2; 731 } 732 733 static inline u32 size_ir_buf(u32 num_lcu_in_frame) 734 { 735 return ALIGN((((((num_lcu_in_frame) << 1) + 7) & (~7)) * 3), 256); 736 } 737 738 static inline 739 u32 size_linebuff_data(bool is_ten_bit, u32 frame_width_coded) 740 { 741 return is_ten_bit ? 742 (((((10 * (frame_width_coded) + 1024) + (256 - 1)) & 743 (~(256 - 1))) * 1) + 744 (((((10 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & 745 (~(256 - 1))) * 2)) : 746 (((((8 * (frame_width_coded) + 1024) + (256 - 1)) & 747 (~(256 - 1))) * 1) + 748 (((((8 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & 749 (~(256 - 1))) * 2)); 750 } 751 752 static inline 753 u32 size_left_linebuff_ctrl(u32 standard, u32 frame_height_coded, 754 u32 num_vpp_pipes_enc) 755 { 756 u32 size = 0; 757 758 size = standard == HFI_CODEC_ENCODE_HEVC ? 759 (((frame_height_coded) + 760 (32)) / 32 * 4 * 16) : 761 (((frame_height_coded) + 15) / 16 * 5 * 16); 762 763 if ((num_vpp_pipes_enc) > 1) { 764 size += 512; 765 size = ALIGN(size, 512) * 766 num_vpp_pipes_enc; 767 } 768 769 return ALIGN(size, 256); 770 } 771 772 static inline 773 u32 size_left_linebuff_recon_pix(bool is_ten_bit, u32 frame_height_coded, 774 u32 num_vpp_pipes_enc) 775 { 776 return (((is_ten_bit + 1) * 2 * (frame_height_coded) + 256) + 777 (256 << (num_vpp_pipes_enc - 1)) - 1) & 778 (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1; 779 } 780 781 static inline 782 u32 size_top_linebuff_ctrl_fe(u32 frame_width_coded, u32 standard) 783 { 784 return standard == HFI_CODEC_ENCODE_HEVC ? 785 ALIGN((64 * ((frame_width_coded) >> 5)), 256) : 786 ALIGN((256 + 16 * ((frame_width_coded) >> 4)), 256); 787 } 788 789 static inline 790 u32 size_left_linebuff_ctrl_fe(u32 frame_height_coded, u32 num_vpp_pipes_enc) 791 { 792 return (((256 + 64 * ((frame_height_coded) >> 4)) + 793 (256 << (num_vpp_pipes_enc - 1)) - 1) & 794 (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1) * 795 num_vpp_pipes_enc; 796 } 797 798 static inline 799 u32 size_left_linebuff_metadata_recon_y(u32 frame_height_coded, 800 bool is_ten_bit, 801 u32 num_vpp_pipes_enc) 802 { 803 return ALIGN(((256 + 64 * ((frame_height_coded) / 804 (8 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; 805 } 806 807 static inline 808 u32 size_left_linebuff_metadata_recon_uv(u32 frame_height_coded, 809 bool is_ten_bit, 810 u32 num_vpp_pipes_enc) 811 { 812 return ALIGN(((256 + 64 * ((frame_height_coded) / 813 (4 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; 814 } 815 816 static inline 817 u32 size_linebuff_recon_pix(bool is_ten_bit, u32 frame_width_coded) 818 { 819 return ALIGN(((is_ten_bit ? 3 : 2) * (frame_width_coded)), 256); 820 } 821 822 static inline 823 u32 size_line_buf_ctrl(u32 frame_width_coded) 824 { 825 return ALIGN(frame_width_coded, 256); 826 } 827 828 static inline 829 u32 size_line_buf_ctrl_id2(u32 frame_width_coded) 830 { 831 return ALIGN(frame_width_coded, 256); 832 } 833 834 static inline u32 size_line_buf_sde(u32 frame_width_coded) 835 { 836 return ALIGN((256 + (16 * ((frame_width_coded) >> 4))), 256); 837 } 838 839 static inline 840 u32 size_vpss_line_buf(u32 num_vpp_pipes_enc, u32 frame_height_coded, 841 u32 frame_width_coded) 842 { 843 return ALIGN(((((((8192) >> 2) << 5) * (num_vpp_pipes_enc)) + 64) + 844 (((((max_t(u32, (frame_width_coded), 845 (frame_height_coded)) + 3) >> 2) << 5) + 256) * 16)), 256); 846 } 847 static inline 848 u32 size_vpss_line_buf_vpu33(u32 num_vpp_pipes_enc, u32 frame_height_coded, 849 u32 frame_width_coded) 850 { 851 u32 vpss_4tap_top, vpss_4tap_left, vpss_div2_top; 852 u32 vpss_div2_left, vpss_top_lb, vpss_left_lb; 853 u32 size_left, size_top; 854 u32 max_width_height; 855 856 max_width_height = max_t(u32, frame_width_coded, frame_height_coded); 857 vpss_4tap_top = ((((max_width_height * 2) + 3) >> 2) << 4) + 256; 858 vpss_4tap_left = (((8192 + 3) >> 2) << 5) + 64; 859 vpss_div2_top = (((max_width_height + 3) >> 2) << 4) + 256; 860 vpss_div2_left = ((((max_width_height * 2) + 3) >> 2) << 5) + 64; 861 vpss_top_lb = (frame_width_coded + 1) << 3; 862 vpss_left_lb = (frame_height_coded << 3) * num_vpp_pipes_enc; 863 size_left = (vpss_4tap_left + vpss_div2_left) * 2 * num_vpp_pipes_enc; 864 size_top = (vpss_4tap_top + vpss_div2_top) * 2; 865 866 return ALIGN(size_left + size_top + vpss_top_lb + vpss_left_lb, DMA_ALIGNMENT); 867 } 868 869 static inline 870 u32 size_top_line_buf_first_stg_sao(u32 frame_width_coded) 871 { 872 return ALIGN((16 * ((frame_width_coded) >> 5)), 256); 873 } 874 875 static inline 876 u32 size_enc_ref_buffer(u32 frame_width, u32 frame_height) 877 { 878 u32 u_chroma_buffer_height = ALIGN(frame_height >> 1, 32); 879 u32 u_buffer_height = ALIGN(frame_height, 32); 880 u32 u_buffer_width = ALIGN(frame_width, 32); 881 882 return (u_buffer_height + u_chroma_buffer_height) * u_buffer_width; 883 } 884 885 static inline 886 u32 size_enc_ten_bit_ref_buffer(u32 frame_width, u32 frame_height) 887 { 888 u32 ref_luma_stride_in_bytes = ((frame_width + SYSTEM_LAL_TILE10 - 1) / SYSTEM_LAL_TILE10) * 889 SYSTEM_LAL_TILE10; 890 u32 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1)); 891 u32 u_ref_stride, luma_size; 892 u32 ref_chrm_height_in_bytes; 893 u32 chroma_size; 894 895 u_ref_stride = 4 * (ref_luma_stride_in_bytes / 3); 896 u_ref_stride = (u_ref_stride + (128 - 1)) & (~(128 - 1)); 897 luma_size = ref_buf_height * u_ref_stride; 898 luma_size = (luma_size + (4096 - 1)) & (~(4096 - 1)); 899 900 ref_chrm_height_in_bytes = (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); 901 chroma_size = u_ref_stride * ref_chrm_height_in_bytes; 902 chroma_size = (chroma_size + (4096 - 1)) & (~(4096 - 1)); 903 904 return luma_size + chroma_size; 905 } 906 907 static inline 908 u32 hfi_ubwc_calc_metadata_plane_stride(u32 frame_width, 909 u32 metadata_stride_multiple, 910 u32 tile_width_in_pels) 911 { 912 return ALIGN(((frame_width + (tile_width_in_pels - 1)) / tile_width_in_pels), 913 metadata_stride_multiple); 914 } 915 916 static inline 917 u32 hfi_ubwc_metadata_plane_bufheight(u32 frame_height, 918 u32 metadata_height_multiple, 919 u32 tile_height_in_pels) 920 { 921 return ALIGN(((frame_height + (tile_height_in_pels - 1)) / tile_height_in_pels), 922 metadata_height_multiple); 923 } 924 925 static inline 926 u32 hfi_ubwc_metadata_plane_buffer_size(u32 _metadata_tride, u32 _metadata_buf_height) 927 { 928 return ALIGN(_metadata_tride * _metadata_buf_height, 4096); 929 } 930 931 static inline 932 u32 hfi_buffer_non_comv_enc(u32 frame_width, u32 frame_height, 933 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 934 { 935 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 936 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 937 u32 num_lcu_in_frame = width_in_lcus * height_in_lcus; 938 u32 frame_height_coded = height_in_lcus * (lcu_size); 939 u32 frame_width_coded = width_in_lcus * (lcu_size); 940 u32 num_lcumb, frame_rc_buf_size; 941 942 num_lcumb = (frame_height_coded / lcu_size) * 943 ((frame_width_coded + lcu_size * 8) / lcu_size); 944 frame_rc_buf_size = size_frame_rc_buf_size(standard, frame_height_coded, 945 num_vpp_pipes_enc); 946 return size_enc_slice_info_buf(num_lcu_in_frame) + 947 SIZE_SLICE_CMD_BUFFER + 948 SIZE_SPS_PPS_SLICE_HDR + 949 frame_rc_buf_size + 950 enc_bitcnt_buf_size(num_lcu_in_frame) + 951 enc_bitmap_buf_size(num_lcu_in_frame) + 952 SIZE_BSE_SLICE_CMD_BUF + 953 SIZE_LAMBDA_LUT + 954 size_override_buf(num_lcumb) + 955 size_ir_buf(num_lcu_in_frame); 956 } 957 958 static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst) 959 { 960 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 961 struct v4l2_format *f = inst->fmt_dst; 962 u32 height = f->fmt.pix_mp.height; 963 u32 width = f->fmt.pix_mp.width; 964 u32 lcu_size = 16; 965 966 if (inst->codec == V4L2_PIX_FMT_HEVC) { 967 lcu_size = 32; 968 return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, 969 lcu_size, HFI_CODEC_ENCODE_HEVC) + 970 SIZE_ONE_SLICE_BUF; 971 } 972 973 return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, 974 lcu_size, HFI_CODEC_ENCODE_AVC); 975 } 976 977 static inline 978 u32 hfi_buffer_line_enc_base(u32 frame_width, u32 frame_height, bool is_ten_bit, 979 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 980 { 981 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 982 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 983 u32 frame_height_coded = height_in_lcus * (lcu_size); 984 u32 frame_width_coded = width_in_lcus * (lcu_size); 985 u32 line_buff_data_size, left_line_buff_ctrl_size; 986 u32 left_line_buff_metadata_recon__uv__size; 987 u32 left_line_buff_metadata_recon__y__size; 988 u32 left_line_buff_recon_pix_size; 989 u32 top_line_buff_ctrl_fe_size; 990 u32 line_buff_recon_pix_size; 991 992 line_buff_data_size = size_linebuff_data(is_ten_bit, frame_width_coded); 993 left_line_buff_ctrl_size = 994 size_left_linebuff_ctrl(standard, frame_height_coded, num_vpp_pipes_enc); 995 left_line_buff_recon_pix_size = 996 size_left_linebuff_recon_pix(is_ten_bit, frame_height_coded, 997 num_vpp_pipes_enc); 998 top_line_buff_ctrl_fe_size = 999 size_top_linebuff_ctrl_fe(frame_width_coded, standard); 1000 left_line_buff_metadata_recon__y__size = 1001 size_left_linebuff_metadata_recon_y(frame_height_coded, is_ten_bit, 1002 num_vpp_pipes_enc); 1003 left_line_buff_metadata_recon__uv__size = 1004 size_left_linebuff_metadata_recon_uv(frame_height_coded, is_ten_bit, 1005 num_vpp_pipes_enc); 1006 line_buff_recon_pix_size = size_linebuff_recon_pix(is_ten_bit, frame_width_coded); 1007 1008 return size_line_buf_ctrl(frame_width_coded) + 1009 size_line_buf_ctrl_id2(frame_width_coded) + 1010 line_buff_data_size + 1011 left_line_buff_ctrl_size + 1012 left_line_buff_recon_pix_size + 1013 top_line_buff_ctrl_fe_size + 1014 left_line_buff_metadata_recon__y__size + 1015 left_line_buff_metadata_recon__uv__size + 1016 line_buff_recon_pix_size + 1017 size_left_linebuff_ctrl_fe(frame_height_coded, num_vpp_pipes_enc) + 1018 size_line_buf_sde(frame_width_coded) + 1019 size_top_line_buf_first_stg_sao(frame_width_coded); 1020 } 1021 1022 static inline 1023 u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit, 1024 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 1025 { 1026 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 1027 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 1028 u32 frame_height_coded = height_in_lcus * (lcu_size); 1029 u32 frame_width_coded = width_in_lcus * (lcu_size); 1030 1031 return hfi_buffer_line_enc_base(frame_width, frame_height, is_ten_bit, 1032 num_vpp_pipes_enc, lcu_size, standard) + 1033 size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_coded); 1034 } 1035 1036 static inline 1037 u32 hfi_buffer_line_enc_vpu33(u32 frame_width, u32 frame_height, bool is_ten_bit, 1038 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) 1039 { 1040 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size); 1041 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size); 1042 u32 frame_height_coded = height_in_lcus * (lcu_size); 1043 u32 frame_width_coded = width_in_lcus * (lcu_size); 1044 1045 return hfi_buffer_line_enc_base(frame_width, frame_height, is_ten_bit, 1046 num_vpp_pipes_enc, lcu_size, standard) + 1047 size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_height_coded, 1048 frame_width_coded); 1049 } 1050 1051 static u32 iris_vpu_enc_line_size(struct iris_inst *inst) 1052 { 1053 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1054 struct v4l2_format *f = inst->fmt_dst; 1055 u32 height = f->fmt.pix_mp.height; 1056 u32 width = f->fmt.pix_mp.width; 1057 u32 lcu_size = 16; 1058 1059 if (inst->codec == V4L2_PIX_FMT_HEVC) { 1060 lcu_size = 32; 1061 return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, 1062 lcu_size, HFI_CODEC_ENCODE_HEVC); 1063 } 1064 1065 return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, 1066 lcu_size, HFI_CODEC_ENCODE_AVC); 1067 } 1068 1069 static u32 iris_vpu33_enc_line_size(struct iris_inst *inst) 1070 { 1071 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1072 struct v4l2_format *f = inst->fmt_dst; 1073 u32 height = f->fmt.pix_mp.height; 1074 u32 width = f->fmt.pix_mp.width; 1075 u32 lcu_size = 16; 1076 1077 if (inst->codec == V4L2_PIX_FMT_HEVC) { 1078 lcu_size = 32; 1079 return hfi_buffer_line_enc_vpu33(width, height, 0, num_vpp_pipes, 1080 lcu_size, HFI_CODEC_ENCODE_HEVC); 1081 } 1082 1083 return hfi_buffer_line_enc_vpu33(width, height, 0, num_vpp_pipes, 1084 lcu_size, HFI_CODEC_ENCODE_AVC); 1085 } 1086 1087 static inline 1088 u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit) 1089 { 1090 u32 metadata_stride, metadata_buf_height, meta_size_y, meta_size_c; 1091 u32 ten_bit_ref_buf_size = 0, ref_buf_size = 0; 1092 u32 size; 1093 1094 if (!is_ten_bit) { 1095 ref_buf_size = size_enc_ref_buffer(frame_width, frame_height); 1096 metadata_stride = 1097 hfi_ubwc_calc_metadata_plane_stride(frame_width, 64, 1098 HFI_COL_FMT_NV12C_Y_TILE_WIDTH); 1099 metadata_buf_height = 1100 hfi_ubwc_metadata_plane_bufheight(frame_height, 16, 1101 HFI_COL_FMT_NV12C_Y_TILE_HEIGHT); 1102 meta_size_y = 1103 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1104 meta_size_c = 1105 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1106 size = ref_buf_size + meta_size_y + meta_size_c; 1107 } else { 1108 ten_bit_ref_buf_size = size_enc_ten_bit_ref_buffer(frame_width, frame_height); 1109 metadata_stride = 1110 hfi_ubwc_calc_metadata_plane_stride(frame_width, 1111 IRIS_METADATA_STRIDE_MULTIPLE, 1112 HFI_COL_FMT_TP10C_Y_TILE_WIDTH); 1113 metadata_buf_height = 1114 hfi_ubwc_metadata_plane_bufheight(frame_height, 1115 IRIS_METADATA_HEIGHT_MULTIPLE, 1116 HFI_COL_FMT_TP10C_Y_TILE_HEIGHT); 1117 meta_size_y = 1118 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1119 meta_size_c = 1120 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height); 1121 size = ten_bit_ref_buf_size + meta_size_y + meta_size_c; 1122 } 1123 1124 return size; 1125 } 1126 1127 static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) 1128 { 1129 return HFI_BUFFER_ARP_ENC; 1130 } 1131 1132 inline bool is_scaling_enabled(struct iris_inst *inst) 1133 { 1134 return inst->crop.left != inst->compose.left || 1135 inst->crop.top != inst->compose.top || 1136 inst->crop.width != inst->compose.width || 1137 inst->crop.height != inst->compose.height; 1138 } 1139 1140 static inline 1141 u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable, 1142 u32 blur, bool is_ten_bit) 1143 { 1144 if (ds_enable || blur) 1145 return hfi_buffer_dpb_enc(dswidth, dsheight, is_ten_bit); 1146 1147 return 0; 1148 } 1149 1150 static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_height, 1151 u32 lcu_size, u32 num_ref, 1152 bool ten_bit, u32 num_vpp_pipes, 1153 bool is_h265) 1154 { 1155 u32 line_buf_ctrl_size, line_buf_data_size, leftline_buf_ctrl_size; 1156 u32 line_buf_sde_size, sps_pps_slice_hdr, topline_buf_ctrl_size_FE; 1157 u32 leftline_buf_ctrl_size_FE, line_buf_recon_pix_size; 1158 u32 leftline_buf_recon_pix_size, lambda_lut_size, override_buffer_size; 1159 u32 col_mv_buf_size, vpp_reg_buffer_size, ir_buffer_size; 1160 u32 vpss_line_buf, leftline_buf_meta_recony, h265e_colrcbuf_size; 1161 u32 h265e_framerc_bufsize, h265e_lcubitcnt_bufsize; 1162 u32 h265e_lcubitmap_bufsize, se_stats_bufsize; 1163 u32 bse_reg_buffer_size, bse_slice_cmd_buffer_size, slice_info_bufsize; 1164 u32 line_buf_ctrl_size_buffid2, slice_cmd_buffer_size; 1165 u32 width_lcu_num, height_lcu_num, width_coded, height_coded; 1166 u32 frame_num_lcu, linebuf_meta_recon_uv, topline_bufsize_fe_1stg_sao; 1167 u32 vpss_line_buffer_size_1; 1168 u32 bit_depth, num_lcu_mb; 1169 1170 width_lcu_num = (frame_width + lcu_size - 1) / lcu_size; 1171 height_lcu_num = (frame_height + lcu_size - 1) / lcu_size; 1172 frame_num_lcu = width_lcu_num * height_lcu_num; 1173 width_coded = width_lcu_num * lcu_size; 1174 height_coded = height_lcu_num * lcu_size; 1175 num_lcu_mb = (height_coded / lcu_size) * 1176 ((width_coded + lcu_size * 8) / lcu_size); 1177 slice_info_bufsize = 256 + (frame_num_lcu << 4); 1178 slice_info_bufsize = ALIGN(slice_info_bufsize, 256); 1179 line_buf_ctrl_size = ALIGN(width_coded, 256); 1180 line_buf_ctrl_size_buffid2 = ALIGN(width_coded, 256); 1181 1182 bit_depth = ten_bit ? 10 : 8; 1183 line_buf_data_size = 1184 (((((bit_depth * width_coded + 1024) + (256 - 1)) & 1185 (~(256 - 1))) * 1) + 1186 (((((bit_depth * width_coded + 1024) >> 1) + (256 - 1)) & 1187 (~(256 - 1))) * 2)); 1188 1189 leftline_buf_ctrl_size = is_h265 ? ((height_coded + 32) / 32 * 4 * 16) : 1190 ((height_coded + 15) / 16 * 5 * 16); 1191 1192 if (num_vpp_pipes > 1) { 1193 leftline_buf_ctrl_size += 512; 1194 leftline_buf_ctrl_size = 1195 ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes; 1196 } 1197 1198 leftline_buf_ctrl_size = ALIGN(leftline_buf_ctrl_size, 256); 1199 leftline_buf_recon_pix_size = 1200 (((ten_bit + 1) * 2 * (height_coded) + 256) + 1201 (256 << (num_vpp_pipes - 1)) - 1) & 1202 (~((256 << (num_vpp_pipes - 1)) - 1)) * 1; 1203 1204 topline_buf_ctrl_size_FE = is_h265 ? (64 * (width_coded >> 5)) : 1205 (256 + 16 * (width_coded >> 4)); 1206 topline_buf_ctrl_size_FE = ALIGN(topline_buf_ctrl_size_FE, 256); 1207 leftline_buf_ctrl_size_FE = 1208 (((256 + 64 * (height_coded >> 4)) + 1209 (256 << (num_vpp_pipes - 1)) - 1) & 1210 (~((256 << (num_vpp_pipes - 1)) - 1)) * 1) * 1211 num_vpp_pipes; 1212 leftline_buf_meta_recony = 1213 (256 + 64 * ((height_coded) / (8 * (ten_bit ? 4 : 8)))); 1214 leftline_buf_meta_recony = ALIGN(leftline_buf_meta_recony, 256); 1215 leftline_buf_meta_recony = leftline_buf_meta_recony * num_vpp_pipes; 1216 linebuf_meta_recon_uv = 1217 (256 + 64 * ((height_coded) / (4 * (ten_bit ? 4 : 8)))); 1218 linebuf_meta_recon_uv = ALIGN(linebuf_meta_recon_uv, 256); 1219 linebuf_meta_recon_uv = linebuf_meta_recon_uv * num_vpp_pipes; 1220 line_buf_recon_pix_size = ((ten_bit ? 3 : 2) * width_coded); 1221 line_buf_recon_pix_size = ALIGN(line_buf_recon_pix_size, 256); 1222 slice_cmd_buffer_size = ALIGN(20480, 256); 1223 sps_pps_slice_hdr = 2048 + 4096; 1224 col_mv_buf_size = 1225 is_h265 ? (16 * ((frame_num_lcu << 2) + 32)) : 1226 (3 * 16 * (width_lcu_num * height_lcu_num + 32)); 1227 col_mv_buf_size = ALIGN(col_mv_buf_size, 256) * (num_ref + 1); 1228 h265e_colrcbuf_size = 1229 (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); 1230 if (num_vpp_pipes > 1) 1231 h265e_colrcbuf_size = 1232 ALIGN(h265e_colrcbuf_size, 256) * num_vpp_pipes; 1233 1234 h265e_colrcbuf_size = 1235 ALIGN(h265e_colrcbuf_size, 256) * HFI_MAX_COL_FRAME; 1236 h265e_framerc_bufsize = 1237 (is_h265) ? 1238 (256 + 16 * (14 + (((height_coded >> 5) + 7) >> 3))) : 1239 (256 + 16 * (14 + (((height_coded >> 4) + 7) >> 3))); 1240 h265e_framerc_bufsize *= 6; 1241 if (num_vpp_pipes > 1) 1242 h265e_framerc_bufsize = 1243 ALIGN(h265e_framerc_bufsize, 256) * num_vpp_pipes; 1244 1245 h265e_framerc_bufsize = 1246 ALIGN(h265e_framerc_bufsize, 512) * HFI_MAX_COL_FRAME; 1247 h265e_lcubitcnt_bufsize = 256 + 4 * frame_num_lcu; 1248 h265e_lcubitcnt_bufsize = ALIGN(h265e_lcubitcnt_bufsize, 256); 1249 h265e_lcubitmap_bufsize = 256 + (frame_num_lcu >> 3); 1250 h265e_lcubitmap_bufsize = ALIGN(h265e_lcubitmap_bufsize, 256); 1251 line_buf_sde_size = 256 + 16 * (width_coded >> 4); 1252 line_buf_sde_size = ALIGN(line_buf_sde_size, 256); 1253 if ((width_coded * height_coded) > (4096 * 2160)) 1254 se_stats_bufsize = 0; 1255 else if ((width_coded * height_coded) > (1920 * 1088)) 1256 se_stats_bufsize = (40 * 4 * frame_num_lcu + 256 + 256); 1257 else 1258 se_stats_bufsize = (1024 * frame_num_lcu + 256 + 256); 1259 1260 se_stats_bufsize = ALIGN(se_stats_bufsize, 256) * 2; 1261 bse_slice_cmd_buffer_size = (((8192 << 2) + 7) & (~7)) * 6; 1262 bse_reg_buffer_size = (((512 << 3) + 7) & (~7)) * 4; 1263 vpp_reg_buffer_size = (((2048 << 3) + 31) & (~31)) * 10; 1264 lambda_lut_size = 256 * 11; 1265 override_buffer_size = 16 * ((num_lcu_mb + 7) >> 3); 1266 override_buffer_size = ALIGN(override_buffer_size, 256) * 2; 1267 ir_buffer_size = (((frame_num_lcu << 1) + 7) & (~7)) * 3; 1268 vpss_line_buffer_size_1 = (((8192 >> 2) << 5) * num_vpp_pipes) + 64; 1269 vpss_line_buf = 1270 (((((max(width_coded, height_coded) + 3) >> 2) << 5) + 256) * 1271 16) + 1272 vpss_line_buffer_size_1; 1273 topline_bufsize_fe_1stg_sao = 16 * (width_coded >> 5); 1274 topline_bufsize_fe_1stg_sao = ALIGN(topline_bufsize_fe_1stg_sao, 256); 1275 1276 return line_buf_ctrl_size + line_buf_data_size + 1277 line_buf_ctrl_size_buffid2 + leftline_buf_ctrl_size + 1278 vpss_line_buf + col_mv_buf_size + topline_buf_ctrl_size_FE + 1279 leftline_buf_ctrl_size_FE + line_buf_recon_pix_size + 1280 leftline_buf_recon_pix_size + leftline_buf_meta_recony + 1281 linebuf_meta_recon_uv + h265e_colrcbuf_size + 1282 h265e_framerc_bufsize + h265e_lcubitcnt_bufsize + 1283 h265e_lcubitmap_bufsize + line_buf_sde_size + 1284 topline_bufsize_fe_1stg_sao + override_buffer_size + 1285 bse_reg_buffer_size + vpp_reg_buffer_size + sps_pps_slice_hdr + 1286 slice_cmd_buffer_size + bse_slice_cmd_buffer_size + 1287 ir_buffer_size + slice_info_bufsize + lambda_lut_size + 1288 se_stats_bufsize + 1024; 1289 } 1290 1291 static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst) 1292 { 1293 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe; 1294 struct v4l2_format *f = inst->fmt_dst; 1295 u32 frame_height = f->fmt.pix_mp.height; 1296 u32 frame_width = f->fmt.pix_mp.width; 1297 u32 num_ref = 1; 1298 u32 lcu_size; 1299 bool is_h265; 1300 1301 if (inst->codec == V4L2_PIX_FMT_H264) { 1302 lcu_size = 16; 1303 is_h265 = false; 1304 } else if (inst->codec == V4L2_PIX_FMT_HEVC) { 1305 lcu_size = 32; 1306 is_h265 = true; 1307 } else { 1308 return 0; 1309 } 1310 1311 return hfi_buffer_scratch1_enc(frame_width, frame_height, lcu_size, 1312 num_ref, false, num_vpp_pipes, is_h265); 1313 } 1314 1315 static inline u32 ubwc_metadata_plane_stride(u32 width, 1316 u32 metadata_stride_multi, 1317 u32 tile_width_pels) 1318 { 1319 return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels), 1320 metadata_stride_multi); 1321 } 1322 1323 static inline u32 ubwc_metadata_plane_bufheight(u32 height, 1324 u32 metadata_height_multi, 1325 u32 tile_height_pels) 1326 { 1327 return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels), 1328 metadata_height_multi); 1329 } 1330 1331 static inline u32 ubwc_metadata_plane_buffer_size(u32 metadata_stride, 1332 u32 metadata_buf_height) 1333 { 1334 return ALIGN(metadata_stride * metadata_buf_height, SZ_4K); 1335 } 1336 1337 static inline u32 hfi_buffer_scratch2_enc(u32 frame_width, u32 frame_height, 1338 u32 num_ref, bool ten_bit) 1339 { 1340 u32 aligned_width, aligned_height, chroma_height, ref_buf_height; 1341 u32 metadata_stride, meta_buf_height, meta_size_y, meta_size_c; 1342 u32 ref_luma_stride_bytes, ref_chroma_height_bytes; 1343 u32 ref_buf_size, ref_stride; 1344 u32 luma_size, chroma_size; 1345 u32 size; 1346 1347 if (!ten_bit) { 1348 aligned_height = ALIGN(frame_height, 32); 1349 chroma_height = frame_height >> 1; 1350 chroma_height = ALIGN(chroma_height, 32); 1351 aligned_width = ALIGN(frame_width, 128); 1352 metadata_stride = 1353 ubwc_metadata_plane_stride(frame_width, 64, 32); 1354 meta_buf_height = 1355 ubwc_metadata_plane_bufheight(frame_height, 16, 8); 1356 meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, 1357 meta_buf_height); 1358 meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, 1359 meta_buf_height); 1360 size = (aligned_height + chroma_height) * aligned_width + 1361 meta_size_y + meta_size_c; 1362 size = (size * (num_ref + 3)) + 4096; 1363 } else { 1364 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1)); 1365 ref_luma_stride_bytes = ((frame_width + 192 - 1) / 192) * 192; 1366 ref_stride = 4 * (ref_luma_stride_bytes / 3); 1367 ref_stride = (ref_stride + (128 - 1)) & (~(128 - 1)); 1368 luma_size = ref_buf_height * ref_stride; 1369 ref_chroma_height_bytes = 1370 (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); 1371 chroma_size = ref_stride * ref_chroma_height_bytes; 1372 luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); 1373 chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); 1374 ref_buf_size = luma_size + chroma_size; 1375 metadata_stride = 1376 ubwc_metadata_plane_stride(frame_width, 64, 48); 1377 meta_buf_height = 1378 ubwc_metadata_plane_bufheight(frame_height, 16, 4); 1379 meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, 1380 meta_buf_height); 1381 meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, 1382 meta_buf_height); 1383 size = ref_buf_size + meta_size_y + meta_size_c; 1384 size = (size * (num_ref + 3)) + 4096; 1385 } 1386 1387 return size; 1388 } 1389 1390 static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst) 1391 { 1392 struct v4l2_format *f = inst->fmt_dst; 1393 u32 frame_width = f->fmt.pix_mp.width; 1394 u32 frame_height = f->fmt.pix_mp.height; 1395 u32 num_ref = 1; 1396 1397 return hfi_buffer_scratch2_enc(frame_width, frame_height, num_ref, 1398 false); 1399 } 1400 1401 static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst) 1402 { 1403 u32 ds_enable = is_scaling_enabled(inst); 1404 struct v4l2_format *f = inst->fmt_dst; 1405 u32 height = f->fmt.pix_mp.height; 1406 u32 width = f->fmt.pix_mp.width; 1407 1408 return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); 1409 } 1410 1411 static int output_min_count(struct iris_inst *inst) 1412 { 1413 int output_min_count = 4; 1414 1415 /* fw_min_count > 0 indicates reconfig event has already arrived */ 1416 if (inst->fw_min_count) { 1417 if (iris_split_mode_enabled(inst) && inst->codec == V4L2_PIX_FMT_VP9) 1418 return min_t(u32, 4, inst->fw_min_count); 1419 else 1420 return inst->fw_min_count; 1421 } 1422 1423 if (inst->codec == V4L2_PIX_FMT_VP9) 1424 output_min_count = 9; 1425 1426 return output_min_count; 1427 } 1428 1429 struct iris_vpu_buf_type_handle { 1430 enum iris_buffer_type type; 1431 u32 (*handle)(struct iris_inst *inst); 1432 }; 1433 1434 u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) 1435 { 1436 const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL; 1437 u32 size = 0, buf_type_handle_size = 0, i; 1438 1439 static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = { 1440 {BUF_BIN, iris_vpu_dec_bin_size }, 1441 {BUF_COMV, iris_vpu_dec_comv_size }, 1442 {BUF_NON_COMV, iris_vpu_dec_non_comv_size }, 1443 {BUF_LINE, iris_vpu_dec_line_size }, 1444 {BUF_PERSIST, iris_vpu_dec_persist_size }, 1445 {BUF_DPB, iris_vpu_dec_dpb_size }, 1446 {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, 1447 }; 1448 1449 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = { 1450 {BUF_BIN, iris_vpu_enc_bin_size }, 1451 {BUF_COMV, iris_vpu_enc_comv_size }, 1452 {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, 1453 {BUF_LINE, iris_vpu_enc_line_size }, 1454 {BUF_ARP, iris_vpu_enc_arp_size }, 1455 {BUF_VPSS, iris_vpu_enc_vpss_size }, 1456 {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, 1457 {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, 1458 }; 1459 1460 if (inst->domain == DECODER) { 1461 buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle); 1462 buf_type_handle_arr = dec_internal_buf_type_handle; 1463 } else if (inst->domain == ENCODER) { 1464 buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle); 1465 buf_type_handle_arr = enc_internal_buf_type_handle; 1466 } 1467 1468 for (i = 0; i < buf_type_handle_size; i++) { 1469 if (buf_type_handle_arr[i].type == buffer_type) { 1470 size = buf_type_handle_arr[i].handle(inst); 1471 break; 1472 } 1473 } 1474 1475 return size; 1476 } 1477 1478 u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) 1479 { 1480 u32 size = 0, i; 1481 1482 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = { 1483 {BUF_BIN, iris_vpu_enc_bin_size }, 1484 {BUF_COMV, iris_vpu_enc_comv_size }, 1485 {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, 1486 {BUF_LINE, iris_vpu33_enc_line_size }, 1487 {BUF_ARP, iris_vpu_enc_arp_size }, 1488 {BUF_VPSS, iris_vpu_enc_vpss_size }, 1489 {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, 1490 {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, 1491 }; 1492 1493 if (inst->domain == DECODER) 1494 return iris_vpu_buf_size(inst, buffer_type); 1495 1496 for (i = 0; i < ARRAY_SIZE(enc_internal_buf_type_handle); i++) { 1497 if (enc_internal_buf_type_handle[i].type == buffer_type) { 1498 size = enc_internal_buf_type_handle[i].handle(inst); 1499 break; 1500 } 1501 } 1502 1503 return size; 1504 } 1505 1506 static u32 internal_buffer_count(struct iris_inst *inst, 1507 enum iris_buffer_type buffer_type) 1508 { 1509 if (buffer_type == BUF_BIN || buffer_type == BUF_LINE || 1510 buffer_type == BUF_PERSIST) { 1511 return 1; 1512 } else if (buffer_type == BUF_COMV || buffer_type == BUF_NON_COMV) { 1513 if (inst->codec == V4L2_PIX_FMT_H264 || inst->codec == V4L2_PIX_FMT_HEVC) 1514 return 1; 1515 } 1516 return 0; 1517 } 1518 1519 static inline int iris_vpu_dpb_count(struct iris_inst *inst) 1520 { 1521 if (iris_split_mode_enabled(inst)) { 1522 return inst->fw_min_count ? 1523 inst->fw_min_count : inst->buffers[BUF_OUTPUT].min_count; 1524 } 1525 1526 return 0; 1527 } 1528 1529 int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) 1530 { 1531 switch (buffer_type) { 1532 case BUF_INPUT: 1533 return MIN_BUFFERS; 1534 case BUF_OUTPUT: 1535 if (inst->domain == ENCODER) 1536 return MIN_BUFFERS; 1537 else 1538 return output_min_count(inst); 1539 case BUF_BIN: 1540 case BUF_COMV: 1541 case BUF_NON_COMV: 1542 case BUF_LINE: 1543 case BUF_PERSIST: 1544 return internal_buffer_count(inst, buffer_type); 1545 case BUF_SCRATCH_1: 1546 case BUF_SCRATCH_2: 1547 case BUF_VPSS: 1548 case BUF_ARP: 1549 return 1; /* internal buffer count needed by firmware is 1 */ 1550 case BUF_DPB: 1551 return iris_vpu_dpb_count(inst); 1552 default: 1553 return 0; 1554 } 1555 } 1556