1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/devfreq.h> 8 #include <linux/interconnect.h> 9 #include <linux/pm_domain.h> 10 #include <linux/pm_opp.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/reset.h> 13 14 #include "iris_core.h" 15 #include "iris_resources.h" 16 17 #define BW_THRESHOLD 50000 18 19 int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw) 20 { 21 unsigned long bw_kbps = 0, bw_prev = 0; 22 const struct icc_info *icc_tbl; 23 int ret = 0, i; 24 25 icc_tbl = core->iris_platform_data->icc_tbl; 26 27 for (i = 0; i < core->icc_count; i++) { 28 if (!strcmp(core->icc_tbl[i].name, "video-mem")) { 29 bw_kbps = icc_bw; 30 bw_prev = core->power.icc_bw; 31 32 bw_kbps = clamp_t(typeof(bw_kbps), bw_kbps, 33 icc_tbl[i].bw_min_kbps, icc_tbl[i].bw_max_kbps); 34 35 if (abs(bw_kbps - bw_prev) < BW_THRESHOLD && bw_prev) 36 return ret; 37 38 core->icc_tbl[i].avg_bw = bw_kbps; 39 40 core->power.icc_bw = bw_kbps; 41 break; 42 } 43 } 44 45 return icc_bulk_set_bw(core->icc_count, core->icc_tbl); 46 } 47 48 int iris_unset_icc_bw(struct iris_core *core) 49 { 50 u32 i; 51 52 core->power.icc_bw = 0; 53 54 for (i = 0; i < core->icc_count; i++) { 55 core->icc_tbl[i].avg_bw = 0; 56 core->icc_tbl[i].peak_bw = 0; 57 } 58 59 return icc_bulk_set_bw(core->icc_count, core->icc_tbl); 60 } 61 62 int iris_opp_set_rate(struct device *dev, unsigned long freq) 63 { 64 struct dev_pm_opp *opp __free(put_opp) = 65 devfreq_recommended_opp(dev, &freq, 0); 66 67 if (IS_ERR(opp)) 68 return PTR_ERR(opp); 69 70 return dev_pm_opp_set_opp(dev, opp); 71 } 72 73 int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev) 74 { 75 int ret; 76 77 ret = iris_opp_set_rate(core->dev, ULONG_MAX); 78 if (ret) 79 return ret; 80 81 return pm_runtime_resume_and_get(pd_dev); 82 } 83 84 int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev) 85 { 86 int ret; 87 int pm_ret; 88 89 ret = iris_opp_set_rate(core->dev, 0); 90 91 pm_ret = pm_runtime_put_sync(pd_dev); 92 if (!ret) 93 ret = pm_ret; 94 95 return ret; 96 } 97 98 static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platform_clk_type clk_type) 99 { 100 const struct platform_clk_data *clk_tbl; 101 u32 clk_cnt, i, j; 102 103 clk_tbl = core->iris_platform_data->clk_tbl; 104 clk_cnt = core->iris_platform_data->clk_tbl_size; 105 106 for (i = 0; i < clk_cnt; i++) { 107 if (clk_tbl[i].clk_type == clk_type) { 108 for (j = 0; core->clock_tbl && j < core->clk_count; j++) { 109 if (!strcmp(core->clock_tbl[j].id, clk_tbl[i].clk_name)) 110 return core->clock_tbl[j].clk; 111 } 112 } 113 } 114 115 return NULL; 116 } 117 118 int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type) 119 { 120 struct clk *clock; 121 122 clock = iris_get_clk_by_type(core, clk_type); 123 if (!clock) 124 return -ENOENT; 125 126 return clk_prepare_enable(clock); 127 } 128 129 int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type) 130 { 131 struct clk *clock; 132 133 clock = iris_get_clk_by_type(core, clk_type); 134 if (!clock) 135 return -EINVAL; 136 137 clk_disable_unprepare(clock); 138 139 return 0; 140 } 141