1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/interconnect.h> 8 #include <linux/module.h> 9 #include <linux/pm_domain.h> 10 #include <linux/pm_opp.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/reset.h> 13 #include <linux/soc/qcom/ubwc.h> 14 15 #include "iris_core.h" 16 #include "iris_ctrls.h" 17 #include "iris_vidc.h" 18 19 static int iris_init_icc(struct iris_core *core) 20 { 21 const struct icc_info *icc_tbl; 22 u32 i = 0; 23 24 icc_tbl = core->iris_platform_data->icc_tbl; 25 26 core->icc_count = core->iris_platform_data->icc_tbl_size; 27 core->icc_tbl = devm_kzalloc(core->dev, 28 sizeof(struct icc_bulk_data) * core->icc_count, 29 GFP_KERNEL); 30 if (!core->icc_tbl) 31 return -ENOMEM; 32 33 for (i = 0; i < core->icc_count; i++) { 34 core->icc_tbl[i].name = icc_tbl[i].name; 35 core->icc_tbl[i].avg_bw = icc_tbl[i].bw_min_kbps; 36 core->icc_tbl[i].peak_bw = 0; 37 } 38 39 return devm_of_icc_bulk_get(core->dev, core->icc_count, core->icc_tbl); 40 } 41 42 static int iris_init_power_domains(struct iris_core *core) 43 { 44 int ret; 45 46 struct dev_pm_domain_attach_data iris_pd_data = { 47 .pd_names = core->iris_platform_data->pmdomain_tbl, 48 .num_pd_names = core->iris_platform_data->pmdomain_tbl_size, 49 .pd_flags = PD_FLAG_NO_DEV_LINK, 50 }; 51 52 struct dev_pm_domain_attach_data iris_opp_pd_data = { 53 .pd_names = core->iris_platform_data->opp_pd_tbl, 54 .num_pd_names = core->iris_platform_data->opp_pd_tbl_size, 55 .pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP, 56 }; 57 58 struct dev_pm_opp_config iris_opp_clk_data = { 59 .clk_names = core->iris_platform_data->opp_clk_tbl, 60 .config_clks = dev_pm_opp_config_clks_simple, 61 }; 62 63 ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl); 64 if (ret < 0) 65 return ret; 66 67 ret = devm_pm_domain_attach_list(core->dev, &iris_opp_pd_data, &core->opp_pmdomain_tbl); 68 /* backwards compatibility for incomplete ABI SM8250 */ 69 if (ret == -ENODEV && 70 of_device_is_compatible(core->dev->of_node, "qcom,sm8250-venus")) { 71 iris_opp_pd_data.num_pd_names--; 72 ret = devm_pm_domain_attach_list(core->dev, &iris_opp_pd_data, 73 &core->opp_pmdomain_tbl); 74 } 75 if (ret < 0) 76 return ret; 77 78 ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data); 79 if (ret) 80 return ret; 81 82 return devm_pm_opp_of_add_table(core->dev); 83 } 84 85 static int iris_init_clocks(struct iris_core *core) 86 { 87 int ret; 88 89 ret = devm_clk_bulk_get_all(core->dev, &core->clock_tbl); 90 if (ret < 0) 91 return ret; 92 93 core->clk_count = ret; 94 95 return 0; 96 } 97 98 static int iris_init_reset_table(struct iris_core *core, 99 struct reset_control_bulk_data **resets, 100 const char * const *rst_tbl, u32 rst_tbl_size) 101 { 102 u32 i = 0; 103 104 *resets = devm_kzalloc(core->dev, 105 sizeof(struct reset_control_bulk_data) * rst_tbl_size, 106 GFP_KERNEL); 107 if (!*resets) 108 return -ENOMEM; 109 110 for (i = 0; i < rst_tbl_size; i++) 111 (*resets)[i].id = rst_tbl[i]; 112 113 return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *resets); 114 } 115 116 static int iris_init_resets(struct iris_core *core) 117 { 118 int ret; 119 120 ret = iris_init_reset_table(core, &core->resets, 121 core->iris_platform_data->clk_rst_tbl, 122 core->iris_platform_data->clk_rst_tbl_size); 123 if (ret) 124 return ret; 125 126 if (!core->iris_platform_data->controller_rst_tbl_size) 127 return 0; 128 129 return iris_init_reset_table(core, &core->controller_resets, 130 core->iris_platform_data->controller_rst_tbl, 131 core->iris_platform_data->controller_rst_tbl_size); 132 } 133 134 static int iris_init_resources(struct iris_core *core) 135 { 136 int ret; 137 138 ret = iris_init_icc(core); 139 if (ret) 140 return ret; 141 142 ret = iris_init_power_domains(core); 143 if (ret) 144 return ret; 145 146 ret = iris_init_clocks(core); 147 if (ret) 148 return ret; 149 150 return iris_init_resets(core); 151 } 152 153 static int iris_register_video_device(struct iris_core *core, enum domain_type type) 154 { 155 struct video_device *vdev; 156 int ret; 157 158 vdev = video_device_alloc(); 159 if (!vdev) 160 return -ENOMEM; 161 162 vdev->release = video_device_release; 163 vdev->fops = core->iris_v4l2_file_ops; 164 vdev->vfl_dir = VFL_DIR_M2M; 165 vdev->v4l2_dev = &core->v4l2_dev; 166 vdev->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; 167 168 if (type == DECODER) { 169 strscpy(vdev->name, "qcom-iris-decoder", sizeof(vdev->name)); 170 vdev->ioctl_ops = core->iris_v4l2_ioctl_ops_dec; 171 core->vdev_dec = vdev; 172 } else if (type == ENCODER) { 173 strscpy(vdev->name, "qcom-iris-encoder", sizeof(vdev->name)); 174 vdev->ioctl_ops = core->iris_v4l2_ioctl_ops_enc; 175 core->vdev_enc = vdev; 176 } else { 177 ret = -EINVAL; 178 goto err_vdev_release; 179 } 180 181 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 182 if (ret) 183 goto err_vdev_release; 184 185 video_set_drvdata(vdev, core); 186 187 return 0; 188 189 err_vdev_release: 190 video_device_release(vdev); 191 192 return ret; 193 } 194 195 static void iris_remove(struct platform_device *pdev) 196 { 197 struct iris_core *core; 198 199 core = platform_get_drvdata(pdev); 200 if (!core) 201 return; 202 203 iris_core_deinit(core); 204 205 video_unregister_device(core->vdev_dec); 206 video_unregister_device(core->vdev_enc); 207 208 v4l2_device_unregister(&core->v4l2_dev); 209 210 mutex_destroy(&core->lock); 211 } 212 213 static void iris_sys_error_handler(struct work_struct *work) 214 { 215 struct iris_core *core = 216 container_of(work, struct iris_core, sys_error_handler.work); 217 218 iris_core_deinit(core); 219 iris_core_init(core); 220 } 221 222 static int iris_probe(struct platform_device *pdev) 223 { 224 struct device *dev = &pdev->dev; 225 struct iris_core *core; 226 u64 dma_mask; 227 int ret; 228 229 core = devm_kzalloc(&pdev->dev, sizeof(*core), GFP_KERNEL); 230 if (!core) 231 return -ENOMEM; 232 core->dev = dev; 233 234 core->state = IRIS_CORE_DEINIT; 235 mutex_init(&core->lock); 236 init_completion(&core->core_init_done); 237 238 core->response_packet = devm_kzalloc(core->dev, IFACEQ_CORE_PKT_SIZE, GFP_KERNEL); 239 if (!core->response_packet) 240 return -ENOMEM; 241 242 INIT_LIST_HEAD(&core->instances); 243 INIT_DELAYED_WORK(&core->sys_error_handler, iris_sys_error_handler); 244 245 core->reg_base = devm_platform_ioremap_resource(pdev, 0); 246 if (IS_ERR(core->reg_base)) 247 return PTR_ERR(core->reg_base); 248 249 core->irq = platform_get_irq(pdev, 0); 250 if (core->irq < 0) 251 return core->irq; 252 253 core->iris_platform_data = of_device_get_match_data(core->dev); 254 255 core->ubwc_cfg = qcom_ubwc_config_get_data(); 256 if (IS_ERR(core->ubwc_cfg)) 257 return PTR_ERR(core->ubwc_cfg); 258 259 ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr, 260 iris_hfi_isr_handler, 261 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 262 "iris", core); 263 if (ret) 264 return ret; 265 266 iris_init_ops(core); 267 268 ret = iris_init_resources(core); 269 if (ret) 270 return ret; 271 272 ret = v4l2_device_register(dev, &core->v4l2_dev); 273 if (ret) 274 return ret; 275 276 ret = iris_register_video_device(core, DECODER); 277 if (ret) 278 goto err_v4l2_unreg; 279 280 ret = iris_register_video_device(core, ENCODER); 281 if (ret) 282 goto err_vdev_unreg_dec; 283 284 platform_set_drvdata(pdev, core); 285 286 dma_mask = core->iris_platform_data->dma_mask; 287 288 ret = dma_set_mask_and_coherent(dev, dma_mask); 289 if (ret) 290 goto err_vdev_unreg_enc; 291 292 dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); 293 dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); 294 295 pm_runtime_set_autosuspend_delay(core->dev, AUTOSUSPEND_DELAY_VALUE); 296 pm_runtime_use_autosuspend(core->dev); 297 ret = devm_pm_runtime_enable(core->dev); 298 if (ret) 299 goto err_vdev_unreg_enc; 300 301 return 0; 302 303 err_vdev_unreg_enc: 304 video_unregister_device(core->vdev_enc); 305 err_vdev_unreg_dec: 306 video_unregister_device(core->vdev_dec); 307 err_v4l2_unreg: 308 v4l2_device_unregister(&core->v4l2_dev); 309 310 return ret; 311 } 312 313 static int __maybe_unused iris_pm_suspend(struct device *dev) 314 { 315 struct iris_core *core; 316 int ret = 0; 317 318 core = dev_get_drvdata(dev); 319 320 mutex_lock(&core->lock); 321 if (core->state != IRIS_CORE_INIT) 322 goto exit; 323 324 ret = iris_hfi_pm_suspend(core); 325 326 exit: 327 mutex_unlock(&core->lock); 328 329 return ret; 330 } 331 332 static int __maybe_unused iris_pm_resume(struct device *dev) 333 { 334 struct iris_core *core; 335 int ret = 0; 336 337 core = dev_get_drvdata(dev); 338 339 mutex_lock(&core->lock); 340 if (core->state != IRIS_CORE_INIT) 341 goto exit; 342 343 ret = iris_hfi_pm_resume(core); 344 pm_runtime_mark_last_busy(core->dev); 345 346 exit: 347 mutex_unlock(&core->lock); 348 349 return ret; 350 } 351 352 static const struct dev_pm_ops iris_pm_ops = { 353 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 354 pm_runtime_force_resume) 355 SET_RUNTIME_PM_OPS(iris_pm_suspend, iris_pm_resume, NULL) 356 }; 357 358 static const struct of_device_id iris_dt_match[] = { 359 { 360 .compatible = "qcom,milos-iris", 361 .data = &milos_data, 362 }, 363 { 364 .compatible = "qcom,qcs8300-iris", 365 .data = &qcs8300_data, 366 }, 367 { 368 .compatible = "qcom,sc7280-venus", 369 .data = &sc7280_data, 370 }, 371 { 372 .compatible = "qcom,sm8250-venus", 373 .data = &sm8250_data, 374 }, 375 { 376 .compatible = "qcom,sm8550-iris", 377 .data = &sm8550_data, 378 }, 379 { 380 .compatible = "qcom,sm8650-iris", 381 .data = &sm8650_data, 382 }, 383 { 384 .compatible = "qcom,sm8750-iris", 385 .data = &sm8750_data, 386 }, 387 { 388 .compatible = "qcom,x1p42100-iris", 389 .data = &x1p42100_data, 390 }, 391 { }, 392 }; 393 MODULE_DEVICE_TABLE(of, iris_dt_match); 394 395 static struct platform_driver qcom_iris_driver = { 396 .probe = iris_probe, 397 .remove = iris_remove, 398 .driver = { 399 .name = "qcom-iris", 400 .of_match_table = iris_dt_match, 401 .pm = &iris_pm_ops, 402 }, 403 }; 404 405 module_platform_driver(qcom_iris_driver); 406 MODULE_DESCRIPTION("Qualcomm iris video driver"); 407 MODULE_LICENSE("GPL"); 408