1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: 102 return PROFILE_AV1; 103 case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: 104 return LEVEL_AV1; 105 case V4L2_CID_ROTATE: 106 return ROTATION; 107 case V4L2_CID_HFLIP: 108 return HFLIP; 109 case V4L2_CID_VFLIP: 110 return VFLIP; 111 case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: 112 return IR_TYPE; 113 case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD: 114 return IR_PERIOD; 115 case V4L2_CID_MPEG_VIDEO_LTR_COUNT: 116 return LTR_COUNT; 117 case V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES: 118 return USE_LTR; 119 case V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX: 120 return MARK_LTR; 121 case V4L2_CID_MPEG_VIDEO_B_FRAMES: 122 return B_FRAME; 123 case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING: 124 return LAYER_ENABLE; 125 case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE: 126 return LAYER_TYPE_H264; 127 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE: 128 return LAYER_TYPE_HEVC; 129 case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER: 130 return LAYER_COUNT_H264; 131 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER: 132 return LAYER_COUNT_HEVC; 133 case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR: 134 return LAYER0_BITRATE_H264; 135 case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR: 136 return LAYER1_BITRATE_H264; 137 case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR: 138 return LAYER2_BITRATE_H264; 139 case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR: 140 return LAYER3_BITRATE_H264; 141 case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR: 142 return LAYER4_BITRATE_H264; 143 case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR: 144 return LAYER5_BITRATE_H264; 145 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR: 146 return LAYER0_BITRATE_HEVC; 147 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR: 148 return LAYER1_BITRATE_HEVC; 149 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR: 150 return LAYER2_BITRATE_HEVC; 151 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR: 152 return LAYER3_BITRATE_HEVC; 153 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR: 154 return LAYER4_BITRATE_HEVC; 155 case V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR: 156 return LAYER5_BITRATE_HEVC; 157 default: 158 return INST_FW_CAP_MAX; 159 } 160 } 161 162 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 163 { 164 if (!iris_valid_cap_id(cap_id)) 165 return 0; 166 167 switch (cap_id) { 168 case PROFILE_H264: 169 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 170 case PROFILE_HEVC: 171 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 172 case PROFILE_VP9: 173 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 174 case LEVEL_H264: 175 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 176 case LEVEL_HEVC: 177 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 178 case LEVEL_VP9: 179 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 180 case TIER: 181 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 182 case HEADER_MODE: 183 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 184 case PREPEND_SPSPPS_TO_IDR: 185 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 186 case BITRATE: 187 return V4L2_CID_MPEG_VIDEO_BITRATE; 188 case BITRATE_PEAK: 189 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 190 case BITRATE_MODE: 191 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 192 case FRAME_SKIP_MODE: 193 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 194 case FRAME_RC_ENABLE: 195 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 196 case GOP_SIZE: 197 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 198 case ENTROPY_MODE: 199 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 200 case MIN_FRAME_QP_H264: 201 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 202 case MIN_FRAME_QP_HEVC: 203 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 204 case MAX_FRAME_QP_H264: 205 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 206 case MAX_FRAME_QP_HEVC: 207 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 208 case I_FRAME_MIN_QP_H264: 209 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 210 case I_FRAME_MIN_QP_HEVC: 211 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 212 case P_FRAME_MIN_QP_H264: 213 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 214 case P_FRAME_MIN_QP_HEVC: 215 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 216 case B_FRAME_MIN_QP_H264: 217 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 218 case B_FRAME_MIN_QP_HEVC: 219 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 220 case I_FRAME_MAX_QP_H264: 221 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 222 case I_FRAME_MAX_QP_HEVC: 223 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 224 case P_FRAME_MAX_QP_H264: 225 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 226 case P_FRAME_MAX_QP_HEVC: 227 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 228 case B_FRAME_MAX_QP_H264: 229 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 230 case B_FRAME_MAX_QP_HEVC: 231 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 232 case I_FRAME_QP_H264: 233 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 234 case I_FRAME_QP_HEVC: 235 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 236 case P_FRAME_QP_H264: 237 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 238 case P_FRAME_QP_HEVC: 239 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 240 case B_FRAME_QP_H264: 241 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 242 case B_FRAME_QP_HEVC: 243 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 244 case PROFILE_AV1: 245 return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; 246 case LEVEL_AV1: 247 return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; 248 case ROTATION: 249 return V4L2_CID_ROTATE; 250 case HFLIP: 251 return V4L2_CID_HFLIP; 252 case VFLIP: 253 return V4L2_CID_VFLIP; 254 case IR_TYPE: 255 return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE; 256 case IR_PERIOD: 257 return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD; 258 case LTR_COUNT: 259 return V4L2_CID_MPEG_VIDEO_LTR_COUNT; 260 case USE_LTR: 261 return V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES; 262 case MARK_LTR: 263 return V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX; 264 case B_FRAME: 265 return V4L2_CID_MPEG_VIDEO_B_FRAMES; 266 case LAYER_ENABLE: 267 return V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING; 268 case LAYER_TYPE_H264: 269 return V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE; 270 case LAYER_TYPE_HEVC: 271 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE; 272 case LAYER_COUNT_H264: 273 return V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER; 274 case LAYER_COUNT_HEVC: 275 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER; 276 case LAYER0_BITRATE_H264: 277 return V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR; 278 case LAYER1_BITRATE_H264: 279 return V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR; 280 case LAYER2_BITRATE_H264: 281 return V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR; 282 case LAYER3_BITRATE_H264: 283 return V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR; 284 case LAYER4_BITRATE_H264: 285 return V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR; 286 case LAYER5_BITRATE_H264: 287 return V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR; 288 case LAYER0_BITRATE_HEVC: 289 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR; 290 case LAYER1_BITRATE_HEVC: 291 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR; 292 case LAYER2_BITRATE_HEVC: 293 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR; 294 case LAYER3_BITRATE_HEVC: 295 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR; 296 case LAYER4_BITRATE_HEVC: 297 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR; 298 case LAYER5_BITRATE_HEVC: 299 return V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR; 300 default: 301 return 0; 302 } 303 } 304 305 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 306 { 307 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 308 enum platform_inst_fw_cap_type cap_id; 309 struct platform_inst_fw_cap *cap; 310 struct vb2_queue *q; 311 312 cap = &inst->fw_caps[0]; 313 cap_id = iris_get_cap_id(ctrl->id); 314 if (!iris_valid_cap_id(cap_id)) 315 return -EINVAL; 316 317 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 318 if (vb2_is_streaming(q) && 319 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 320 return -EINVAL; 321 322 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 323 324 inst->fw_caps[cap_id].value = ctrl->val; 325 326 if (vb2_is_streaming(q)) { 327 if (cap[cap_id].set) 328 cap[cap_id].set(inst, cap_id); 329 } 330 331 return 0; 332 } 333 334 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 335 .s_ctrl = iris_op_s_ctrl, 336 }; 337 338 int iris_ctrls_init(struct iris_inst *inst) 339 { 340 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 341 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 342 u32 v4l2_id; 343 int ret; 344 345 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 346 if (iris_get_v4l2_id(cap[idx].cap_id)) 347 num_ctrls++; 348 } 349 350 /* Adding 1 to num_ctrls to include 351 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 352 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 353 */ 354 355 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 356 if (ret) 357 return ret; 358 359 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 360 struct v4l2_ctrl *ctrl; 361 362 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 363 if (!v4l2_id) 364 continue; 365 366 if (ctrl_idx >= num_ctrls) { 367 ret = -EINVAL; 368 goto error; 369 } 370 371 if (cap[idx].flags & CAP_FLAG_MENU) { 372 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 373 &iris_ctrl_ops, 374 v4l2_id, 375 cap[idx].max, 376 ~(cap[idx].step_or_mask), 377 cap[idx].value); 378 } else { 379 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 380 &iris_ctrl_ops, 381 v4l2_id, 382 cap[idx].min, 383 cap[idx].max, 384 cap[idx].step_or_mask, 385 cap[idx].value); 386 } 387 if (!ctrl) { 388 ret = -EINVAL; 389 goto error; 390 } 391 392 ctrl_idx++; 393 } 394 395 if (inst->domain == DECODER) { 396 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 397 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 398 } else { 399 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 400 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 401 } 402 403 ret = inst->ctrl_handler.error; 404 if (ret) 405 goto error; 406 407 return 0; 408 error: 409 v4l2_ctrl_handler_free(&inst->ctrl_handler); 410 411 return ret; 412 } 413 414 void iris_session_init_caps(struct iris_core *core) 415 { 416 const struct platform_inst_fw_cap *caps; 417 u32 i, num_cap, cap_id; 418 419 caps = core->iris_firmware_data->inst_fw_caps_dec; 420 num_cap = core->iris_firmware_data->inst_fw_caps_dec_size; 421 422 for (i = 0; i < num_cap; i++) { 423 cap_id = caps[i].cap_id; 424 if (!iris_valid_cap_id(cap_id)) 425 continue; 426 427 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 428 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 429 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 430 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 431 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 432 433 if (cap_id == PIPE) { 434 core->inst_fw_caps_dec[cap_id].value = 435 core->iris_platform_data->num_vpp_pipe; 436 core->inst_fw_caps_dec[cap_id].min = 437 core->iris_platform_data->num_vpp_pipe; 438 core->inst_fw_caps_dec[cap_id].max = 439 core->iris_platform_data->num_vpp_pipe; 440 } else { 441 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 442 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 443 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 444 } 445 } 446 447 caps = core->iris_firmware_data->inst_fw_caps_enc; 448 num_cap = core->iris_firmware_data->inst_fw_caps_enc_size; 449 450 for (i = 0; i < num_cap; i++) { 451 cap_id = caps[i].cap_id; 452 if (!iris_valid_cap_id(cap_id)) 453 continue; 454 455 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 456 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 457 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 458 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 459 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 460 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 461 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 462 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 463 } 464 } 465 466 static u32 iris_get_port_info(struct iris_inst *inst, 467 enum platform_inst_fw_cap_type cap_id) 468 { 469 if (inst->domain == DECODER) { 470 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 471 return HFI_PORT_BITSTREAM; 472 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 473 return HFI_PORT_RAW; 474 } else { 475 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 476 return HFI_PORT_RAW; 477 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 478 return HFI_PORT_BITSTREAM; 479 } 480 481 return HFI_PORT_NONE; 482 } 483 484 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 485 { 486 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 487 u32 hfi_value = inst->fw_caps[cap_id].value; 488 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 489 490 return hfi_ops->session_set_property(inst, hfi_id, 491 HFI_HOST_FLAGS_NONE, 492 iris_get_port_info(inst, cap_id), 493 HFI_PAYLOAD_U32_ENUM, 494 &hfi_value, sizeof(u32)); 495 } 496 497 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 498 { 499 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 500 u32 hfi_value = inst->fw_caps[cap_id].value; 501 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 502 503 return hfi_ops->session_set_property(inst, hfi_id, 504 HFI_HOST_FLAGS_NONE, 505 iris_get_port_info(inst, cap_id), 506 HFI_PAYLOAD_U32, 507 &hfi_value, sizeof(u32)); 508 } 509 510 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 511 { 512 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 513 struct v4l2_format *inp_f = inst->fmt_src; 514 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 515 u32 height = inp_f->fmt.pix_mp.height; 516 u32 width = inp_f->fmt.pix_mp.width; 517 u32 work_mode = STAGE_2; 518 519 if (inst->domain == DECODER) { 520 if (iris_res_is_less_than(width, height, 1280, 720)) 521 work_mode = STAGE_1; 522 } 523 524 return hfi_ops->session_set_property(inst, hfi_id, 525 HFI_HOST_FLAGS_NONE, 526 iris_get_port_info(inst, cap_id), 527 HFI_PAYLOAD_U32, 528 &work_mode, sizeof(u32)); 529 } 530 531 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 532 { 533 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 534 u32 work_route = inst->fw_caps[PIPE].value; 535 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 536 537 return hfi_ops->session_set_property(inst, hfi_id, 538 HFI_HOST_FLAGS_NONE, 539 iris_get_port_info(inst, cap_id), 540 HFI_PAYLOAD_U32, 541 &work_route, sizeof(u32)); 542 } 543 544 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 545 { 546 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 547 u32 hfi_id, hfi_value; 548 549 if (inst->codec == V4L2_PIX_FMT_H264) { 550 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 551 hfi_value = inst->fw_caps[PROFILE_H264].value; 552 } else { 553 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 554 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 555 } 556 557 return hfi_ops->session_set_property(inst, hfi_id, 558 HFI_HOST_FLAGS_NONE, 559 iris_get_port_info(inst, cap_id), 560 HFI_PAYLOAD_U32_ENUM, 561 &hfi_value, sizeof(u32)); 562 } 563 564 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 565 { 566 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 567 u32 hfi_id, hfi_value; 568 569 if (inst->codec == V4L2_PIX_FMT_H264) { 570 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 571 hfi_value = inst->fw_caps[LEVEL_H264].value; 572 } else { 573 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 574 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 575 } 576 577 return hfi_ops->session_set_property(inst, hfi_id, 578 HFI_HOST_FLAGS_NONE, 579 iris_get_port_info(inst, cap_id), 580 HFI_PAYLOAD_U32_ENUM, 581 &hfi_value, sizeof(u32)); 582 } 583 584 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 585 { 586 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 587 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 588 struct hfi_profile_level pl; 589 590 if (inst->codec == V4L2_PIX_FMT_H264) { 591 pl.profile = inst->fw_caps[PROFILE_H264].value; 592 pl.level = inst->fw_caps[LEVEL_H264].value; 593 } else { 594 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 595 pl.level = inst->fw_caps[LEVEL_HEVC].value; 596 } 597 598 return hfi_ops->session_set_property(inst, hfi_id, 599 HFI_HOST_FLAGS_NONE, 600 iris_get_port_info(inst, cap_id), 601 HFI_PAYLOAD_U32_ENUM, 602 &pl, sizeof(u32)); 603 } 604 605 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 606 { 607 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 608 u32 header_mode = inst->fw_caps[cap_id].value; 609 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 610 u32 hfi_val; 611 612 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 613 hfi_val = 0; 614 else 615 hfi_val = 1; 616 617 return hfi_ops->session_set_property(inst, hfi_id, 618 HFI_HOST_FLAGS_NONE, 619 iris_get_port_info(inst, cap_id), 620 HFI_PAYLOAD_U32, 621 &hfi_val, sizeof(u32)); 622 } 623 624 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 625 { 626 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 627 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 628 u32 header_mode = inst->fw_caps[cap_id].value; 629 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 630 u32 hfi_val; 631 632 if (prepend_sps_pps) 633 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 634 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 635 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 636 else 637 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 638 639 return hfi_ops->session_set_property(inst, hfi_id, 640 HFI_HOST_FLAGS_NONE, 641 iris_get_port_info(inst, cap_id), 642 HFI_PAYLOAD_U32_ENUM, 643 &hfi_val, sizeof(u32)); 644 } 645 646 int iris_set_bitrate_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 647 { 648 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 649 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 650 u32 bitrate = inst->fw_caps[cap_id].value; 651 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 652 struct hfi_bitrate hfi_val; 653 u32 max_bitrate; 654 655 if (!(inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) && cap_id != BITRATE) 656 return -EINVAL; 657 658 if (inst->codec == V4L2_PIX_FMT_HEVC) { 659 max_bitrate = CABAC_MAX_BITRATE; 660 } else { 661 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 662 max_bitrate = CABAC_MAX_BITRATE; 663 else 664 max_bitrate = CAVLC_MAX_BITRATE; 665 } 666 667 hfi_val.bitrate = min(bitrate, max_bitrate); 668 669 switch (cap_id) { 670 case BITRATE: 671 case LAYER0_BITRATE_H264: 672 hfi_val.layer_id = 0; 673 break; 674 case LAYER1_BITRATE_H264: 675 hfi_val.layer_id = 1; 676 break; 677 case LAYER2_BITRATE_H264: 678 hfi_val.layer_id = 2; 679 break; 680 case LAYER3_BITRATE_H264: 681 hfi_val.layer_id = 3; 682 break; 683 case LAYER4_BITRATE_H264: 684 hfi_val.layer_id = 4; 685 break; 686 case LAYER5_BITRATE_H264: 687 hfi_val.layer_id = 5; 688 break; 689 default: 690 return -EINVAL; 691 } 692 693 if (hfi_val.layer_id > 0 && !inst->fw_caps[LAYER_ENABLE].value) 694 return -EINVAL; 695 696 return hfi_ops->session_set_property(inst, hfi_id, 697 HFI_HOST_FLAGS_NONE, 698 iris_get_port_info(inst, cap_id), 699 HFI_PAYLOAD_STRUCTURE, 700 &hfi_val, sizeof(hfi_val)); 701 } 702 703 int iris_set_bitrate_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 704 { 705 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 706 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 707 u32 bitrate = inst->fw_caps[cap_id].value; 708 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 709 u32 max_bitrate; 710 711 if (inst->codec == V4L2_PIX_FMT_HEVC) 712 max_bitrate = CABAC_MAX_BITRATE; 713 714 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 715 max_bitrate = CABAC_MAX_BITRATE; 716 else 717 max_bitrate = CAVLC_MAX_BITRATE; 718 719 bitrate = min(bitrate, max_bitrate); 720 721 return hfi_ops->session_set_property(inst, hfi_id, 722 HFI_HOST_FLAGS_NONE, 723 iris_get_port_info(inst, cap_id), 724 HFI_PAYLOAD_U32, 725 &bitrate, sizeof(u32)); 726 } 727 728 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 729 { 730 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 731 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 732 u32 peak_bitrate = inst->fw_caps[cap_id].value; 733 u32 bitrate = inst->fw_caps[BITRATE].value; 734 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 735 736 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 737 return 0; 738 739 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 740 if (peak_bitrate < bitrate) 741 peak_bitrate = bitrate; 742 } else { 743 peak_bitrate = bitrate; 744 } 745 746 inst->fw_caps[cap_id].value = peak_bitrate; 747 748 return hfi_ops->session_set_property(inst, hfi_id, 749 HFI_HOST_FLAGS_NONE, 750 iris_get_port_info(inst, cap_id), 751 HFI_PAYLOAD_U32, 752 &peak_bitrate, sizeof(u32)); 753 } 754 755 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 756 { 757 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 758 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 759 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 760 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 761 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 762 u32 rc_mode = 0; 763 764 if (!frame_rc) 765 rc_mode = HFI_RATE_CONTROL_OFF; 766 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 767 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 768 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 769 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 770 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 771 rc_mode = HFI_RATE_CONTROL_CQ; 772 773 inst->hfi_rc_type = rc_mode; 774 775 return hfi_ops->session_set_property(inst, hfi_id, 776 HFI_HOST_FLAGS_NONE, 777 iris_get_port_info(inst, cap_id), 778 HFI_PAYLOAD_U32_ENUM, 779 &rc_mode, sizeof(u32)); 780 } 781 782 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 783 { 784 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 785 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 786 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 787 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 788 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 789 u32 rc_mode = 0; 790 791 if (!frame_rc) 792 rc_mode = HFI_RC_OFF; 793 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 794 rc_mode = HFI_RC_VBR_CFR; 795 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 796 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 797 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 798 rc_mode = HFI_RC_CQ; 799 800 inst->hfi_rc_type = rc_mode; 801 802 return hfi_ops->session_set_property(inst, hfi_id, 803 HFI_HOST_FLAGS_NONE, 804 iris_get_port_info(inst, cap_id), 805 HFI_PAYLOAD_U32_ENUM, 806 &rc_mode, sizeof(u32)); 807 } 808 809 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 810 { 811 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 812 u32 entropy_mode = inst->fw_caps[cap_id].value; 813 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 814 u32 hfi_val; 815 816 if (inst->codec != V4L2_PIX_FMT_H264) 817 return 0; 818 819 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 820 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 821 822 return hfi_ops->session_set_property(inst, hfi_id, 823 HFI_HOST_FLAGS_NONE, 824 iris_get_port_info(inst, cap_id), 825 HFI_PAYLOAD_U32, 826 &hfi_val, sizeof(u32)); 827 } 828 829 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 830 { 831 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 832 u32 entropy_mode = inst->fw_caps[cap_id].value; 833 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 834 u32 profile; 835 836 if (inst->codec != V4L2_PIX_FMT_H264) 837 return 0; 838 839 profile = inst->fw_caps[PROFILE_H264].value; 840 841 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 842 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 843 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 844 845 inst->fw_caps[cap_id].value = entropy_mode; 846 847 return hfi_ops->session_set_property(inst, hfi_id, 848 HFI_HOST_FLAGS_NONE, 849 iris_get_port_info(inst, cap_id), 850 HFI_PAYLOAD_U32, 851 &entropy_mode, sizeof(u32)); 852 } 853 854 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 855 { 856 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 857 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 858 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 859 u32 min_qp_enable = 0, client_qp_enable = 0; 860 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 861 u32 hfi_val; 862 863 if (inst->codec == V4L2_PIX_FMT_H264) { 864 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 865 min_qp_enable = 1; 866 if (min_qp_enable || 867 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 868 i_qp_enable = 1; 869 if (min_qp_enable || 870 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 871 p_qp_enable = 1; 872 if (min_qp_enable || 873 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 874 b_qp_enable = 1; 875 } else { 876 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 877 min_qp_enable = 1; 878 if (min_qp_enable || 879 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 880 i_qp_enable = 1; 881 if (min_qp_enable || 882 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 883 p_qp_enable = 1; 884 if (min_qp_enable || 885 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 886 b_qp_enable = 1; 887 } 888 889 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 890 if (!client_qp_enable) 891 return 0; 892 893 if (inst->codec == V4L2_PIX_FMT_H264) { 894 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 895 inst->fw_caps[MIN_FRAME_QP_H264].value); 896 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 897 inst->fw_caps[MIN_FRAME_QP_H264].value); 898 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 899 inst->fw_caps[MIN_FRAME_QP_H264].value); 900 } else { 901 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 902 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 903 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 904 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 905 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 906 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 907 } 908 909 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 910 911 return hfi_ops->session_set_property(inst, hfi_id, 912 HFI_HOST_FLAGS_NONE, 913 iris_get_port_info(inst, cap_id), 914 HFI_PAYLOAD_32_PACKED, 915 &hfi_val, sizeof(u32)); 916 } 917 918 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 919 { 920 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 921 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 922 u32 max_qp_enable = 0, client_qp_enable; 923 u32 i_frame_qp, p_frame_qp, b_frame_qp; 924 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 925 u32 hfi_val; 926 927 if (inst->codec == V4L2_PIX_FMT_H264) { 928 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 929 max_qp_enable = 1; 930 if (max_qp_enable || 931 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 932 i_qp_enable = 1; 933 if (max_qp_enable || 934 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 935 p_qp_enable = 1; 936 if (max_qp_enable || 937 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 938 b_qp_enable = 1; 939 } else { 940 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 941 max_qp_enable = 1; 942 if (max_qp_enable || 943 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 944 i_qp_enable = 1; 945 if (max_qp_enable || 946 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 947 p_qp_enable = 1; 948 if (max_qp_enable || 949 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 950 b_qp_enable = 1; 951 } 952 953 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 954 if (!client_qp_enable) 955 return 0; 956 957 if (inst->codec == V4L2_PIX_FMT_H264) { 958 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 959 inst->fw_caps[MAX_FRAME_QP_H264].value); 960 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 961 inst->fw_caps[MAX_FRAME_QP_H264].value); 962 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 963 inst->fw_caps[MAX_FRAME_QP_H264].value); 964 } else { 965 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 966 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 967 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 968 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 969 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 970 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 971 } 972 973 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 974 client_qp_enable << 24; 975 976 return hfi_ops->session_set_property(inst, hfi_id, 977 HFI_HOST_FLAGS_NONE, 978 iris_get_port_info(inst, cap_id), 979 HFI_PAYLOAD_32_PACKED, 980 &hfi_val, sizeof(u32)); 981 } 982 983 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 984 { 985 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 986 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 987 u32 i_frame_qp, p_frame_qp, b_frame_qp; 988 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 989 struct vb2_queue *q; 990 u32 hfi_val; 991 992 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 993 if (vb2_is_streaming(q)) { 994 if (inst->hfi_rc_type != HFI_RC_OFF) 995 return 0; 996 } 997 998 if (inst->hfi_rc_type == HFI_RC_OFF) { 999 i_qp_enable = 1; 1000 p_qp_enable = 1; 1001 b_qp_enable = 1; 1002 } else { 1003 if (inst->codec == V4L2_PIX_FMT_H264) { 1004 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 1005 i_qp_enable = 1; 1006 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 1007 p_qp_enable = 1; 1008 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 1009 b_qp_enable = 1; 1010 } else { 1011 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 1012 i_qp_enable = 1; 1013 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 1014 p_qp_enable = 1; 1015 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 1016 b_qp_enable = 1; 1017 } 1018 } 1019 1020 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 1021 if (!client_qp_enable) 1022 return 0; 1023 1024 if (inst->codec == V4L2_PIX_FMT_H264) { 1025 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 1026 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 1027 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 1028 } else { 1029 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 1030 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 1031 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 1032 } 1033 1034 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 1035 client_qp_enable << 24; 1036 1037 return hfi_ops->session_set_property(inst, hfi_id, 1038 HFI_HOST_FLAGS_NONE, 1039 iris_get_port_info(inst, cap_id), 1040 HFI_PAYLOAD_32_PACKED, 1041 &hfi_val, sizeof(u32)); 1042 } 1043 1044 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1045 { 1046 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1047 struct hfi_quantization_range_v2 range; 1048 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1049 1050 if (inst->codec == V4L2_PIX_FMT_HEVC) { 1051 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 1052 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 1053 } else { 1054 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 1055 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 1056 } 1057 1058 return hfi_ops->session_set_property(inst, hfi_id, 1059 HFI_HOST_FLAGS_NONE, 1060 iris_get_port_info(inst, cap_id), 1061 HFI_PAYLOAD_32_PACKED, 1062 &range, sizeof(range)); 1063 } 1064 1065 int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1066 { 1067 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1068 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1069 u32 hfi_val; 1070 1071 switch (inst->fw_caps[cap_id].value) { 1072 case 0: 1073 hfi_val = HFI_ROTATION_NONE; 1074 return 0; 1075 case 90: 1076 hfi_val = HFI_ROTATION_90; 1077 break; 1078 case 180: 1079 hfi_val = HFI_ROTATION_180; 1080 break; 1081 case 270: 1082 hfi_val = HFI_ROTATION_270; 1083 break; 1084 default: 1085 return -EINVAL; 1086 } 1087 1088 return hfi_ops->session_set_property(inst, hfi_id, 1089 HFI_HOST_FLAGS_NONE, 1090 iris_get_port_info(inst, cap_id), 1091 HFI_PAYLOAD_U32, 1092 &hfi_val, sizeof(u32)); 1093 } 1094 1095 int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1096 { 1097 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1098 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1099 u32 hfi_val = HFI_DISABLE_FLIP; 1100 1101 if (inst->fw_caps[HFLIP].value) 1102 hfi_val |= HFI_HORIZONTAL_FLIP; 1103 1104 if (inst->fw_caps[VFLIP].value) 1105 hfi_val |= HFI_VERTICAL_FLIP; 1106 1107 return hfi_ops->session_set_property(inst, hfi_id, 1108 HFI_HOST_FLAGS_NONE, 1109 iris_get_port_info(inst, cap_id), 1110 HFI_PAYLOAD_U32_ENUM, 1111 &hfi_val, sizeof(u32)); 1112 } 1113 1114 int iris_set_ir_period_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1115 { 1116 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1117 struct v4l2_pix_format_mplane *fmt = &inst->fmt_dst->fmt.pix_mp; 1118 u32 codec_align = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16; 1119 u32 ir_period = inst->fw_caps[cap_id].value; 1120 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1121 struct hfi_intra_refresh hfi_val; 1122 1123 if (!ir_period) 1124 return -EINVAL; 1125 1126 if (inst->fw_caps[IR_TYPE].value == 1127 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) { 1128 hfi_val.mode = HFI_INTRA_REFRESH_RANDOM; 1129 } else if (inst->fw_caps[IR_TYPE].value == 1130 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) { 1131 hfi_val.mode = HFI_INTRA_REFRESH_CYCLIC; 1132 } else { 1133 return -EINVAL; 1134 } 1135 1136 /* 1137 * Calculate the number of macroblocks in a frame, 1138 * then determine how many macroblocks need to be 1139 * refreshed within one ir_period. 1140 */ 1141 hfi_val.mbs = (fmt->width / codec_align) * (fmt->height / codec_align); 1142 hfi_val.mbs /= ir_period; 1143 1144 return hfi_ops->session_set_property(inst, hfi_id, 1145 HFI_HOST_FLAGS_NONE, 1146 iris_get_port_info(inst, cap_id), 1147 HFI_PAYLOAD_STRUCTURE, 1148 &hfi_val, sizeof(hfi_val)); 1149 } 1150 1151 int iris_set_ir_period_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1152 { 1153 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1154 struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 1155 u32 ir_period = inst->fw_caps[cap_id].value; 1156 u32 ir_type = 0; 1157 1158 if (inst->fw_caps[IR_TYPE].value == 1159 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) { 1160 if (vb2_is_streaming(q)) 1161 return 0; 1162 ir_type = HFI_PROP_IR_RANDOM_PERIOD; 1163 } else if (inst->fw_caps[IR_TYPE].value == 1164 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) { 1165 ir_type = HFI_PROP_IR_CYCLIC_PERIOD; 1166 } else { 1167 return -EINVAL; 1168 } 1169 1170 return hfi_ops->session_set_property(inst, ir_type, 1171 HFI_HOST_FLAGS_NONE, 1172 iris_get_port_info(inst, cap_id), 1173 HFI_PAYLOAD_U32, 1174 &ir_period, sizeof(u32)); 1175 } 1176 1177 int iris_set_ltr_count_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1178 { 1179 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1180 u32 ltr_count = inst->fw_caps[cap_id].value; 1181 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1182 struct hfi_ltr_mode ltr_mode; 1183 1184 if (!ltr_count) 1185 return -EINVAL; 1186 1187 ltr_mode.count = ltr_count; 1188 ltr_mode.mode = HFI_LTR_MODE_MANUAL; 1189 ltr_mode.trust_mode = 1; 1190 1191 return hfi_ops->session_set_property(inst, hfi_id, 1192 HFI_HOST_FLAGS_NONE, 1193 iris_get_port_info(inst, cap_id), 1194 HFI_PAYLOAD_STRUCTURE, 1195 <r_mode, sizeof(ltr_mode)); 1196 } 1197 1198 int iris_set_use_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1199 { 1200 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1201 struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx); 1202 struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 1203 u32 ltr_count = inst->fw_caps[LTR_COUNT].value; 1204 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1205 struct hfi_ltr_use ltr_use; 1206 1207 if (!vb2_is_streaming(sq) && !vb2_is_streaming(dq)) 1208 return -EINVAL; 1209 1210 if (!ltr_count) 1211 return -EINVAL; 1212 1213 ltr_use.ref_ltr = inst->fw_caps[cap_id].value; 1214 ltr_use.use_constrnt = true; 1215 ltr_use.frames = 0; 1216 1217 return hfi_ops->session_set_property(inst, hfi_id, 1218 HFI_HOST_FLAGS_NONE, 1219 iris_get_port_info(inst, cap_id), 1220 HFI_PAYLOAD_STRUCTURE, 1221 <r_use, sizeof(ltr_use)); 1222 } 1223 1224 int iris_set_mark_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1225 { 1226 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1227 struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx); 1228 struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 1229 u32 ltr_count = inst->fw_caps[LTR_COUNT].value; 1230 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1231 struct hfi_ltr_mark ltr_mark; 1232 1233 if (!vb2_is_streaming(sq) && !vb2_is_streaming(dq)) 1234 return -EINVAL; 1235 1236 if (!ltr_count) 1237 return -EINVAL; 1238 1239 ltr_mark.mark_frame = inst->fw_caps[cap_id].value; 1240 1241 return hfi_ops->session_set_property(inst, hfi_id, 1242 HFI_HOST_FLAGS_NONE, 1243 iris_get_port_info(inst, cap_id), 1244 HFI_PAYLOAD_STRUCTURE, 1245 <r_mark, sizeof(ltr_mark)); 1246 } 1247 1248 int iris_set_ltr_count_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1249 { 1250 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1251 u32 ltr_count = inst->fw_caps[cap_id].value; 1252 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1253 1254 if (!ltr_count) 1255 return -EINVAL; 1256 1257 if (inst->hfi_rc_type == HFI_RC_CBR_VFR || 1258 inst->hfi_rc_type == HFI_RC_CBR_CFR || 1259 inst->hfi_rc_type == HFI_RC_OFF) { 1260 inst->fw_caps[LTR_COUNT].value = 0; 1261 return -EINVAL; 1262 } 1263 1264 return hfi_ops->session_set_property(inst, hfi_id, 1265 HFI_HOST_FLAGS_NONE, 1266 iris_get_port_info(inst, cap_id), 1267 HFI_PAYLOAD_U32, 1268 <r_count, sizeof(u32)); 1269 } 1270 1271 int iris_set_use_and_mark_ltr(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1272 { 1273 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1274 struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx); 1275 struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 1276 u32 ltr_count = inst->fw_caps[LTR_COUNT].value; 1277 u32 hfi_val = inst->fw_caps[cap_id].value; 1278 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1279 1280 if (!vb2_is_streaming(sq) && !vb2_is_streaming(dq)) 1281 return -EINVAL; 1282 1283 if (!ltr_count || hfi_val == INVALID_DEFAULT_MARK_OR_USE_LTR) 1284 return -EINVAL; 1285 1286 return hfi_ops->session_set_property(inst, hfi_id, 1287 HFI_HOST_FLAGS_NONE, 1288 iris_get_port_info(inst, cap_id), 1289 HFI_PAYLOAD_U32, 1290 &hfi_val, sizeof(u32)); 1291 } 1292 1293 int iris_set_intra_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1294 { 1295 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1296 u32 gop_size = inst->fw_caps[GOP_SIZE].value; 1297 u32 b_frame = inst->fw_caps[B_FRAME].value; 1298 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1299 struct hfi_intra_period intra_period; 1300 1301 if (!gop_size || b_frame >= gop_size) 1302 return -EINVAL; 1303 1304 /* 1305 * intra_period represents the length of a GOP, which includes both P-frames 1306 * and B-frames. The counts of P-frames and B-frames within a GOP must be 1307 * communicated to the firmware. 1308 */ 1309 intra_period.pframes = (gop_size - 1) / (b_frame + 1); 1310 intra_period.bframes = b_frame; 1311 1312 return hfi_ops->session_set_property(inst, hfi_id, 1313 HFI_HOST_FLAGS_NONE, 1314 iris_get_port_info(inst, cap_id), 1315 HFI_PAYLOAD_STRUCTURE, 1316 &intra_period, sizeof(intra_period)); 1317 } 1318 1319 int iris_set_layer_type(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1320 { 1321 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1322 u32 layer_enable = inst->fw_caps[LAYER_ENABLE].value; 1323 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1324 u32 layer_type; 1325 1326 if (inst->hfi_rc_type == HFI_RATE_CONTROL_CQ || 1327 inst->hfi_rc_type == HFI_RATE_CONTROL_OFF) 1328 return -EINVAL; 1329 1330 if (inst->codec == V4L2_PIX_FMT_H264) { 1331 if (!layer_enable || !inst->fw_caps[LAYER_COUNT_H264].value) 1332 return -EINVAL; 1333 1334 if (inst->fw_caps[LAYER_TYPE_H264].value == 1335 V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P) { 1336 if (inst->hfi_rc_type == HFI_RC_VBR_CFR) 1337 layer_type = HFI_HIER_P_HYBRID_LTR; 1338 else 1339 layer_type = HFI_HIER_P_SLIDING_WINDOW; 1340 } else if (inst->fw_caps[LAYER_TYPE_H264].value == 1341 V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B) { 1342 if (inst->hfi_rc_type == HFI_RC_VBR_CFR) 1343 layer_type = HFI_HIER_B; 1344 else 1345 return -EINVAL; 1346 } else { 1347 return -EINVAL; 1348 } 1349 } else if (inst->codec == V4L2_PIX_FMT_HEVC) { 1350 if (!inst->fw_caps[LAYER_COUNT_HEVC].value) 1351 return -EINVAL; 1352 1353 if (inst->fw_caps[LAYER_TYPE_HEVC].value == 1354 V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P) { 1355 layer_type = HFI_HIER_P_SLIDING_WINDOW; 1356 } else if (inst->fw_caps[LAYER_TYPE_HEVC].value == 1357 V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) { 1358 if (inst->hfi_rc_type == HFI_RC_VBR_CFR) 1359 layer_type = HFI_HIER_B; 1360 else 1361 return -EINVAL; 1362 } else { 1363 return -EINVAL; 1364 } 1365 } else { 1366 return -EINVAL; 1367 } 1368 1369 inst->hfi_layer_type = layer_type; 1370 1371 return hfi_ops->session_set_property(inst, hfi_id, 1372 HFI_HOST_FLAGS_NONE, 1373 iris_get_port_info(inst, cap_id), 1374 HFI_PAYLOAD_U32_ENUM, 1375 &layer_type, sizeof(u32)); 1376 } 1377 1378 int iris_set_layer_count_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1379 { 1380 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1381 struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx); 1382 struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 1383 u32 layer_enable = inst->fw_caps[LAYER_ENABLE].value; 1384 u32 layer_count = inst->fw_caps[cap_id].value; 1385 u32 hfi_id, ret; 1386 1387 if (!layer_enable || !layer_count) 1388 return -EINVAL; 1389 1390 inst->hfi_layer_count = layer_count; 1391 1392 if (!vb2_is_streaming(sq) && !vb2_is_streaming(dq)) { 1393 hfi_id = HFI_PROPERTY_PARAM_VENC_HIER_P_MAX_NUM_ENH_LAYER; 1394 ret = hfi_ops->session_set_property(inst, hfi_id, 1395 HFI_HOST_FLAGS_NONE, 1396 iris_get_port_info(inst, cap_id), 1397 HFI_PAYLOAD_U32, 1398 &layer_count, sizeof(u32)); 1399 if (ret) 1400 return ret; 1401 } 1402 1403 hfi_id = inst->fw_caps[cap_id].hfi_id; 1404 return hfi_ops->session_set_property(inst, hfi_id, 1405 HFI_HOST_FLAGS_NONE, 1406 iris_get_port_info(inst, cap_id), 1407 HFI_PAYLOAD_U32, 1408 &layer_count, sizeof(u32)); 1409 } 1410 1411 int iris_set_layer_count_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1412 { 1413 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1414 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1415 u32 layer_type = inst->hfi_layer_type; 1416 u32 layer_count, layer_count_max; 1417 1418 layer_count = (inst->codec == V4L2_PIX_FMT_H264) ? 1419 inst->fw_caps[LAYER_COUNT_H264].value : 1420 inst->fw_caps[LAYER_COUNT_HEVC].value; 1421 1422 if (!layer_count) 1423 return -EINVAL; 1424 1425 if (layer_type == HFI_HIER_B) { 1426 layer_count_max = MAX_LAYER_HB; 1427 } else if (layer_type == HFI_HIER_P_HYBRID_LTR) { 1428 layer_count_max = MAX_AVC_LAYER_HP_HYBRID_LTR; 1429 } else if (layer_type == HFI_HIER_P_SLIDING_WINDOW) { 1430 if (inst->codec == V4L2_PIX_FMT_H264) { 1431 layer_count_max = MAX_AVC_LAYER_HP_SLIDING_WINDOW; 1432 } else { 1433 if (inst->hfi_rc_type == HFI_RC_VBR_CFR) 1434 layer_count_max = MAX_HEVC_VBR_LAYER_HP_SLIDING_WINDOW; 1435 else 1436 layer_count_max = MAX_HEVC_LAYER_HP_SLIDING_WINDOW; 1437 } 1438 } else { 1439 return -EINVAL; 1440 } 1441 1442 if (layer_count > layer_count_max) 1443 layer_count = layer_count_max; 1444 1445 layer_count += 1; /* base layer */ 1446 inst->hfi_layer_count = layer_count; 1447 1448 return hfi_ops->session_set_property(inst, hfi_id, 1449 HFI_HOST_FLAGS_NONE, 1450 iris_get_port_info(inst, cap_id), 1451 HFI_PAYLOAD_U32, 1452 &layer_count, sizeof(u32)); 1453 } 1454 1455 int iris_set_layer_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 1456 { 1457 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1458 struct vb2_queue *sq = v4l2_m2m_get_src_vq(inst->m2m_ctx); 1459 struct vb2_queue *dq = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 1460 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 1461 u32 bitrate = inst->fw_caps[cap_id].value; 1462 1463 /* ignore layer bitrate when total bitrate is set */ 1464 if (inst->fw_caps[BITRATE].flags & CAP_FLAG_CLIENT_SET) 1465 return 0; 1466 1467 if (!(inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET)) 1468 return -EINVAL; 1469 1470 if (!vb2_is_streaming(sq) && !vb2_is_streaming(dq)) 1471 return -EINVAL; 1472 1473 return hfi_ops->session_set_property(inst, hfi_id, 1474 HFI_HOST_FLAGS_NONE, 1475 iris_get_port_info(inst, cap_id), 1476 HFI_PAYLOAD_U32, 1477 &bitrate, sizeof(u32)); 1478 } 1479 1480 int iris_set_properties(struct iris_inst *inst, u32 plane) 1481 { 1482 const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops; 1483 struct platform_inst_fw_cap *cap; 1484 int ret; 1485 u32 i; 1486 1487 ret = hfi_ops->session_set_config_params(inst, plane); 1488 if (ret) 1489 return ret; 1490 1491 for (i = 1; i < INST_FW_CAP_MAX; i++) { 1492 cap = &inst->fw_caps[i]; 1493 if (!iris_valid_cap_id(cap->cap_id)) 1494 continue; 1495 1496 if (cap->cap_id && cap->set) 1497 cap->set(inst, i); 1498 } 1499 1500 return 0; 1501 } 1502