1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: 102 return PROFILE_AV1; 103 case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: 104 return LEVEL_AV1; 105 case V4L2_CID_ROTATE: 106 return ROTATION; 107 case V4L2_CID_HFLIP: 108 return HFLIP; 109 case V4L2_CID_VFLIP: 110 return VFLIP; 111 default: 112 return INST_FW_CAP_MAX; 113 } 114 } 115 116 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 117 { 118 if (!iris_valid_cap_id(cap_id)) 119 return 0; 120 121 switch (cap_id) { 122 case PROFILE_H264: 123 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 124 case PROFILE_HEVC: 125 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 126 case PROFILE_VP9: 127 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 128 case LEVEL_H264: 129 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 130 case LEVEL_HEVC: 131 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 132 case LEVEL_VP9: 133 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 134 case TIER: 135 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 136 case HEADER_MODE: 137 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 138 case PREPEND_SPSPPS_TO_IDR: 139 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 140 case BITRATE: 141 return V4L2_CID_MPEG_VIDEO_BITRATE; 142 case BITRATE_PEAK: 143 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 144 case BITRATE_MODE: 145 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 146 case FRAME_SKIP_MODE: 147 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 148 case FRAME_RC_ENABLE: 149 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 150 case GOP_SIZE: 151 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 152 case ENTROPY_MODE: 153 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 154 case MIN_FRAME_QP_H264: 155 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 156 case MIN_FRAME_QP_HEVC: 157 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 158 case MAX_FRAME_QP_H264: 159 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 160 case MAX_FRAME_QP_HEVC: 161 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 162 case I_FRAME_MIN_QP_H264: 163 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 164 case I_FRAME_MIN_QP_HEVC: 165 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 166 case P_FRAME_MIN_QP_H264: 167 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 168 case P_FRAME_MIN_QP_HEVC: 169 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 170 case B_FRAME_MIN_QP_H264: 171 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 172 case B_FRAME_MIN_QP_HEVC: 173 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 174 case I_FRAME_MAX_QP_H264: 175 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 176 case I_FRAME_MAX_QP_HEVC: 177 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 178 case P_FRAME_MAX_QP_H264: 179 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 180 case P_FRAME_MAX_QP_HEVC: 181 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 182 case B_FRAME_MAX_QP_H264: 183 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 184 case B_FRAME_MAX_QP_HEVC: 185 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 186 case I_FRAME_QP_H264: 187 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 188 case I_FRAME_QP_HEVC: 189 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 190 case P_FRAME_QP_H264: 191 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 192 case P_FRAME_QP_HEVC: 193 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 194 case B_FRAME_QP_H264: 195 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 196 case B_FRAME_QP_HEVC: 197 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 198 case PROFILE_AV1: 199 return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; 200 case LEVEL_AV1: 201 return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; 202 case ROTATION: 203 return V4L2_CID_ROTATE; 204 case HFLIP: 205 return V4L2_CID_HFLIP; 206 case VFLIP: 207 return V4L2_CID_VFLIP; 208 default: 209 return 0; 210 } 211 } 212 213 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 214 { 215 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 216 enum platform_inst_fw_cap_type cap_id; 217 struct platform_inst_fw_cap *cap; 218 struct vb2_queue *q; 219 220 cap = &inst->fw_caps[0]; 221 cap_id = iris_get_cap_id(ctrl->id); 222 if (!iris_valid_cap_id(cap_id)) 223 return -EINVAL; 224 225 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 226 if (vb2_is_streaming(q) && 227 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 228 return -EINVAL; 229 230 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 231 232 inst->fw_caps[cap_id].value = ctrl->val; 233 234 if (vb2_is_streaming(q)) { 235 if (cap[cap_id].set) 236 cap[cap_id].set(inst, cap_id); 237 } 238 239 return 0; 240 } 241 242 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 243 .s_ctrl = iris_op_s_ctrl, 244 }; 245 246 int iris_ctrls_init(struct iris_inst *inst) 247 { 248 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 249 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 250 u32 v4l2_id; 251 int ret; 252 253 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 254 if (iris_get_v4l2_id(cap[idx].cap_id)) 255 num_ctrls++; 256 } 257 258 /* Adding 1 to num_ctrls to include 259 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 260 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 261 */ 262 263 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 264 if (ret) 265 return ret; 266 267 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 268 struct v4l2_ctrl *ctrl; 269 270 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 271 if (!v4l2_id) 272 continue; 273 274 if (ctrl_idx >= num_ctrls) { 275 ret = -EINVAL; 276 goto error; 277 } 278 279 if (cap[idx].flags & CAP_FLAG_MENU) { 280 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 281 &iris_ctrl_ops, 282 v4l2_id, 283 cap[idx].max, 284 ~(cap[idx].step_or_mask), 285 cap[idx].value); 286 } else { 287 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 288 &iris_ctrl_ops, 289 v4l2_id, 290 cap[idx].min, 291 cap[idx].max, 292 cap[idx].step_or_mask, 293 cap[idx].value); 294 } 295 if (!ctrl) { 296 ret = -EINVAL; 297 goto error; 298 } 299 300 ctrl_idx++; 301 } 302 303 if (inst->domain == DECODER) { 304 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 305 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 306 } else { 307 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 308 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 309 } 310 311 ret = inst->ctrl_handler.error; 312 if (ret) 313 goto error; 314 315 return 0; 316 error: 317 v4l2_ctrl_handler_free(&inst->ctrl_handler); 318 319 return ret; 320 } 321 322 void iris_session_init_caps(struct iris_core *core) 323 { 324 const struct platform_inst_fw_cap *caps; 325 u32 i, num_cap, cap_id; 326 327 caps = core->iris_platform_data->inst_fw_caps_dec; 328 num_cap = core->iris_platform_data->inst_fw_caps_dec_size; 329 330 for (i = 0; i < num_cap; i++) { 331 cap_id = caps[i].cap_id; 332 if (!iris_valid_cap_id(cap_id)) 333 continue; 334 335 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 336 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 337 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 338 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 339 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 340 341 if (cap_id == PIPE) { 342 core->inst_fw_caps_dec[cap_id].value = 343 core->iris_platform_data->num_vpp_pipe; 344 core->inst_fw_caps_dec[cap_id].min = 345 core->iris_platform_data->num_vpp_pipe; 346 core->inst_fw_caps_dec[cap_id].max = 347 core->iris_platform_data->num_vpp_pipe; 348 } else { 349 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 350 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 351 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 352 } 353 } 354 355 caps = core->iris_platform_data->inst_fw_caps_enc; 356 num_cap = core->iris_platform_data->inst_fw_caps_enc_size; 357 358 for (i = 0; i < num_cap; i++) { 359 cap_id = caps[i].cap_id; 360 if (!iris_valid_cap_id(cap_id)) 361 continue; 362 363 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 364 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 365 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 366 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 367 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 368 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 369 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 370 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 371 } 372 } 373 374 static u32 iris_get_port_info(struct iris_inst *inst, 375 enum platform_inst_fw_cap_type cap_id) 376 { 377 if (inst->domain == DECODER) { 378 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 379 return HFI_PORT_BITSTREAM; 380 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 381 return HFI_PORT_RAW; 382 } else { 383 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 384 return HFI_PORT_RAW; 385 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 386 return HFI_PORT_BITSTREAM; 387 } 388 389 return HFI_PORT_NONE; 390 } 391 392 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 393 { 394 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 395 u32 hfi_value = inst->fw_caps[cap_id].value; 396 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 397 398 return hfi_ops->session_set_property(inst, hfi_id, 399 HFI_HOST_FLAGS_NONE, 400 iris_get_port_info(inst, cap_id), 401 HFI_PAYLOAD_U32_ENUM, 402 &hfi_value, sizeof(u32)); 403 } 404 405 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 406 { 407 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 408 u32 hfi_value = inst->fw_caps[cap_id].value; 409 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 410 411 return hfi_ops->session_set_property(inst, hfi_id, 412 HFI_HOST_FLAGS_NONE, 413 iris_get_port_info(inst, cap_id), 414 HFI_PAYLOAD_U32, 415 &hfi_value, sizeof(u32)); 416 } 417 418 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 419 { 420 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 421 struct v4l2_format *inp_f = inst->fmt_src; 422 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 423 u32 height = inp_f->fmt.pix_mp.height; 424 u32 width = inp_f->fmt.pix_mp.width; 425 u32 work_mode = STAGE_2; 426 427 if (inst->domain == DECODER) { 428 if (iris_res_is_less_than(width, height, 1280, 720)) 429 work_mode = STAGE_1; 430 } 431 432 return hfi_ops->session_set_property(inst, hfi_id, 433 HFI_HOST_FLAGS_NONE, 434 iris_get_port_info(inst, cap_id), 435 HFI_PAYLOAD_U32, 436 &work_mode, sizeof(u32)); 437 } 438 439 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 440 { 441 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 442 u32 work_route = inst->fw_caps[PIPE].value; 443 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 444 445 return hfi_ops->session_set_property(inst, hfi_id, 446 HFI_HOST_FLAGS_NONE, 447 iris_get_port_info(inst, cap_id), 448 HFI_PAYLOAD_U32, 449 &work_route, sizeof(u32)); 450 } 451 452 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 453 { 454 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 455 u32 hfi_id, hfi_value; 456 457 if (inst->codec == V4L2_PIX_FMT_H264) { 458 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 459 hfi_value = inst->fw_caps[PROFILE_H264].value; 460 } else { 461 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 462 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 463 } 464 465 return hfi_ops->session_set_property(inst, hfi_id, 466 HFI_HOST_FLAGS_NONE, 467 iris_get_port_info(inst, cap_id), 468 HFI_PAYLOAD_U32_ENUM, 469 &hfi_value, sizeof(u32)); 470 } 471 472 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 473 { 474 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 475 u32 hfi_id, hfi_value; 476 477 if (inst->codec == V4L2_PIX_FMT_H264) { 478 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 479 hfi_value = inst->fw_caps[LEVEL_H264].value; 480 } else { 481 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 482 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 483 } 484 485 return hfi_ops->session_set_property(inst, hfi_id, 486 HFI_HOST_FLAGS_NONE, 487 iris_get_port_info(inst, cap_id), 488 HFI_PAYLOAD_U32_ENUM, 489 &hfi_value, sizeof(u32)); 490 } 491 492 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 493 { 494 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 495 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 496 struct hfi_profile_level pl; 497 498 if (inst->codec == V4L2_PIX_FMT_H264) { 499 pl.profile = inst->fw_caps[PROFILE_H264].value; 500 pl.level = inst->fw_caps[LEVEL_H264].value; 501 } else { 502 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 503 pl.level = inst->fw_caps[LEVEL_HEVC].value; 504 } 505 506 return hfi_ops->session_set_property(inst, hfi_id, 507 HFI_HOST_FLAGS_NONE, 508 iris_get_port_info(inst, cap_id), 509 HFI_PAYLOAD_U32_ENUM, 510 &pl, sizeof(u32)); 511 } 512 513 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 514 { 515 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 516 u32 header_mode = inst->fw_caps[cap_id].value; 517 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 518 u32 hfi_val; 519 520 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 521 hfi_val = 0; 522 else 523 hfi_val = 1; 524 525 return hfi_ops->session_set_property(inst, hfi_id, 526 HFI_HOST_FLAGS_NONE, 527 iris_get_port_info(inst, cap_id), 528 HFI_PAYLOAD_U32, 529 &hfi_val, sizeof(u32)); 530 } 531 532 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 533 { 534 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 535 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 536 u32 header_mode = inst->fw_caps[cap_id].value; 537 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 538 u32 hfi_val; 539 540 if (prepend_sps_pps) 541 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 542 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 543 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 544 else 545 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 546 547 return hfi_ops->session_set_property(inst, hfi_id, 548 HFI_HOST_FLAGS_NONE, 549 iris_get_port_info(inst, cap_id), 550 HFI_PAYLOAD_U32_ENUM, 551 &hfi_val, sizeof(u32)); 552 } 553 554 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 555 { 556 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 557 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 558 u32 bitrate = inst->fw_caps[cap_id].value; 559 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 560 u32 max_bitrate; 561 562 if (inst->codec == V4L2_PIX_FMT_HEVC) 563 max_bitrate = CABAC_MAX_BITRATE; 564 565 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 566 max_bitrate = CABAC_MAX_BITRATE; 567 else 568 max_bitrate = CAVLC_MAX_BITRATE; 569 570 bitrate = min(bitrate, max_bitrate); 571 572 return hfi_ops->session_set_property(inst, hfi_id, 573 HFI_HOST_FLAGS_NONE, 574 iris_get_port_info(inst, cap_id), 575 HFI_PAYLOAD_U32, 576 &bitrate, sizeof(u32)); 577 } 578 579 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 580 { 581 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 582 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 583 u32 peak_bitrate = inst->fw_caps[cap_id].value; 584 u32 bitrate = inst->fw_caps[BITRATE].value; 585 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 586 587 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 588 return 0; 589 590 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 591 if (peak_bitrate < bitrate) 592 peak_bitrate = bitrate; 593 } else { 594 peak_bitrate = bitrate; 595 } 596 597 inst->fw_caps[cap_id].value = peak_bitrate; 598 599 return hfi_ops->session_set_property(inst, hfi_id, 600 HFI_HOST_FLAGS_NONE, 601 iris_get_port_info(inst, cap_id), 602 HFI_PAYLOAD_U32, 603 &peak_bitrate, sizeof(u32)); 604 } 605 606 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 607 { 608 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 609 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 610 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 611 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 612 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 613 u32 rc_mode = 0; 614 615 if (!frame_rc) 616 rc_mode = HFI_RATE_CONTROL_OFF; 617 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 618 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 619 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 620 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 621 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 622 rc_mode = HFI_RATE_CONTROL_CQ; 623 624 inst->hfi_rc_type = rc_mode; 625 626 return hfi_ops->session_set_property(inst, hfi_id, 627 HFI_HOST_FLAGS_NONE, 628 iris_get_port_info(inst, cap_id), 629 HFI_PAYLOAD_U32_ENUM, 630 &rc_mode, sizeof(u32)); 631 } 632 633 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 634 { 635 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 636 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 637 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 638 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 639 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 640 u32 rc_mode = 0; 641 642 if (!frame_rc) 643 rc_mode = HFI_RC_OFF; 644 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 645 rc_mode = HFI_RC_VBR_CFR; 646 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 647 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 648 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 649 rc_mode = HFI_RC_CQ; 650 651 inst->hfi_rc_type = rc_mode; 652 653 return hfi_ops->session_set_property(inst, hfi_id, 654 HFI_HOST_FLAGS_NONE, 655 iris_get_port_info(inst, cap_id), 656 HFI_PAYLOAD_U32_ENUM, 657 &rc_mode, sizeof(u32)); 658 } 659 660 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 661 { 662 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 663 u32 entropy_mode = inst->fw_caps[cap_id].value; 664 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 665 u32 hfi_val; 666 667 if (inst->codec != V4L2_PIX_FMT_H264) 668 return 0; 669 670 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 671 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 672 673 return hfi_ops->session_set_property(inst, hfi_id, 674 HFI_HOST_FLAGS_NONE, 675 iris_get_port_info(inst, cap_id), 676 HFI_PAYLOAD_U32, 677 &hfi_val, sizeof(u32)); 678 } 679 680 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 681 { 682 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 683 u32 entropy_mode = inst->fw_caps[cap_id].value; 684 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 685 u32 profile; 686 687 if (inst->codec != V4L2_PIX_FMT_H264) 688 return 0; 689 690 profile = inst->fw_caps[PROFILE_H264].value; 691 692 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 693 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 694 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 695 696 inst->fw_caps[cap_id].value = entropy_mode; 697 698 return hfi_ops->session_set_property(inst, hfi_id, 699 HFI_HOST_FLAGS_NONE, 700 iris_get_port_info(inst, cap_id), 701 HFI_PAYLOAD_U32, 702 &entropy_mode, sizeof(u32)); 703 } 704 705 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 706 { 707 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 708 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 709 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 710 u32 min_qp_enable = 0, client_qp_enable = 0; 711 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 712 u32 hfi_val; 713 714 if (inst->codec == V4L2_PIX_FMT_H264) { 715 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 716 min_qp_enable = 1; 717 if (min_qp_enable || 718 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 719 i_qp_enable = 1; 720 if (min_qp_enable || 721 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 722 p_qp_enable = 1; 723 if (min_qp_enable || 724 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 725 b_qp_enable = 1; 726 } else { 727 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 728 min_qp_enable = 1; 729 if (min_qp_enable || 730 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 731 i_qp_enable = 1; 732 if (min_qp_enable || 733 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 734 p_qp_enable = 1; 735 if (min_qp_enable || 736 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 737 b_qp_enable = 1; 738 } 739 740 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 741 if (!client_qp_enable) 742 return 0; 743 744 if (inst->codec == V4L2_PIX_FMT_H264) { 745 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 746 inst->fw_caps[MIN_FRAME_QP_H264].value); 747 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 748 inst->fw_caps[MIN_FRAME_QP_H264].value); 749 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 750 inst->fw_caps[MIN_FRAME_QP_H264].value); 751 } else { 752 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 753 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 754 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 755 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 756 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 757 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 758 } 759 760 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 761 762 return hfi_ops->session_set_property(inst, hfi_id, 763 HFI_HOST_FLAGS_NONE, 764 iris_get_port_info(inst, cap_id), 765 HFI_PAYLOAD_32_PACKED, 766 &hfi_val, sizeof(u32)); 767 } 768 769 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 770 { 771 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 772 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 773 u32 max_qp_enable = 0, client_qp_enable; 774 u32 i_frame_qp, p_frame_qp, b_frame_qp; 775 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 776 u32 hfi_val; 777 778 if (inst->codec == V4L2_PIX_FMT_H264) { 779 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 780 max_qp_enable = 1; 781 if (max_qp_enable || 782 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 783 i_qp_enable = 1; 784 if (max_qp_enable || 785 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 786 p_qp_enable = 1; 787 if (max_qp_enable || 788 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 789 b_qp_enable = 1; 790 } else { 791 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 792 max_qp_enable = 1; 793 if (max_qp_enable || 794 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 795 i_qp_enable = 1; 796 if (max_qp_enable || 797 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 798 p_qp_enable = 1; 799 if (max_qp_enable || 800 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 801 b_qp_enable = 1; 802 } 803 804 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 805 if (!client_qp_enable) 806 return 0; 807 808 if (inst->codec == V4L2_PIX_FMT_H264) { 809 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 810 inst->fw_caps[MAX_FRAME_QP_H264].value); 811 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 812 inst->fw_caps[MAX_FRAME_QP_H264].value); 813 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 814 inst->fw_caps[MAX_FRAME_QP_H264].value); 815 } else { 816 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 817 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 818 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 819 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 820 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 821 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 822 } 823 824 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 825 client_qp_enable << 24; 826 827 return hfi_ops->session_set_property(inst, hfi_id, 828 HFI_HOST_FLAGS_NONE, 829 iris_get_port_info(inst, cap_id), 830 HFI_PAYLOAD_32_PACKED, 831 &hfi_val, sizeof(u32)); 832 } 833 834 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 835 { 836 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 837 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 838 u32 i_frame_qp, p_frame_qp, b_frame_qp; 839 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 840 struct vb2_queue *q; 841 u32 hfi_val; 842 843 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 844 if (vb2_is_streaming(q)) { 845 if (inst->hfi_rc_type != HFI_RC_OFF) 846 return 0; 847 } 848 849 if (inst->hfi_rc_type == HFI_RC_OFF) { 850 i_qp_enable = 1; 851 p_qp_enable = 1; 852 b_qp_enable = 1; 853 } else { 854 if (inst->codec == V4L2_PIX_FMT_H264) { 855 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 856 i_qp_enable = 1; 857 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 858 p_qp_enable = 1; 859 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 860 b_qp_enable = 1; 861 } else { 862 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 863 i_qp_enable = 1; 864 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 865 p_qp_enable = 1; 866 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 867 b_qp_enable = 1; 868 } 869 } 870 871 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 872 if (!client_qp_enable) 873 return 0; 874 875 if (inst->codec == V4L2_PIX_FMT_H264) { 876 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 877 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 878 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 879 } else { 880 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 881 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 882 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 883 } 884 885 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 886 client_qp_enable << 24; 887 888 return hfi_ops->session_set_property(inst, hfi_id, 889 HFI_HOST_FLAGS_NONE, 890 iris_get_port_info(inst, cap_id), 891 HFI_PAYLOAD_32_PACKED, 892 &hfi_val, sizeof(u32)); 893 } 894 895 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 896 { 897 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 898 struct hfi_quantization_range_v2 range; 899 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 900 901 if (inst->codec == V4L2_PIX_FMT_HEVC) { 902 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 903 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 904 } else { 905 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 906 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 907 } 908 909 return hfi_ops->session_set_property(inst, hfi_id, 910 HFI_HOST_FLAGS_NONE, 911 iris_get_port_info(inst, cap_id), 912 HFI_PAYLOAD_32_PACKED, 913 &range, sizeof(range)); 914 } 915 916 int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 917 { 918 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 919 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 920 u32 hfi_val; 921 922 switch (inst->fw_caps[cap_id].value) { 923 case 0: 924 hfi_val = HFI_ROTATION_NONE; 925 return 0; 926 case 90: 927 hfi_val = HFI_ROTATION_90; 928 break; 929 case 180: 930 hfi_val = HFI_ROTATION_180; 931 break; 932 case 270: 933 hfi_val = HFI_ROTATION_270; 934 break; 935 default: 936 return -EINVAL; 937 } 938 939 return hfi_ops->session_set_property(inst, hfi_id, 940 HFI_HOST_FLAGS_NONE, 941 iris_get_port_info(inst, cap_id), 942 HFI_PAYLOAD_U32, 943 &hfi_val, sizeof(u32)); 944 } 945 946 int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 947 { 948 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 949 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 950 u32 hfi_val = HFI_DISABLE_FLIP; 951 952 if (inst->fw_caps[HFLIP].value) 953 hfi_val |= HFI_HORIZONTAL_FLIP; 954 955 if (inst->fw_caps[VFLIP].value) 956 hfi_val |= HFI_VERTICAL_FLIP; 957 958 return hfi_ops->session_set_property(inst, hfi_id, 959 HFI_HOST_FLAGS_NONE, 960 iris_get_port_info(inst, cap_id), 961 HFI_PAYLOAD_U32_ENUM, 962 &hfi_val, sizeof(u32)); 963 } 964 965 int iris_set_properties(struct iris_inst *inst, u32 plane) 966 { 967 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 968 struct platform_inst_fw_cap *cap; 969 int ret; 970 u32 i; 971 972 ret = hfi_ops->session_set_config_params(inst, plane); 973 if (ret) 974 return ret; 975 976 for (i = 1; i < INST_FW_CAP_MAX; i++) { 977 cap = &inst->fw_caps[i]; 978 if (!iris_valid_cap_id(cap->cap_id)) 979 continue; 980 981 if (cap->cap_id && cap->set) 982 cap->set(inst, i); 983 } 984 985 return 0; 986 } 987