1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 default: 102 return INST_FW_CAP_MAX; 103 } 104 } 105 106 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 107 { 108 if (!iris_valid_cap_id(cap_id)) 109 return 0; 110 111 switch (cap_id) { 112 case PROFILE_H264: 113 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 114 case PROFILE_HEVC: 115 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 116 case PROFILE_VP9: 117 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 118 case LEVEL_H264: 119 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 120 case LEVEL_HEVC: 121 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 122 case LEVEL_VP9: 123 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 124 case TIER: 125 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 126 case HEADER_MODE: 127 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 128 case PREPEND_SPSPPS_TO_IDR: 129 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 130 case BITRATE: 131 return V4L2_CID_MPEG_VIDEO_BITRATE; 132 case BITRATE_PEAK: 133 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 134 case BITRATE_MODE: 135 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 136 case FRAME_SKIP_MODE: 137 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 138 case FRAME_RC_ENABLE: 139 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 140 case GOP_SIZE: 141 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 142 case ENTROPY_MODE: 143 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 144 case MIN_FRAME_QP_H264: 145 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 146 case MIN_FRAME_QP_HEVC: 147 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 148 case MAX_FRAME_QP_H264: 149 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 150 case MAX_FRAME_QP_HEVC: 151 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 152 case I_FRAME_MIN_QP_H264: 153 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 154 case I_FRAME_MIN_QP_HEVC: 155 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 156 case P_FRAME_MIN_QP_H264: 157 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 158 case P_FRAME_MIN_QP_HEVC: 159 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 160 case B_FRAME_MIN_QP_H264: 161 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 162 case B_FRAME_MIN_QP_HEVC: 163 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 164 case I_FRAME_MAX_QP_H264: 165 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 166 case I_FRAME_MAX_QP_HEVC: 167 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 168 case P_FRAME_MAX_QP_H264: 169 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 170 case P_FRAME_MAX_QP_HEVC: 171 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 172 case B_FRAME_MAX_QP_H264: 173 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 174 case B_FRAME_MAX_QP_HEVC: 175 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 176 case I_FRAME_QP_H264: 177 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 178 case I_FRAME_QP_HEVC: 179 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 180 case P_FRAME_QP_H264: 181 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 182 case P_FRAME_QP_HEVC: 183 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 184 case B_FRAME_QP_H264: 185 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 186 case B_FRAME_QP_HEVC: 187 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 188 default: 189 return 0; 190 } 191 } 192 193 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 194 { 195 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 196 enum platform_inst_fw_cap_type cap_id; 197 struct platform_inst_fw_cap *cap; 198 struct vb2_queue *q; 199 200 cap = &inst->fw_caps[0]; 201 cap_id = iris_get_cap_id(ctrl->id); 202 if (!iris_valid_cap_id(cap_id)) 203 return -EINVAL; 204 205 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 206 if (vb2_is_streaming(q) && 207 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 208 return -EINVAL; 209 210 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 211 212 inst->fw_caps[cap_id].value = ctrl->val; 213 214 if (vb2_is_streaming(q)) { 215 if (cap[cap_id].set) 216 cap[cap_id].set(inst, cap_id); 217 } 218 219 return 0; 220 } 221 222 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 223 .s_ctrl = iris_op_s_ctrl, 224 }; 225 226 int iris_ctrls_init(struct iris_inst *inst) 227 { 228 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 229 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 230 u32 v4l2_id; 231 int ret; 232 233 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 234 if (iris_get_v4l2_id(cap[idx].cap_id)) 235 num_ctrls++; 236 } 237 238 /* Adding 1 to num_ctrls to include 239 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 240 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 241 */ 242 243 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 244 if (ret) 245 return ret; 246 247 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 248 struct v4l2_ctrl *ctrl; 249 250 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 251 if (!v4l2_id) 252 continue; 253 254 if (ctrl_idx >= num_ctrls) { 255 ret = -EINVAL; 256 goto error; 257 } 258 259 if (cap[idx].flags & CAP_FLAG_MENU) { 260 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 261 &iris_ctrl_ops, 262 v4l2_id, 263 cap[idx].max, 264 ~(cap[idx].step_or_mask), 265 cap[idx].value); 266 } else { 267 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 268 &iris_ctrl_ops, 269 v4l2_id, 270 cap[idx].min, 271 cap[idx].max, 272 cap[idx].step_or_mask, 273 cap[idx].value); 274 } 275 if (!ctrl) { 276 ret = -EINVAL; 277 goto error; 278 } 279 280 ctrl_idx++; 281 } 282 283 if (inst->domain == DECODER) { 284 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 285 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 286 } else { 287 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 288 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 289 } 290 291 ret = inst->ctrl_handler.error; 292 if (ret) 293 goto error; 294 295 return 0; 296 error: 297 v4l2_ctrl_handler_free(&inst->ctrl_handler); 298 299 return ret; 300 } 301 302 void iris_session_init_caps(struct iris_core *core) 303 { 304 const struct platform_inst_fw_cap *caps; 305 u32 i, num_cap, cap_id; 306 307 caps = core->iris_platform_data->inst_fw_caps_dec; 308 num_cap = core->iris_platform_data->inst_fw_caps_dec_size; 309 310 for (i = 0; i < num_cap; i++) { 311 cap_id = caps[i].cap_id; 312 if (!iris_valid_cap_id(cap_id)) 313 continue; 314 315 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 316 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 317 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 318 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 319 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 320 321 if (cap_id == PIPE) { 322 core->inst_fw_caps_dec[cap_id].value = 323 core->iris_platform_data->num_vpp_pipe; 324 core->inst_fw_caps_dec[cap_id].min = 325 core->iris_platform_data->num_vpp_pipe; 326 core->inst_fw_caps_dec[cap_id].max = 327 core->iris_platform_data->num_vpp_pipe; 328 } else { 329 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 330 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 331 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 332 } 333 } 334 335 caps = core->iris_platform_data->inst_fw_caps_enc; 336 num_cap = core->iris_platform_data->inst_fw_caps_enc_size; 337 338 for (i = 0; i < num_cap; i++) { 339 cap_id = caps[i].cap_id; 340 if (!iris_valid_cap_id(cap_id)) 341 continue; 342 343 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 344 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 345 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 346 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 347 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 348 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 349 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 350 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 351 } 352 } 353 354 static u32 iris_get_port_info(struct iris_inst *inst, 355 enum platform_inst_fw_cap_type cap_id) 356 { 357 if (inst->domain == DECODER) { 358 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 359 return HFI_PORT_BITSTREAM; 360 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 361 return HFI_PORT_RAW; 362 } else { 363 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 364 return HFI_PORT_RAW; 365 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 366 return HFI_PORT_BITSTREAM; 367 } 368 369 return HFI_PORT_NONE; 370 } 371 372 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 373 { 374 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 375 u32 hfi_value = inst->fw_caps[cap_id].value; 376 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 377 378 return hfi_ops->session_set_property(inst, hfi_id, 379 HFI_HOST_FLAGS_NONE, 380 iris_get_port_info(inst, cap_id), 381 HFI_PAYLOAD_U32_ENUM, 382 &hfi_value, sizeof(u32)); 383 } 384 385 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 386 { 387 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 388 u32 hfi_value = inst->fw_caps[cap_id].value; 389 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 390 391 return hfi_ops->session_set_property(inst, hfi_id, 392 HFI_HOST_FLAGS_NONE, 393 iris_get_port_info(inst, cap_id), 394 HFI_PAYLOAD_U32, 395 &hfi_value, sizeof(u32)); 396 } 397 398 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 399 { 400 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 401 struct v4l2_format *inp_f = inst->fmt_src; 402 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 403 u32 height = inp_f->fmt.pix_mp.height; 404 u32 width = inp_f->fmt.pix_mp.width; 405 u32 work_mode = STAGE_2; 406 407 if (inst->domain == DECODER) { 408 if (iris_res_is_less_than(width, height, 1280, 720)) 409 work_mode = STAGE_1; 410 } 411 412 return hfi_ops->session_set_property(inst, hfi_id, 413 HFI_HOST_FLAGS_NONE, 414 iris_get_port_info(inst, cap_id), 415 HFI_PAYLOAD_U32, 416 &work_mode, sizeof(u32)); 417 } 418 419 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 420 { 421 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 422 u32 work_route = inst->fw_caps[PIPE].value; 423 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 424 425 return hfi_ops->session_set_property(inst, hfi_id, 426 HFI_HOST_FLAGS_NONE, 427 iris_get_port_info(inst, cap_id), 428 HFI_PAYLOAD_U32, 429 &work_route, sizeof(u32)); 430 } 431 432 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 433 { 434 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 435 u32 hfi_id, hfi_value; 436 437 if (inst->codec == V4L2_PIX_FMT_H264) { 438 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 439 hfi_value = inst->fw_caps[PROFILE_H264].value; 440 } else { 441 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 442 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 443 } 444 445 return hfi_ops->session_set_property(inst, hfi_id, 446 HFI_HOST_FLAGS_NONE, 447 iris_get_port_info(inst, cap_id), 448 HFI_PAYLOAD_U32_ENUM, 449 &hfi_value, sizeof(u32)); 450 } 451 452 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 453 { 454 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 455 u32 hfi_id, hfi_value; 456 457 if (inst->codec == V4L2_PIX_FMT_H264) { 458 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 459 hfi_value = inst->fw_caps[LEVEL_H264].value; 460 } else { 461 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 462 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 463 } 464 465 return hfi_ops->session_set_property(inst, hfi_id, 466 HFI_HOST_FLAGS_NONE, 467 iris_get_port_info(inst, cap_id), 468 HFI_PAYLOAD_U32_ENUM, 469 &hfi_value, sizeof(u32)); 470 } 471 472 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 473 { 474 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 475 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 476 struct hfi_profile_level pl; 477 478 if (inst->codec == V4L2_PIX_FMT_H264) { 479 pl.profile = inst->fw_caps[PROFILE_H264].value; 480 pl.level = inst->fw_caps[LEVEL_H264].value; 481 } else { 482 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 483 pl.level = inst->fw_caps[LEVEL_HEVC].value; 484 } 485 486 return hfi_ops->session_set_property(inst, hfi_id, 487 HFI_HOST_FLAGS_NONE, 488 iris_get_port_info(inst, cap_id), 489 HFI_PAYLOAD_U32_ENUM, 490 &pl, sizeof(u32)); 491 } 492 493 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 494 { 495 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 496 u32 header_mode = inst->fw_caps[cap_id].value; 497 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 498 u32 hfi_val; 499 500 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 501 hfi_val = 0; 502 else 503 hfi_val = 1; 504 505 return hfi_ops->session_set_property(inst, hfi_id, 506 HFI_HOST_FLAGS_NONE, 507 iris_get_port_info(inst, cap_id), 508 HFI_PAYLOAD_U32, 509 &hfi_val, sizeof(u32)); 510 } 511 512 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 513 { 514 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 515 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 516 u32 header_mode = inst->fw_caps[cap_id].value; 517 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 518 u32 hfi_val; 519 520 if (prepend_sps_pps) 521 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 522 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 523 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 524 else 525 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 526 527 return hfi_ops->session_set_property(inst, hfi_id, 528 HFI_HOST_FLAGS_NONE, 529 iris_get_port_info(inst, cap_id), 530 HFI_PAYLOAD_U32_ENUM, 531 &hfi_val, sizeof(u32)); 532 } 533 534 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 535 { 536 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 537 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 538 u32 bitrate = inst->fw_caps[cap_id].value; 539 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 540 u32 max_bitrate; 541 542 if (inst->codec == V4L2_PIX_FMT_HEVC) 543 max_bitrate = CABAC_MAX_BITRATE; 544 545 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 546 max_bitrate = CABAC_MAX_BITRATE; 547 else 548 max_bitrate = CAVLC_MAX_BITRATE; 549 550 bitrate = min(bitrate, max_bitrate); 551 552 return hfi_ops->session_set_property(inst, hfi_id, 553 HFI_HOST_FLAGS_NONE, 554 iris_get_port_info(inst, cap_id), 555 HFI_PAYLOAD_U32, 556 &bitrate, sizeof(u32)); 557 } 558 559 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 560 { 561 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 562 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 563 u32 peak_bitrate = inst->fw_caps[cap_id].value; 564 u32 bitrate = inst->fw_caps[BITRATE].value; 565 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 566 567 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 568 return 0; 569 570 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 571 if (peak_bitrate < bitrate) 572 peak_bitrate = bitrate; 573 } else { 574 peak_bitrate = bitrate; 575 } 576 577 inst->fw_caps[cap_id].value = peak_bitrate; 578 579 return hfi_ops->session_set_property(inst, hfi_id, 580 HFI_HOST_FLAGS_NONE, 581 iris_get_port_info(inst, cap_id), 582 HFI_PAYLOAD_U32, 583 &peak_bitrate, sizeof(u32)); 584 } 585 586 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 587 { 588 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 589 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 590 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 591 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 592 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 593 u32 rc_mode = 0; 594 595 if (!frame_rc) 596 rc_mode = HFI_RATE_CONTROL_OFF; 597 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 598 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 599 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 600 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 601 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 602 rc_mode = HFI_RATE_CONTROL_CQ; 603 604 inst->hfi_rc_type = rc_mode; 605 606 return hfi_ops->session_set_property(inst, hfi_id, 607 HFI_HOST_FLAGS_NONE, 608 iris_get_port_info(inst, cap_id), 609 HFI_PAYLOAD_U32_ENUM, 610 &rc_mode, sizeof(u32)); 611 } 612 613 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 614 { 615 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 616 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 617 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 618 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 619 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 620 u32 rc_mode = 0; 621 622 if (!frame_rc) 623 rc_mode = HFI_RC_OFF; 624 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 625 rc_mode = HFI_RC_VBR_CFR; 626 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 627 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 628 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 629 rc_mode = HFI_RC_CQ; 630 631 inst->hfi_rc_type = rc_mode; 632 633 return hfi_ops->session_set_property(inst, hfi_id, 634 HFI_HOST_FLAGS_NONE, 635 iris_get_port_info(inst, cap_id), 636 HFI_PAYLOAD_U32_ENUM, 637 &rc_mode, sizeof(u32)); 638 } 639 640 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 641 { 642 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 643 u32 entropy_mode = inst->fw_caps[cap_id].value; 644 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 645 u32 hfi_val; 646 647 if (inst->codec != V4L2_PIX_FMT_H264) 648 return 0; 649 650 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 651 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 652 653 return hfi_ops->session_set_property(inst, hfi_id, 654 HFI_HOST_FLAGS_NONE, 655 iris_get_port_info(inst, cap_id), 656 HFI_PAYLOAD_U32, 657 &hfi_val, sizeof(u32)); 658 } 659 660 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 661 { 662 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 663 u32 entropy_mode = inst->fw_caps[cap_id].value; 664 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 665 u32 profile; 666 667 if (inst->codec != V4L2_PIX_FMT_H264) 668 return 0; 669 670 profile = inst->fw_caps[PROFILE_H264].value; 671 672 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 673 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 674 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 675 676 inst->fw_caps[cap_id].value = entropy_mode; 677 678 return hfi_ops->session_set_property(inst, hfi_id, 679 HFI_HOST_FLAGS_NONE, 680 iris_get_port_info(inst, cap_id), 681 HFI_PAYLOAD_U32, 682 &entropy_mode, sizeof(u32)); 683 } 684 685 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 686 { 687 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 688 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 689 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 690 u32 min_qp_enable = 0, client_qp_enable = 0; 691 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 692 u32 hfi_val; 693 694 if (inst->codec == V4L2_PIX_FMT_H264) { 695 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 696 min_qp_enable = 1; 697 if (min_qp_enable || 698 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 699 i_qp_enable = 1; 700 if (min_qp_enable || 701 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 702 p_qp_enable = 1; 703 if (min_qp_enable || 704 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 705 b_qp_enable = 1; 706 } else { 707 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 708 min_qp_enable = 1; 709 if (min_qp_enable || 710 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 711 i_qp_enable = 1; 712 if (min_qp_enable || 713 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 714 p_qp_enable = 1; 715 if (min_qp_enable || 716 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 717 b_qp_enable = 1; 718 } 719 720 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 721 if (!client_qp_enable) 722 return 0; 723 724 if (inst->codec == V4L2_PIX_FMT_H264) { 725 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 726 inst->fw_caps[MIN_FRAME_QP_H264].value); 727 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 728 inst->fw_caps[MIN_FRAME_QP_H264].value); 729 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 730 inst->fw_caps[MIN_FRAME_QP_H264].value); 731 } else { 732 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 733 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 734 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 735 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 736 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 737 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 738 } 739 740 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 741 742 return hfi_ops->session_set_property(inst, hfi_id, 743 HFI_HOST_FLAGS_NONE, 744 iris_get_port_info(inst, cap_id), 745 HFI_PAYLOAD_32_PACKED, 746 &hfi_val, sizeof(u32)); 747 } 748 749 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 750 { 751 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 752 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 753 u32 max_qp_enable = 0, client_qp_enable; 754 u32 i_frame_qp, p_frame_qp, b_frame_qp; 755 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 756 u32 hfi_val; 757 758 if (inst->codec == V4L2_PIX_FMT_H264) { 759 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 760 max_qp_enable = 1; 761 if (max_qp_enable || 762 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 763 i_qp_enable = 1; 764 if (max_qp_enable || 765 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 766 p_qp_enable = 1; 767 if (max_qp_enable || 768 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 769 b_qp_enable = 1; 770 } else { 771 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 772 max_qp_enable = 1; 773 if (max_qp_enable || 774 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 775 i_qp_enable = 1; 776 if (max_qp_enable || 777 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 778 p_qp_enable = 1; 779 if (max_qp_enable || 780 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 781 b_qp_enable = 1; 782 } 783 784 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 785 if (!client_qp_enable) 786 return 0; 787 788 if (inst->codec == V4L2_PIX_FMT_H264) { 789 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 790 inst->fw_caps[MAX_FRAME_QP_H264].value); 791 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 792 inst->fw_caps[MAX_FRAME_QP_H264].value); 793 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 794 inst->fw_caps[MAX_FRAME_QP_H264].value); 795 } else { 796 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 797 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 798 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 799 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 800 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 801 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 802 } 803 804 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 805 client_qp_enable << 24; 806 807 return hfi_ops->session_set_property(inst, hfi_id, 808 HFI_HOST_FLAGS_NONE, 809 iris_get_port_info(inst, cap_id), 810 HFI_PAYLOAD_32_PACKED, 811 &hfi_val, sizeof(u32)); 812 } 813 814 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 815 { 816 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 817 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 818 u32 i_frame_qp, p_frame_qp, b_frame_qp; 819 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 820 struct vb2_queue *q; 821 u32 hfi_val; 822 823 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 824 if (vb2_is_streaming(q)) { 825 if (inst->hfi_rc_type != HFI_RC_OFF) 826 return 0; 827 } 828 829 if (inst->hfi_rc_type == HFI_RC_OFF) { 830 i_qp_enable = 1; 831 p_qp_enable = 1; 832 b_qp_enable = 1; 833 } else { 834 if (inst->codec == V4L2_PIX_FMT_H264) { 835 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 836 i_qp_enable = 1; 837 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 838 p_qp_enable = 1; 839 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 840 b_qp_enable = 1; 841 } else { 842 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 843 i_qp_enable = 1; 844 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 845 p_qp_enable = 1; 846 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 847 b_qp_enable = 1; 848 } 849 } 850 851 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 852 if (!client_qp_enable) 853 return 0; 854 855 if (inst->codec == V4L2_PIX_FMT_H264) { 856 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 857 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 858 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 859 } else { 860 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 861 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 862 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 863 } 864 865 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 866 client_qp_enable << 24; 867 868 return hfi_ops->session_set_property(inst, hfi_id, 869 HFI_HOST_FLAGS_NONE, 870 iris_get_port_info(inst, cap_id), 871 HFI_PAYLOAD_32_PACKED, 872 &hfi_val, sizeof(u32)); 873 } 874 875 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 876 { 877 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 878 struct hfi_quantization_range_v2 range; 879 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 880 881 if (inst->codec == V4L2_PIX_FMT_HEVC) { 882 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 883 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 884 } else { 885 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 886 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 887 } 888 889 return hfi_ops->session_set_property(inst, hfi_id, 890 HFI_HOST_FLAGS_NONE, 891 iris_get_port_info(inst, cap_id), 892 HFI_PAYLOAD_32_PACKED, 893 &range, sizeof(range)); 894 } 895 896 int iris_set_properties(struct iris_inst *inst, u32 plane) 897 { 898 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 899 struct platform_inst_fw_cap *cap; 900 int ret; 901 u32 i; 902 903 ret = hfi_ops->session_set_config_params(inst, plane); 904 if (ret) 905 return ret; 906 907 for (i = 1; i < INST_FW_CAP_MAX; i++) { 908 cap = &inst->fw_caps[i]; 909 if (!iris_valid_cap_id(cap->cap_id)) 910 continue; 911 912 if (cap->cap_id && cap->set) 913 cap->set(inst, i); 914 } 915 916 return 0; 917 } 918