1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: 102 return PROFILE_AV1; 103 case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: 104 return LEVEL_AV1; 105 case V4L2_CID_ROTATE: 106 return ROTATION; 107 default: 108 return INST_FW_CAP_MAX; 109 } 110 } 111 112 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 113 { 114 if (!iris_valid_cap_id(cap_id)) 115 return 0; 116 117 switch (cap_id) { 118 case PROFILE_H264: 119 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 120 case PROFILE_HEVC: 121 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 122 case PROFILE_VP9: 123 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 124 case LEVEL_H264: 125 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 126 case LEVEL_HEVC: 127 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 128 case LEVEL_VP9: 129 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 130 case TIER: 131 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 132 case HEADER_MODE: 133 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 134 case PREPEND_SPSPPS_TO_IDR: 135 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 136 case BITRATE: 137 return V4L2_CID_MPEG_VIDEO_BITRATE; 138 case BITRATE_PEAK: 139 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 140 case BITRATE_MODE: 141 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 142 case FRAME_SKIP_MODE: 143 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 144 case FRAME_RC_ENABLE: 145 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 146 case GOP_SIZE: 147 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 148 case ENTROPY_MODE: 149 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 150 case MIN_FRAME_QP_H264: 151 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 152 case MIN_FRAME_QP_HEVC: 153 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 154 case MAX_FRAME_QP_H264: 155 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 156 case MAX_FRAME_QP_HEVC: 157 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 158 case I_FRAME_MIN_QP_H264: 159 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 160 case I_FRAME_MIN_QP_HEVC: 161 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 162 case P_FRAME_MIN_QP_H264: 163 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 164 case P_FRAME_MIN_QP_HEVC: 165 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 166 case B_FRAME_MIN_QP_H264: 167 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 168 case B_FRAME_MIN_QP_HEVC: 169 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 170 case I_FRAME_MAX_QP_H264: 171 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 172 case I_FRAME_MAX_QP_HEVC: 173 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 174 case P_FRAME_MAX_QP_H264: 175 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 176 case P_FRAME_MAX_QP_HEVC: 177 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 178 case B_FRAME_MAX_QP_H264: 179 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 180 case B_FRAME_MAX_QP_HEVC: 181 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 182 case I_FRAME_QP_H264: 183 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 184 case I_FRAME_QP_HEVC: 185 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 186 case P_FRAME_QP_H264: 187 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 188 case P_FRAME_QP_HEVC: 189 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 190 case B_FRAME_QP_H264: 191 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 192 case B_FRAME_QP_HEVC: 193 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 194 case PROFILE_AV1: 195 return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; 196 case LEVEL_AV1: 197 return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; 198 case ROTATION: 199 return V4L2_CID_ROTATE; 200 default: 201 return 0; 202 } 203 } 204 205 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 206 { 207 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 208 enum platform_inst_fw_cap_type cap_id; 209 struct platform_inst_fw_cap *cap; 210 struct vb2_queue *q; 211 212 cap = &inst->fw_caps[0]; 213 cap_id = iris_get_cap_id(ctrl->id); 214 if (!iris_valid_cap_id(cap_id)) 215 return -EINVAL; 216 217 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 218 if (vb2_is_streaming(q) && 219 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 220 return -EINVAL; 221 222 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 223 224 inst->fw_caps[cap_id].value = ctrl->val; 225 226 if (vb2_is_streaming(q)) { 227 if (cap[cap_id].set) 228 cap[cap_id].set(inst, cap_id); 229 } 230 231 return 0; 232 } 233 234 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 235 .s_ctrl = iris_op_s_ctrl, 236 }; 237 238 int iris_ctrls_init(struct iris_inst *inst) 239 { 240 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 241 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 242 u32 v4l2_id; 243 int ret; 244 245 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 246 if (iris_get_v4l2_id(cap[idx].cap_id)) 247 num_ctrls++; 248 } 249 250 /* Adding 1 to num_ctrls to include 251 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 252 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 253 */ 254 255 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 256 if (ret) 257 return ret; 258 259 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 260 struct v4l2_ctrl *ctrl; 261 262 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 263 if (!v4l2_id) 264 continue; 265 266 if (ctrl_idx >= num_ctrls) { 267 ret = -EINVAL; 268 goto error; 269 } 270 271 if (cap[idx].flags & CAP_FLAG_MENU) { 272 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 273 &iris_ctrl_ops, 274 v4l2_id, 275 cap[idx].max, 276 ~(cap[idx].step_or_mask), 277 cap[idx].value); 278 } else { 279 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 280 &iris_ctrl_ops, 281 v4l2_id, 282 cap[idx].min, 283 cap[idx].max, 284 cap[idx].step_or_mask, 285 cap[idx].value); 286 } 287 if (!ctrl) { 288 ret = -EINVAL; 289 goto error; 290 } 291 292 ctrl_idx++; 293 } 294 295 if (inst->domain == DECODER) { 296 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 297 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 298 } else { 299 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 300 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 301 } 302 303 ret = inst->ctrl_handler.error; 304 if (ret) 305 goto error; 306 307 return 0; 308 error: 309 v4l2_ctrl_handler_free(&inst->ctrl_handler); 310 311 return ret; 312 } 313 314 void iris_session_init_caps(struct iris_core *core) 315 { 316 const struct platform_inst_fw_cap *caps; 317 u32 i, num_cap, cap_id; 318 319 caps = core->iris_platform_data->inst_fw_caps_dec; 320 num_cap = core->iris_platform_data->inst_fw_caps_dec_size; 321 322 for (i = 0; i < num_cap; i++) { 323 cap_id = caps[i].cap_id; 324 if (!iris_valid_cap_id(cap_id)) 325 continue; 326 327 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 328 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 329 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 330 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 331 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 332 333 if (cap_id == PIPE) { 334 core->inst_fw_caps_dec[cap_id].value = 335 core->iris_platform_data->num_vpp_pipe; 336 core->inst_fw_caps_dec[cap_id].min = 337 core->iris_platform_data->num_vpp_pipe; 338 core->inst_fw_caps_dec[cap_id].max = 339 core->iris_platform_data->num_vpp_pipe; 340 } else { 341 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 342 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 343 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 344 } 345 } 346 347 caps = core->iris_platform_data->inst_fw_caps_enc; 348 num_cap = core->iris_platform_data->inst_fw_caps_enc_size; 349 350 for (i = 0; i < num_cap; i++) { 351 cap_id = caps[i].cap_id; 352 if (!iris_valid_cap_id(cap_id)) 353 continue; 354 355 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 356 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 357 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 358 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 359 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 360 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 361 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 362 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 363 } 364 } 365 366 static u32 iris_get_port_info(struct iris_inst *inst, 367 enum platform_inst_fw_cap_type cap_id) 368 { 369 if (inst->domain == DECODER) { 370 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 371 return HFI_PORT_BITSTREAM; 372 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 373 return HFI_PORT_RAW; 374 } else { 375 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 376 return HFI_PORT_RAW; 377 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 378 return HFI_PORT_BITSTREAM; 379 } 380 381 return HFI_PORT_NONE; 382 } 383 384 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 385 { 386 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 387 u32 hfi_value = inst->fw_caps[cap_id].value; 388 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 389 390 return hfi_ops->session_set_property(inst, hfi_id, 391 HFI_HOST_FLAGS_NONE, 392 iris_get_port_info(inst, cap_id), 393 HFI_PAYLOAD_U32_ENUM, 394 &hfi_value, sizeof(u32)); 395 } 396 397 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 398 { 399 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 400 u32 hfi_value = inst->fw_caps[cap_id].value; 401 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 402 403 return hfi_ops->session_set_property(inst, hfi_id, 404 HFI_HOST_FLAGS_NONE, 405 iris_get_port_info(inst, cap_id), 406 HFI_PAYLOAD_U32, 407 &hfi_value, sizeof(u32)); 408 } 409 410 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 411 { 412 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 413 struct v4l2_format *inp_f = inst->fmt_src; 414 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 415 u32 height = inp_f->fmt.pix_mp.height; 416 u32 width = inp_f->fmt.pix_mp.width; 417 u32 work_mode = STAGE_2; 418 419 if (inst->domain == DECODER) { 420 if (iris_res_is_less_than(width, height, 1280, 720)) 421 work_mode = STAGE_1; 422 } 423 424 return hfi_ops->session_set_property(inst, hfi_id, 425 HFI_HOST_FLAGS_NONE, 426 iris_get_port_info(inst, cap_id), 427 HFI_PAYLOAD_U32, 428 &work_mode, sizeof(u32)); 429 } 430 431 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 432 { 433 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 434 u32 work_route = inst->fw_caps[PIPE].value; 435 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 436 437 return hfi_ops->session_set_property(inst, hfi_id, 438 HFI_HOST_FLAGS_NONE, 439 iris_get_port_info(inst, cap_id), 440 HFI_PAYLOAD_U32, 441 &work_route, sizeof(u32)); 442 } 443 444 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 445 { 446 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 447 u32 hfi_id, hfi_value; 448 449 if (inst->codec == V4L2_PIX_FMT_H264) { 450 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 451 hfi_value = inst->fw_caps[PROFILE_H264].value; 452 } else { 453 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 454 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 455 } 456 457 return hfi_ops->session_set_property(inst, hfi_id, 458 HFI_HOST_FLAGS_NONE, 459 iris_get_port_info(inst, cap_id), 460 HFI_PAYLOAD_U32_ENUM, 461 &hfi_value, sizeof(u32)); 462 } 463 464 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 465 { 466 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 467 u32 hfi_id, hfi_value; 468 469 if (inst->codec == V4L2_PIX_FMT_H264) { 470 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 471 hfi_value = inst->fw_caps[LEVEL_H264].value; 472 } else { 473 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 474 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 475 } 476 477 return hfi_ops->session_set_property(inst, hfi_id, 478 HFI_HOST_FLAGS_NONE, 479 iris_get_port_info(inst, cap_id), 480 HFI_PAYLOAD_U32_ENUM, 481 &hfi_value, sizeof(u32)); 482 } 483 484 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 485 { 486 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 487 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 488 struct hfi_profile_level pl; 489 490 if (inst->codec == V4L2_PIX_FMT_H264) { 491 pl.profile = inst->fw_caps[PROFILE_H264].value; 492 pl.level = inst->fw_caps[LEVEL_H264].value; 493 } else { 494 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 495 pl.level = inst->fw_caps[LEVEL_HEVC].value; 496 } 497 498 return hfi_ops->session_set_property(inst, hfi_id, 499 HFI_HOST_FLAGS_NONE, 500 iris_get_port_info(inst, cap_id), 501 HFI_PAYLOAD_U32_ENUM, 502 &pl, sizeof(u32)); 503 } 504 505 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 506 { 507 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 508 u32 header_mode = inst->fw_caps[cap_id].value; 509 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 510 u32 hfi_val; 511 512 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 513 hfi_val = 0; 514 else 515 hfi_val = 1; 516 517 return hfi_ops->session_set_property(inst, hfi_id, 518 HFI_HOST_FLAGS_NONE, 519 iris_get_port_info(inst, cap_id), 520 HFI_PAYLOAD_U32, 521 &hfi_val, sizeof(u32)); 522 } 523 524 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 525 { 526 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 527 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 528 u32 header_mode = inst->fw_caps[cap_id].value; 529 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 530 u32 hfi_val; 531 532 if (prepend_sps_pps) 533 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 534 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 535 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 536 else 537 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 538 539 return hfi_ops->session_set_property(inst, hfi_id, 540 HFI_HOST_FLAGS_NONE, 541 iris_get_port_info(inst, cap_id), 542 HFI_PAYLOAD_U32_ENUM, 543 &hfi_val, sizeof(u32)); 544 } 545 546 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 547 { 548 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 549 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 550 u32 bitrate = inst->fw_caps[cap_id].value; 551 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 552 u32 max_bitrate; 553 554 if (inst->codec == V4L2_PIX_FMT_HEVC) 555 max_bitrate = CABAC_MAX_BITRATE; 556 557 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 558 max_bitrate = CABAC_MAX_BITRATE; 559 else 560 max_bitrate = CAVLC_MAX_BITRATE; 561 562 bitrate = min(bitrate, max_bitrate); 563 564 return hfi_ops->session_set_property(inst, hfi_id, 565 HFI_HOST_FLAGS_NONE, 566 iris_get_port_info(inst, cap_id), 567 HFI_PAYLOAD_U32, 568 &bitrate, sizeof(u32)); 569 } 570 571 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 572 { 573 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 574 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 575 u32 peak_bitrate = inst->fw_caps[cap_id].value; 576 u32 bitrate = inst->fw_caps[BITRATE].value; 577 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 578 579 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 580 return 0; 581 582 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 583 if (peak_bitrate < bitrate) 584 peak_bitrate = bitrate; 585 } else { 586 peak_bitrate = bitrate; 587 } 588 589 inst->fw_caps[cap_id].value = peak_bitrate; 590 591 return hfi_ops->session_set_property(inst, hfi_id, 592 HFI_HOST_FLAGS_NONE, 593 iris_get_port_info(inst, cap_id), 594 HFI_PAYLOAD_U32, 595 &peak_bitrate, sizeof(u32)); 596 } 597 598 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 599 { 600 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 601 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 602 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 603 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 604 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 605 u32 rc_mode = 0; 606 607 if (!frame_rc) 608 rc_mode = HFI_RATE_CONTROL_OFF; 609 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 610 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 611 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 612 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 613 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 614 rc_mode = HFI_RATE_CONTROL_CQ; 615 616 inst->hfi_rc_type = rc_mode; 617 618 return hfi_ops->session_set_property(inst, hfi_id, 619 HFI_HOST_FLAGS_NONE, 620 iris_get_port_info(inst, cap_id), 621 HFI_PAYLOAD_U32_ENUM, 622 &rc_mode, sizeof(u32)); 623 } 624 625 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 626 { 627 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 628 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 629 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 630 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 631 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 632 u32 rc_mode = 0; 633 634 if (!frame_rc) 635 rc_mode = HFI_RC_OFF; 636 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 637 rc_mode = HFI_RC_VBR_CFR; 638 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 639 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 640 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 641 rc_mode = HFI_RC_CQ; 642 643 inst->hfi_rc_type = rc_mode; 644 645 return hfi_ops->session_set_property(inst, hfi_id, 646 HFI_HOST_FLAGS_NONE, 647 iris_get_port_info(inst, cap_id), 648 HFI_PAYLOAD_U32_ENUM, 649 &rc_mode, sizeof(u32)); 650 } 651 652 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 653 { 654 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 655 u32 entropy_mode = inst->fw_caps[cap_id].value; 656 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 657 u32 hfi_val; 658 659 if (inst->codec != V4L2_PIX_FMT_H264) 660 return 0; 661 662 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 663 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 664 665 return hfi_ops->session_set_property(inst, hfi_id, 666 HFI_HOST_FLAGS_NONE, 667 iris_get_port_info(inst, cap_id), 668 HFI_PAYLOAD_U32, 669 &hfi_val, sizeof(u32)); 670 } 671 672 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 673 { 674 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 675 u32 entropy_mode = inst->fw_caps[cap_id].value; 676 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 677 u32 profile; 678 679 if (inst->codec != V4L2_PIX_FMT_H264) 680 return 0; 681 682 profile = inst->fw_caps[PROFILE_H264].value; 683 684 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 685 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 686 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 687 688 inst->fw_caps[cap_id].value = entropy_mode; 689 690 return hfi_ops->session_set_property(inst, hfi_id, 691 HFI_HOST_FLAGS_NONE, 692 iris_get_port_info(inst, cap_id), 693 HFI_PAYLOAD_U32, 694 &entropy_mode, sizeof(u32)); 695 } 696 697 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 698 { 699 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 700 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 701 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 702 u32 min_qp_enable = 0, client_qp_enable = 0; 703 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 704 u32 hfi_val; 705 706 if (inst->codec == V4L2_PIX_FMT_H264) { 707 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 708 min_qp_enable = 1; 709 if (min_qp_enable || 710 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 711 i_qp_enable = 1; 712 if (min_qp_enable || 713 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 714 p_qp_enable = 1; 715 if (min_qp_enable || 716 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 717 b_qp_enable = 1; 718 } else { 719 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 720 min_qp_enable = 1; 721 if (min_qp_enable || 722 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 723 i_qp_enable = 1; 724 if (min_qp_enable || 725 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 726 p_qp_enable = 1; 727 if (min_qp_enable || 728 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 729 b_qp_enable = 1; 730 } 731 732 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 733 if (!client_qp_enable) 734 return 0; 735 736 if (inst->codec == V4L2_PIX_FMT_H264) { 737 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 738 inst->fw_caps[MIN_FRAME_QP_H264].value); 739 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 740 inst->fw_caps[MIN_FRAME_QP_H264].value); 741 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 742 inst->fw_caps[MIN_FRAME_QP_H264].value); 743 } else { 744 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 745 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 746 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 747 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 748 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 749 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 750 } 751 752 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 753 754 return hfi_ops->session_set_property(inst, hfi_id, 755 HFI_HOST_FLAGS_NONE, 756 iris_get_port_info(inst, cap_id), 757 HFI_PAYLOAD_32_PACKED, 758 &hfi_val, sizeof(u32)); 759 } 760 761 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 762 { 763 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 764 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 765 u32 max_qp_enable = 0, client_qp_enable; 766 u32 i_frame_qp, p_frame_qp, b_frame_qp; 767 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 768 u32 hfi_val; 769 770 if (inst->codec == V4L2_PIX_FMT_H264) { 771 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 772 max_qp_enable = 1; 773 if (max_qp_enable || 774 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 775 i_qp_enable = 1; 776 if (max_qp_enable || 777 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 778 p_qp_enable = 1; 779 if (max_qp_enable || 780 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 781 b_qp_enable = 1; 782 } else { 783 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 784 max_qp_enable = 1; 785 if (max_qp_enable || 786 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 787 i_qp_enable = 1; 788 if (max_qp_enable || 789 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 790 p_qp_enable = 1; 791 if (max_qp_enable || 792 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 793 b_qp_enable = 1; 794 } 795 796 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 797 if (!client_qp_enable) 798 return 0; 799 800 if (inst->codec == V4L2_PIX_FMT_H264) { 801 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 802 inst->fw_caps[MAX_FRAME_QP_H264].value); 803 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 804 inst->fw_caps[MAX_FRAME_QP_H264].value); 805 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 806 inst->fw_caps[MAX_FRAME_QP_H264].value); 807 } else { 808 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 809 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 810 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 811 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 812 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 813 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 814 } 815 816 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 817 client_qp_enable << 24; 818 819 return hfi_ops->session_set_property(inst, hfi_id, 820 HFI_HOST_FLAGS_NONE, 821 iris_get_port_info(inst, cap_id), 822 HFI_PAYLOAD_32_PACKED, 823 &hfi_val, sizeof(u32)); 824 } 825 826 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 827 { 828 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 829 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 830 u32 i_frame_qp, p_frame_qp, b_frame_qp; 831 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 832 struct vb2_queue *q; 833 u32 hfi_val; 834 835 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 836 if (vb2_is_streaming(q)) { 837 if (inst->hfi_rc_type != HFI_RC_OFF) 838 return 0; 839 } 840 841 if (inst->hfi_rc_type == HFI_RC_OFF) { 842 i_qp_enable = 1; 843 p_qp_enable = 1; 844 b_qp_enable = 1; 845 } else { 846 if (inst->codec == V4L2_PIX_FMT_H264) { 847 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 848 i_qp_enable = 1; 849 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 850 p_qp_enable = 1; 851 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 852 b_qp_enable = 1; 853 } else { 854 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 855 i_qp_enable = 1; 856 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 857 p_qp_enable = 1; 858 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 859 b_qp_enable = 1; 860 } 861 } 862 863 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 864 if (!client_qp_enable) 865 return 0; 866 867 if (inst->codec == V4L2_PIX_FMT_H264) { 868 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 869 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 870 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 871 } else { 872 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 873 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 874 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 875 } 876 877 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 878 client_qp_enable << 24; 879 880 return hfi_ops->session_set_property(inst, hfi_id, 881 HFI_HOST_FLAGS_NONE, 882 iris_get_port_info(inst, cap_id), 883 HFI_PAYLOAD_32_PACKED, 884 &hfi_val, sizeof(u32)); 885 } 886 887 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 888 { 889 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 890 struct hfi_quantization_range_v2 range; 891 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 892 893 if (inst->codec == V4L2_PIX_FMT_HEVC) { 894 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 895 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 896 } else { 897 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 898 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 899 } 900 901 return hfi_ops->session_set_property(inst, hfi_id, 902 HFI_HOST_FLAGS_NONE, 903 iris_get_port_info(inst, cap_id), 904 HFI_PAYLOAD_32_PACKED, 905 &range, sizeof(range)); 906 } 907 908 int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 909 { 910 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 911 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 912 u32 hfi_val; 913 914 switch (inst->fw_caps[cap_id].value) { 915 case 0: 916 hfi_val = HFI_ROTATION_NONE; 917 return 0; 918 case 90: 919 hfi_val = HFI_ROTATION_90; 920 break; 921 case 180: 922 hfi_val = HFI_ROTATION_180; 923 break; 924 case 270: 925 hfi_val = HFI_ROTATION_270; 926 break; 927 default: 928 return -EINVAL; 929 } 930 931 return hfi_ops->session_set_property(inst, hfi_id, 932 HFI_HOST_FLAGS_NONE, 933 iris_get_port_info(inst, cap_id), 934 HFI_PAYLOAD_U32, 935 &hfi_val, sizeof(u32)); 936 } 937 938 int iris_set_properties(struct iris_inst *inst, u32 plane) 939 { 940 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 941 struct platform_inst_fw_cap *cap; 942 int ret; 943 u32 i; 944 945 ret = hfi_ops->session_set_config_params(inst, plane); 946 if (ret) 947 return ret; 948 949 for (i = 1; i < INST_FW_CAP_MAX; i++) { 950 cap = &inst->fw_caps[i]; 951 if (!iris_valid_cap_id(cap->cap_id)) 952 continue; 953 954 if (cap->cap_id && cap->set) 955 cap->set(inst, i); 956 } 957 958 return 0; 959 } 960