1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: 102 return PROFILE_AV1; 103 case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: 104 return LEVEL_AV1; 105 default: 106 return INST_FW_CAP_MAX; 107 } 108 } 109 110 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 111 { 112 if (!iris_valid_cap_id(cap_id)) 113 return 0; 114 115 switch (cap_id) { 116 case PROFILE_H264: 117 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 118 case PROFILE_HEVC: 119 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 120 case PROFILE_VP9: 121 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 122 case LEVEL_H264: 123 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 124 case LEVEL_HEVC: 125 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 126 case LEVEL_VP9: 127 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 128 case TIER: 129 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 130 case HEADER_MODE: 131 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 132 case PREPEND_SPSPPS_TO_IDR: 133 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 134 case BITRATE: 135 return V4L2_CID_MPEG_VIDEO_BITRATE; 136 case BITRATE_PEAK: 137 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 138 case BITRATE_MODE: 139 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 140 case FRAME_SKIP_MODE: 141 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 142 case FRAME_RC_ENABLE: 143 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 144 case GOP_SIZE: 145 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 146 case ENTROPY_MODE: 147 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 148 case MIN_FRAME_QP_H264: 149 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 150 case MIN_FRAME_QP_HEVC: 151 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 152 case MAX_FRAME_QP_H264: 153 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 154 case MAX_FRAME_QP_HEVC: 155 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 156 case I_FRAME_MIN_QP_H264: 157 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 158 case I_FRAME_MIN_QP_HEVC: 159 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 160 case P_FRAME_MIN_QP_H264: 161 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 162 case P_FRAME_MIN_QP_HEVC: 163 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 164 case B_FRAME_MIN_QP_H264: 165 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 166 case B_FRAME_MIN_QP_HEVC: 167 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 168 case I_FRAME_MAX_QP_H264: 169 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 170 case I_FRAME_MAX_QP_HEVC: 171 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 172 case P_FRAME_MAX_QP_H264: 173 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 174 case P_FRAME_MAX_QP_HEVC: 175 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 176 case B_FRAME_MAX_QP_H264: 177 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 178 case B_FRAME_MAX_QP_HEVC: 179 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 180 case I_FRAME_QP_H264: 181 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 182 case I_FRAME_QP_HEVC: 183 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 184 case P_FRAME_QP_H264: 185 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 186 case P_FRAME_QP_HEVC: 187 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 188 case B_FRAME_QP_H264: 189 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 190 case B_FRAME_QP_HEVC: 191 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 192 case PROFILE_AV1: 193 return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; 194 case LEVEL_AV1: 195 return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; 196 default: 197 return 0; 198 } 199 } 200 201 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 202 { 203 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 204 enum platform_inst_fw_cap_type cap_id; 205 struct platform_inst_fw_cap *cap; 206 struct vb2_queue *q; 207 208 cap = &inst->fw_caps[0]; 209 cap_id = iris_get_cap_id(ctrl->id); 210 if (!iris_valid_cap_id(cap_id)) 211 return -EINVAL; 212 213 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 214 if (vb2_is_streaming(q) && 215 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 216 return -EINVAL; 217 218 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 219 220 inst->fw_caps[cap_id].value = ctrl->val; 221 222 if (vb2_is_streaming(q)) { 223 if (cap[cap_id].set) 224 cap[cap_id].set(inst, cap_id); 225 } 226 227 return 0; 228 } 229 230 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 231 .s_ctrl = iris_op_s_ctrl, 232 }; 233 234 int iris_ctrls_init(struct iris_inst *inst) 235 { 236 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 237 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 238 u32 v4l2_id; 239 int ret; 240 241 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 242 if (iris_get_v4l2_id(cap[idx].cap_id)) 243 num_ctrls++; 244 } 245 246 /* Adding 1 to num_ctrls to include 247 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 248 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 249 */ 250 251 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 252 if (ret) 253 return ret; 254 255 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 256 struct v4l2_ctrl *ctrl; 257 258 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 259 if (!v4l2_id) 260 continue; 261 262 if (ctrl_idx >= num_ctrls) { 263 ret = -EINVAL; 264 goto error; 265 } 266 267 if (cap[idx].flags & CAP_FLAG_MENU) { 268 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 269 &iris_ctrl_ops, 270 v4l2_id, 271 cap[idx].max, 272 ~(cap[idx].step_or_mask), 273 cap[idx].value); 274 } else { 275 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 276 &iris_ctrl_ops, 277 v4l2_id, 278 cap[idx].min, 279 cap[idx].max, 280 cap[idx].step_or_mask, 281 cap[idx].value); 282 } 283 if (!ctrl) { 284 ret = -EINVAL; 285 goto error; 286 } 287 288 ctrl_idx++; 289 } 290 291 if (inst->domain == DECODER) { 292 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 293 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 294 } else { 295 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 296 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 297 } 298 299 ret = inst->ctrl_handler.error; 300 if (ret) 301 goto error; 302 303 return 0; 304 error: 305 v4l2_ctrl_handler_free(&inst->ctrl_handler); 306 307 return ret; 308 } 309 310 void iris_session_init_caps(struct iris_core *core) 311 { 312 const struct platform_inst_fw_cap *caps; 313 u32 i, num_cap, cap_id; 314 315 caps = core->iris_platform_data->inst_fw_caps_dec; 316 num_cap = core->iris_platform_data->inst_fw_caps_dec_size; 317 318 for (i = 0; i < num_cap; i++) { 319 cap_id = caps[i].cap_id; 320 if (!iris_valid_cap_id(cap_id)) 321 continue; 322 323 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 324 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 325 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 326 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 327 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 328 329 if (cap_id == PIPE) { 330 core->inst_fw_caps_dec[cap_id].value = 331 core->iris_platform_data->num_vpp_pipe; 332 core->inst_fw_caps_dec[cap_id].min = 333 core->iris_platform_data->num_vpp_pipe; 334 core->inst_fw_caps_dec[cap_id].max = 335 core->iris_platform_data->num_vpp_pipe; 336 } else { 337 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 338 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 339 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 340 } 341 } 342 343 caps = core->iris_platform_data->inst_fw_caps_enc; 344 num_cap = core->iris_platform_data->inst_fw_caps_enc_size; 345 346 for (i = 0; i < num_cap; i++) { 347 cap_id = caps[i].cap_id; 348 if (!iris_valid_cap_id(cap_id)) 349 continue; 350 351 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 352 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 353 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 354 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 355 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 356 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 357 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 358 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 359 } 360 } 361 362 static u32 iris_get_port_info(struct iris_inst *inst, 363 enum platform_inst_fw_cap_type cap_id) 364 { 365 if (inst->domain == DECODER) { 366 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 367 return HFI_PORT_BITSTREAM; 368 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 369 return HFI_PORT_RAW; 370 } else { 371 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 372 return HFI_PORT_RAW; 373 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 374 return HFI_PORT_BITSTREAM; 375 } 376 377 return HFI_PORT_NONE; 378 } 379 380 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 381 { 382 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 383 u32 hfi_value = inst->fw_caps[cap_id].value; 384 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 385 386 return hfi_ops->session_set_property(inst, hfi_id, 387 HFI_HOST_FLAGS_NONE, 388 iris_get_port_info(inst, cap_id), 389 HFI_PAYLOAD_U32_ENUM, 390 &hfi_value, sizeof(u32)); 391 } 392 393 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 394 { 395 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 396 u32 hfi_value = inst->fw_caps[cap_id].value; 397 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 398 399 return hfi_ops->session_set_property(inst, hfi_id, 400 HFI_HOST_FLAGS_NONE, 401 iris_get_port_info(inst, cap_id), 402 HFI_PAYLOAD_U32, 403 &hfi_value, sizeof(u32)); 404 } 405 406 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 407 { 408 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 409 struct v4l2_format *inp_f = inst->fmt_src; 410 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 411 u32 height = inp_f->fmt.pix_mp.height; 412 u32 width = inp_f->fmt.pix_mp.width; 413 u32 work_mode = STAGE_2; 414 415 if (inst->domain == DECODER) { 416 if (iris_res_is_less_than(width, height, 1280, 720)) 417 work_mode = STAGE_1; 418 } 419 420 return hfi_ops->session_set_property(inst, hfi_id, 421 HFI_HOST_FLAGS_NONE, 422 iris_get_port_info(inst, cap_id), 423 HFI_PAYLOAD_U32, 424 &work_mode, sizeof(u32)); 425 } 426 427 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 428 { 429 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 430 u32 work_route = inst->fw_caps[PIPE].value; 431 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 432 433 return hfi_ops->session_set_property(inst, hfi_id, 434 HFI_HOST_FLAGS_NONE, 435 iris_get_port_info(inst, cap_id), 436 HFI_PAYLOAD_U32, 437 &work_route, sizeof(u32)); 438 } 439 440 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 441 { 442 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 443 u32 hfi_id, hfi_value; 444 445 if (inst->codec == V4L2_PIX_FMT_H264) { 446 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 447 hfi_value = inst->fw_caps[PROFILE_H264].value; 448 } else { 449 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 450 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 451 } 452 453 return hfi_ops->session_set_property(inst, hfi_id, 454 HFI_HOST_FLAGS_NONE, 455 iris_get_port_info(inst, cap_id), 456 HFI_PAYLOAD_U32_ENUM, 457 &hfi_value, sizeof(u32)); 458 } 459 460 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 461 { 462 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 463 u32 hfi_id, hfi_value; 464 465 if (inst->codec == V4L2_PIX_FMT_H264) { 466 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 467 hfi_value = inst->fw_caps[LEVEL_H264].value; 468 } else { 469 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 470 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 471 } 472 473 return hfi_ops->session_set_property(inst, hfi_id, 474 HFI_HOST_FLAGS_NONE, 475 iris_get_port_info(inst, cap_id), 476 HFI_PAYLOAD_U32_ENUM, 477 &hfi_value, sizeof(u32)); 478 } 479 480 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 481 { 482 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 483 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 484 struct hfi_profile_level pl; 485 486 if (inst->codec == V4L2_PIX_FMT_H264) { 487 pl.profile = inst->fw_caps[PROFILE_H264].value; 488 pl.level = inst->fw_caps[LEVEL_H264].value; 489 } else { 490 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 491 pl.level = inst->fw_caps[LEVEL_HEVC].value; 492 } 493 494 return hfi_ops->session_set_property(inst, hfi_id, 495 HFI_HOST_FLAGS_NONE, 496 iris_get_port_info(inst, cap_id), 497 HFI_PAYLOAD_U32_ENUM, 498 &pl, sizeof(u32)); 499 } 500 501 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 502 { 503 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 504 u32 header_mode = inst->fw_caps[cap_id].value; 505 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 506 u32 hfi_val; 507 508 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 509 hfi_val = 0; 510 else 511 hfi_val = 1; 512 513 return hfi_ops->session_set_property(inst, hfi_id, 514 HFI_HOST_FLAGS_NONE, 515 iris_get_port_info(inst, cap_id), 516 HFI_PAYLOAD_U32, 517 &hfi_val, sizeof(u32)); 518 } 519 520 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 521 { 522 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 523 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 524 u32 header_mode = inst->fw_caps[cap_id].value; 525 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 526 u32 hfi_val; 527 528 if (prepend_sps_pps) 529 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 530 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 531 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 532 else 533 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 534 535 return hfi_ops->session_set_property(inst, hfi_id, 536 HFI_HOST_FLAGS_NONE, 537 iris_get_port_info(inst, cap_id), 538 HFI_PAYLOAD_U32_ENUM, 539 &hfi_val, sizeof(u32)); 540 } 541 542 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 543 { 544 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 545 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 546 u32 bitrate = inst->fw_caps[cap_id].value; 547 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 548 u32 max_bitrate; 549 550 if (inst->codec == V4L2_PIX_FMT_HEVC) 551 max_bitrate = CABAC_MAX_BITRATE; 552 553 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 554 max_bitrate = CABAC_MAX_BITRATE; 555 else 556 max_bitrate = CAVLC_MAX_BITRATE; 557 558 bitrate = min(bitrate, max_bitrate); 559 560 return hfi_ops->session_set_property(inst, hfi_id, 561 HFI_HOST_FLAGS_NONE, 562 iris_get_port_info(inst, cap_id), 563 HFI_PAYLOAD_U32, 564 &bitrate, sizeof(u32)); 565 } 566 567 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 568 { 569 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 570 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 571 u32 peak_bitrate = inst->fw_caps[cap_id].value; 572 u32 bitrate = inst->fw_caps[BITRATE].value; 573 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 574 575 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 576 return 0; 577 578 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 579 if (peak_bitrate < bitrate) 580 peak_bitrate = bitrate; 581 } else { 582 peak_bitrate = bitrate; 583 } 584 585 inst->fw_caps[cap_id].value = peak_bitrate; 586 587 return hfi_ops->session_set_property(inst, hfi_id, 588 HFI_HOST_FLAGS_NONE, 589 iris_get_port_info(inst, cap_id), 590 HFI_PAYLOAD_U32, 591 &peak_bitrate, sizeof(u32)); 592 } 593 594 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 595 { 596 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 597 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 598 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 599 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 600 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 601 u32 rc_mode = 0; 602 603 if (!frame_rc) 604 rc_mode = HFI_RATE_CONTROL_OFF; 605 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 606 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 607 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 608 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 609 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 610 rc_mode = HFI_RATE_CONTROL_CQ; 611 612 inst->hfi_rc_type = rc_mode; 613 614 return hfi_ops->session_set_property(inst, hfi_id, 615 HFI_HOST_FLAGS_NONE, 616 iris_get_port_info(inst, cap_id), 617 HFI_PAYLOAD_U32_ENUM, 618 &rc_mode, sizeof(u32)); 619 } 620 621 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 622 { 623 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 624 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 625 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 626 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 627 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 628 u32 rc_mode = 0; 629 630 if (!frame_rc) 631 rc_mode = HFI_RC_OFF; 632 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 633 rc_mode = HFI_RC_VBR_CFR; 634 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 635 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 636 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 637 rc_mode = HFI_RC_CQ; 638 639 inst->hfi_rc_type = rc_mode; 640 641 return hfi_ops->session_set_property(inst, hfi_id, 642 HFI_HOST_FLAGS_NONE, 643 iris_get_port_info(inst, cap_id), 644 HFI_PAYLOAD_U32_ENUM, 645 &rc_mode, sizeof(u32)); 646 } 647 648 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 649 { 650 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 651 u32 entropy_mode = inst->fw_caps[cap_id].value; 652 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 653 u32 hfi_val; 654 655 if (inst->codec != V4L2_PIX_FMT_H264) 656 return 0; 657 658 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 659 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 660 661 return hfi_ops->session_set_property(inst, hfi_id, 662 HFI_HOST_FLAGS_NONE, 663 iris_get_port_info(inst, cap_id), 664 HFI_PAYLOAD_U32, 665 &hfi_val, sizeof(u32)); 666 } 667 668 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 669 { 670 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 671 u32 entropy_mode = inst->fw_caps[cap_id].value; 672 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 673 u32 profile; 674 675 if (inst->codec != V4L2_PIX_FMT_H264) 676 return 0; 677 678 profile = inst->fw_caps[PROFILE_H264].value; 679 680 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 681 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 682 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 683 684 inst->fw_caps[cap_id].value = entropy_mode; 685 686 return hfi_ops->session_set_property(inst, hfi_id, 687 HFI_HOST_FLAGS_NONE, 688 iris_get_port_info(inst, cap_id), 689 HFI_PAYLOAD_U32, 690 &entropy_mode, sizeof(u32)); 691 } 692 693 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 694 { 695 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 696 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 697 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 698 u32 min_qp_enable = 0, client_qp_enable = 0; 699 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 700 u32 hfi_val; 701 702 if (inst->codec == V4L2_PIX_FMT_H264) { 703 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 704 min_qp_enable = 1; 705 if (min_qp_enable || 706 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 707 i_qp_enable = 1; 708 if (min_qp_enable || 709 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 710 p_qp_enable = 1; 711 if (min_qp_enable || 712 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 713 b_qp_enable = 1; 714 } else { 715 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 716 min_qp_enable = 1; 717 if (min_qp_enable || 718 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 719 i_qp_enable = 1; 720 if (min_qp_enable || 721 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 722 p_qp_enable = 1; 723 if (min_qp_enable || 724 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 725 b_qp_enable = 1; 726 } 727 728 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 729 if (!client_qp_enable) 730 return 0; 731 732 if (inst->codec == V4L2_PIX_FMT_H264) { 733 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 734 inst->fw_caps[MIN_FRAME_QP_H264].value); 735 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 736 inst->fw_caps[MIN_FRAME_QP_H264].value); 737 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 738 inst->fw_caps[MIN_FRAME_QP_H264].value); 739 } else { 740 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 741 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 742 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 743 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 744 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 745 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 746 } 747 748 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 749 750 return hfi_ops->session_set_property(inst, hfi_id, 751 HFI_HOST_FLAGS_NONE, 752 iris_get_port_info(inst, cap_id), 753 HFI_PAYLOAD_32_PACKED, 754 &hfi_val, sizeof(u32)); 755 } 756 757 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 758 { 759 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 760 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 761 u32 max_qp_enable = 0, client_qp_enable; 762 u32 i_frame_qp, p_frame_qp, b_frame_qp; 763 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 764 u32 hfi_val; 765 766 if (inst->codec == V4L2_PIX_FMT_H264) { 767 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 768 max_qp_enable = 1; 769 if (max_qp_enable || 770 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 771 i_qp_enable = 1; 772 if (max_qp_enable || 773 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 774 p_qp_enable = 1; 775 if (max_qp_enable || 776 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 777 b_qp_enable = 1; 778 } else { 779 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 780 max_qp_enable = 1; 781 if (max_qp_enable || 782 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 783 i_qp_enable = 1; 784 if (max_qp_enable || 785 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 786 p_qp_enable = 1; 787 if (max_qp_enable || 788 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 789 b_qp_enable = 1; 790 } 791 792 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 793 if (!client_qp_enable) 794 return 0; 795 796 if (inst->codec == V4L2_PIX_FMT_H264) { 797 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 798 inst->fw_caps[MAX_FRAME_QP_H264].value); 799 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 800 inst->fw_caps[MAX_FRAME_QP_H264].value); 801 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 802 inst->fw_caps[MAX_FRAME_QP_H264].value); 803 } else { 804 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 805 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 806 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 807 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 808 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 809 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 810 } 811 812 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 813 client_qp_enable << 24; 814 815 return hfi_ops->session_set_property(inst, hfi_id, 816 HFI_HOST_FLAGS_NONE, 817 iris_get_port_info(inst, cap_id), 818 HFI_PAYLOAD_32_PACKED, 819 &hfi_val, sizeof(u32)); 820 } 821 822 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 823 { 824 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 825 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 826 u32 i_frame_qp, p_frame_qp, b_frame_qp; 827 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 828 struct vb2_queue *q; 829 u32 hfi_val; 830 831 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 832 if (vb2_is_streaming(q)) { 833 if (inst->hfi_rc_type != HFI_RC_OFF) 834 return 0; 835 } 836 837 if (inst->hfi_rc_type == HFI_RC_OFF) { 838 i_qp_enable = 1; 839 p_qp_enable = 1; 840 b_qp_enable = 1; 841 } else { 842 if (inst->codec == V4L2_PIX_FMT_H264) { 843 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 844 i_qp_enable = 1; 845 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 846 p_qp_enable = 1; 847 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 848 b_qp_enable = 1; 849 } else { 850 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 851 i_qp_enable = 1; 852 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 853 p_qp_enable = 1; 854 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 855 b_qp_enable = 1; 856 } 857 } 858 859 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 860 if (!client_qp_enable) 861 return 0; 862 863 if (inst->codec == V4L2_PIX_FMT_H264) { 864 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 865 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 866 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 867 } else { 868 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 869 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 870 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 871 } 872 873 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 874 client_qp_enable << 24; 875 876 return hfi_ops->session_set_property(inst, hfi_id, 877 HFI_HOST_FLAGS_NONE, 878 iris_get_port_info(inst, cap_id), 879 HFI_PAYLOAD_32_PACKED, 880 &hfi_val, sizeof(u32)); 881 } 882 883 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 884 { 885 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 886 struct hfi_quantization_range_v2 range; 887 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 888 889 if (inst->codec == V4L2_PIX_FMT_HEVC) { 890 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 891 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 892 } else { 893 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 894 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 895 } 896 897 return hfi_ops->session_set_property(inst, hfi_id, 898 HFI_HOST_FLAGS_NONE, 899 iris_get_port_info(inst, cap_id), 900 HFI_PAYLOAD_32_PACKED, 901 &range, sizeof(range)); 902 } 903 904 int iris_set_properties(struct iris_inst *inst, u32 plane) 905 { 906 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 907 struct platform_inst_fw_cap *cap; 908 int ret; 909 u32 i; 910 911 ret = hfi_ops->session_set_config_params(inst, plane); 912 if (ret) 913 return ret; 914 915 for (i = 1; i < INST_FW_CAP_MAX; i++) { 916 cap = &inst->fw_caps[i]; 917 if (!iris_valid_cap_id(cap->cap_id)) 918 continue; 919 920 if (cap->cap_id && cap->set) 921 cap->set(inst, i); 922 } 923 924 return 0; 925 } 926