1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: 102 return PROFILE_AV1; 103 case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: 104 return LEVEL_AV1; 105 case V4L2_CID_ROTATE: 106 return ROTATION; 107 case V4L2_CID_HFLIP: 108 return HFLIP; 109 case V4L2_CID_VFLIP: 110 return VFLIP; 111 case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: 112 return IR_TYPE; 113 case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD: 114 return IR_PERIOD; 115 default: 116 return INST_FW_CAP_MAX; 117 } 118 } 119 120 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 121 { 122 if (!iris_valid_cap_id(cap_id)) 123 return 0; 124 125 switch (cap_id) { 126 case PROFILE_H264: 127 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 128 case PROFILE_HEVC: 129 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 130 case PROFILE_VP9: 131 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 132 case LEVEL_H264: 133 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 134 case LEVEL_HEVC: 135 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 136 case LEVEL_VP9: 137 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 138 case TIER: 139 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 140 case HEADER_MODE: 141 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 142 case PREPEND_SPSPPS_TO_IDR: 143 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 144 case BITRATE: 145 return V4L2_CID_MPEG_VIDEO_BITRATE; 146 case BITRATE_PEAK: 147 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 148 case BITRATE_MODE: 149 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 150 case FRAME_SKIP_MODE: 151 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 152 case FRAME_RC_ENABLE: 153 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 154 case GOP_SIZE: 155 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 156 case ENTROPY_MODE: 157 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 158 case MIN_FRAME_QP_H264: 159 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 160 case MIN_FRAME_QP_HEVC: 161 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 162 case MAX_FRAME_QP_H264: 163 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 164 case MAX_FRAME_QP_HEVC: 165 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 166 case I_FRAME_MIN_QP_H264: 167 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 168 case I_FRAME_MIN_QP_HEVC: 169 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 170 case P_FRAME_MIN_QP_H264: 171 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 172 case P_FRAME_MIN_QP_HEVC: 173 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 174 case B_FRAME_MIN_QP_H264: 175 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 176 case B_FRAME_MIN_QP_HEVC: 177 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 178 case I_FRAME_MAX_QP_H264: 179 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 180 case I_FRAME_MAX_QP_HEVC: 181 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 182 case P_FRAME_MAX_QP_H264: 183 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 184 case P_FRAME_MAX_QP_HEVC: 185 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 186 case B_FRAME_MAX_QP_H264: 187 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 188 case B_FRAME_MAX_QP_HEVC: 189 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 190 case I_FRAME_QP_H264: 191 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 192 case I_FRAME_QP_HEVC: 193 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 194 case P_FRAME_QP_H264: 195 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 196 case P_FRAME_QP_HEVC: 197 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 198 case B_FRAME_QP_H264: 199 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 200 case B_FRAME_QP_HEVC: 201 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 202 case PROFILE_AV1: 203 return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; 204 case LEVEL_AV1: 205 return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; 206 case ROTATION: 207 return V4L2_CID_ROTATE; 208 case HFLIP: 209 return V4L2_CID_HFLIP; 210 case VFLIP: 211 return V4L2_CID_VFLIP; 212 case IR_TYPE: 213 return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE; 214 case IR_PERIOD: 215 return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD; 216 default: 217 return 0; 218 } 219 } 220 221 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 222 { 223 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 224 enum platform_inst_fw_cap_type cap_id; 225 struct platform_inst_fw_cap *cap; 226 struct vb2_queue *q; 227 228 cap = &inst->fw_caps[0]; 229 cap_id = iris_get_cap_id(ctrl->id); 230 if (!iris_valid_cap_id(cap_id)) 231 return -EINVAL; 232 233 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 234 if (vb2_is_streaming(q) && 235 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 236 return -EINVAL; 237 238 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 239 240 inst->fw_caps[cap_id].value = ctrl->val; 241 242 if (vb2_is_streaming(q)) { 243 if (cap[cap_id].set) 244 cap[cap_id].set(inst, cap_id); 245 } 246 247 return 0; 248 } 249 250 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 251 .s_ctrl = iris_op_s_ctrl, 252 }; 253 254 int iris_ctrls_init(struct iris_inst *inst) 255 { 256 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 257 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 258 u32 v4l2_id; 259 int ret; 260 261 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 262 if (iris_get_v4l2_id(cap[idx].cap_id)) 263 num_ctrls++; 264 } 265 266 /* Adding 1 to num_ctrls to include 267 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 268 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 269 */ 270 271 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 272 if (ret) 273 return ret; 274 275 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 276 struct v4l2_ctrl *ctrl; 277 278 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 279 if (!v4l2_id) 280 continue; 281 282 if (ctrl_idx >= num_ctrls) { 283 ret = -EINVAL; 284 goto error; 285 } 286 287 if (cap[idx].flags & CAP_FLAG_MENU) { 288 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 289 &iris_ctrl_ops, 290 v4l2_id, 291 cap[idx].max, 292 ~(cap[idx].step_or_mask), 293 cap[idx].value); 294 } else { 295 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 296 &iris_ctrl_ops, 297 v4l2_id, 298 cap[idx].min, 299 cap[idx].max, 300 cap[idx].step_or_mask, 301 cap[idx].value); 302 } 303 if (!ctrl) { 304 ret = -EINVAL; 305 goto error; 306 } 307 308 ctrl_idx++; 309 } 310 311 if (inst->domain == DECODER) { 312 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 313 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 314 } else { 315 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 316 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 317 } 318 319 ret = inst->ctrl_handler.error; 320 if (ret) 321 goto error; 322 323 return 0; 324 error: 325 v4l2_ctrl_handler_free(&inst->ctrl_handler); 326 327 return ret; 328 } 329 330 void iris_session_init_caps(struct iris_core *core) 331 { 332 const struct platform_inst_fw_cap *caps; 333 u32 i, num_cap, cap_id; 334 335 caps = core->iris_platform_data->inst_fw_caps_dec; 336 num_cap = core->iris_platform_data->inst_fw_caps_dec_size; 337 338 for (i = 0; i < num_cap; i++) { 339 cap_id = caps[i].cap_id; 340 if (!iris_valid_cap_id(cap_id)) 341 continue; 342 343 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 344 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 345 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 346 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 347 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 348 349 if (cap_id == PIPE) { 350 core->inst_fw_caps_dec[cap_id].value = 351 core->iris_platform_data->num_vpp_pipe; 352 core->inst_fw_caps_dec[cap_id].min = 353 core->iris_platform_data->num_vpp_pipe; 354 core->inst_fw_caps_dec[cap_id].max = 355 core->iris_platform_data->num_vpp_pipe; 356 } else { 357 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 358 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 359 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 360 } 361 } 362 363 caps = core->iris_platform_data->inst_fw_caps_enc; 364 num_cap = core->iris_platform_data->inst_fw_caps_enc_size; 365 366 for (i = 0; i < num_cap; i++) { 367 cap_id = caps[i].cap_id; 368 if (!iris_valid_cap_id(cap_id)) 369 continue; 370 371 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 372 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 373 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 374 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 375 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 376 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 377 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 378 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 379 } 380 } 381 382 static u32 iris_get_port_info(struct iris_inst *inst, 383 enum platform_inst_fw_cap_type cap_id) 384 { 385 if (inst->domain == DECODER) { 386 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 387 return HFI_PORT_BITSTREAM; 388 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 389 return HFI_PORT_RAW; 390 } else { 391 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 392 return HFI_PORT_RAW; 393 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 394 return HFI_PORT_BITSTREAM; 395 } 396 397 return HFI_PORT_NONE; 398 } 399 400 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 401 { 402 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 403 u32 hfi_value = inst->fw_caps[cap_id].value; 404 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 405 406 return hfi_ops->session_set_property(inst, hfi_id, 407 HFI_HOST_FLAGS_NONE, 408 iris_get_port_info(inst, cap_id), 409 HFI_PAYLOAD_U32_ENUM, 410 &hfi_value, sizeof(u32)); 411 } 412 413 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 414 { 415 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 416 u32 hfi_value = inst->fw_caps[cap_id].value; 417 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 418 419 return hfi_ops->session_set_property(inst, hfi_id, 420 HFI_HOST_FLAGS_NONE, 421 iris_get_port_info(inst, cap_id), 422 HFI_PAYLOAD_U32, 423 &hfi_value, sizeof(u32)); 424 } 425 426 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 427 { 428 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 429 struct v4l2_format *inp_f = inst->fmt_src; 430 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 431 u32 height = inp_f->fmt.pix_mp.height; 432 u32 width = inp_f->fmt.pix_mp.width; 433 u32 work_mode = STAGE_2; 434 435 if (inst->domain == DECODER) { 436 if (iris_res_is_less_than(width, height, 1280, 720)) 437 work_mode = STAGE_1; 438 } 439 440 return hfi_ops->session_set_property(inst, hfi_id, 441 HFI_HOST_FLAGS_NONE, 442 iris_get_port_info(inst, cap_id), 443 HFI_PAYLOAD_U32, 444 &work_mode, sizeof(u32)); 445 } 446 447 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 448 { 449 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 450 u32 work_route = inst->fw_caps[PIPE].value; 451 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 452 453 return hfi_ops->session_set_property(inst, hfi_id, 454 HFI_HOST_FLAGS_NONE, 455 iris_get_port_info(inst, cap_id), 456 HFI_PAYLOAD_U32, 457 &work_route, sizeof(u32)); 458 } 459 460 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 461 { 462 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 463 u32 hfi_id, hfi_value; 464 465 if (inst->codec == V4L2_PIX_FMT_H264) { 466 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 467 hfi_value = inst->fw_caps[PROFILE_H264].value; 468 } else { 469 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 470 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 471 } 472 473 return hfi_ops->session_set_property(inst, hfi_id, 474 HFI_HOST_FLAGS_NONE, 475 iris_get_port_info(inst, cap_id), 476 HFI_PAYLOAD_U32_ENUM, 477 &hfi_value, sizeof(u32)); 478 } 479 480 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 481 { 482 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 483 u32 hfi_id, hfi_value; 484 485 if (inst->codec == V4L2_PIX_FMT_H264) { 486 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 487 hfi_value = inst->fw_caps[LEVEL_H264].value; 488 } else { 489 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 490 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 491 } 492 493 return hfi_ops->session_set_property(inst, hfi_id, 494 HFI_HOST_FLAGS_NONE, 495 iris_get_port_info(inst, cap_id), 496 HFI_PAYLOAD_U32_ENUM, 497 &hfi_value, sizeof(u32)); 498 } 499 500 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 501 { 502 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 503 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 504 struct hfi_profile_level pl; 505 506 if (inst->codec == V4L2_PIX_FMT_H264) { 507 pl.profile = inst->fw_caps[PROFILE_H264].value; 508 pl.level = inst->fw_caps[LEVEL_H264].value; 509 } else { 510 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 511 pl.level = inst->fw_caps[LEVEL_HEVC].value; 512 } 513 514 return hfi_ops->session_set_property(inst, hfi_id, 515 HFI_HOST_FLAGS_NONE, 516 iris_get_port_info(inst, cap_id), 517 HFI_PAYLOAD_U32_ENUM, 518 &pl, sizeof(u32)); 519 } 520 521 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 522 { 523 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 524 u32 header_mode = inst->fw_caps[cap_id].value; 525 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 526 u32 hfi_val; 527 528 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 529 hfi_val = 0; 530 else 531 hfi_val = 1; 532 533 return hfi_ops->session_set_property(inst, hfi_id, 534 HFI_HOST_FLAGS_NONE, 535 iris_get_port_info(inst, cap_id), 536 HFI_PAYLOAD_U32, 537 &hfi_val, sizeof(u32)); 538 } 539 540 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 541 { 542 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 543 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 544 u32 header_mode = inst->fw_caps[cap_id].value; 545 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 546 u32 hfi_val; 547 548 if (prepend_sps_pps) 549 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 550 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 551 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 552 else 553 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 554 555 return hfi_ops->session_set_property(inst, hfi_id, 556 HFI_HOST_FLAGS_NONE, 557 iris_get_port_info(inst, cap_id), 558 HFI_PAYLOAD_U32_ENUM, 559 &hfi_val, sizeof(u32)); 560 } 561 562 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 563 { 564 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 565 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 566 u32 bitrate = inst->fw_caps[cap_id].value; 567 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 568 u32 max_bitrate; 569 570 if (inst->codec == V4L2_PIX_FMT_HEVC) 571 max_bitrate = CABAC_MAX_BITRATE; 572 573 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 574 max_bitrate = CABAC_MAX_BITRATE; 575 else 576 max_bitrate = CAVLC_MAX_BITRATE; 577 578 bitrate = min(bitrate, max_bitrate); 579 580 return hfi_ops->session_set_property(inst, hfi_id, 581 HFI_HOST_FLAGS_NONE, 582 iris_get_port_info(inst, cap_id), 583 HFI_PAYLOAD_U32, 584 &bitrate, sizeof(u32)); 585 } 586 587 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 588 { 589 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 590 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 591 u32 peak_bitrate = inst->fw_caps[cap_id].value; 592 u32 bitrate = inst->fw_caps[BITRATE].value; 593 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 594 595 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 596 return 0; 597 598 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 599 if (peak_bitrate < bitrate) 600 peak_bitrate = bitrate; 601 } else { 602 peak_bitrate = bitrate; 603 } 604 605 inst->fw_caps[cap_id].value = peak_bitrate; 606 607 return hfi_ops->session_set_property(inst, hfi_id, 608 HFI_HOST_FLAGS_NONE, 609 iris_get_port_info(inst, cap_id), 610 HFI_PAYLOAD_U32, 611 &peak_bitrate, sizeof(u32)); 612 } 613 614 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 615 { 616 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 617 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 618 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 619 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 620 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 621 u32 rc_mode = 0; 622 623 if (!frame_rc) 624 rc_mode = HFI_RATE_CONTROL_OFF; 625 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 626 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 627 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 628 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 629 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 630 rc_mode = HFI_RATE_CONTROL_CQ; 631 632 inst->hfi_rc_type = rc_mode; 633 634 return hfi_ops->session_set_property(inst, hfi_id, 635 HFI_HOST_FLAGS_NONE, 636 iris_get_port_info(inst, cap_id), 637 HFI_PAYLOAD_U32_ENUM, 638 &rc_mode, sizeof(u32)); 639 } 640 641 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 642 { 643 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 644 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 645 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 646 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 647 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 648 u32 rc_mode = 0; 649 650 if (!frame_rc) 651 rc_mode = HFI_RC_OFF; 652 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 653 rc_mode = HFI_RC_VBR_CFR; 654 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 655 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 656 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 657 rc_mode = HFI_RC_CQ; 658 659 inst->hfi_rc_type = rc_mode; 660 661 return hfi_ops->session_set_property(inst, hfi_id, 662 HFI_HOST_FLAGS_NONE, 663 iris_get_port_info(inst, cap_id), 664 HFI_PAYLOAD_U32_ENUM, 665 &rc_mode, sizeof(u32)); 666 } 667 668 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 669 { 670 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 671 u32 entropy_mode = inst->fw_caps[cap_id].value; 672 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 673 u32 hfi_val; 674 675 if (inst->codec != V4L2_PIX_FMT_H264) 676 return 0; 677 678 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 679 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 680 681 return hfi_ops->session_set_property(inst, hfi_id, 682 HFI_HOST_FLAGS_NONE, 683 iris_get_port_info(inst, cap_id), 684 HFI_PAYLOAD_U32, 685 &hfi_val, sizeof(u32)); 686 } 687 688 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 689 { 690 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 691 u32 entropy_mode = inst->fw_caps[cap_id].value; 692 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 693 u32 profile; 694 695 if (inst->codec != V4L2_PIX_FMT_H264) 696 return 0; 697 698 profile = inst->fw_caps[PROFILE_H264].value; 699 700 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 701 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 702 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 703 704 inst->fw_caps[cap_id].value = entropy_mode; 705 706 return hfi_ops->session_set_property(inst, hfi_id, 707 HFI_HOST_FLAGS_NONE, 708 iris_get_port_info(inst, cap_id), 709 HFI_PAYLOAD_U32, 710 &entropy_mode, sizeof(u32)); 711 } 712 713 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 714 { 715 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 716 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 717 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 718 u32 min_qp_enable = 0, client_qp_enable = 0; 719 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 720 u32 hfi_val; 721 722 if (inst->codec == V4L2_PIX_FMT_H264) { 723 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 724 min_qp_enable = 1; 725 if (min_qp_enable || 726 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 727 i_qp_enable = 1; 728 if (min_qp_enable || 729 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 730 p_qp_enable = 1; 731 if (min_qp_enable || 732 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 733 b_qp_enable = 1; 734 } else { 735 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 736 min_qp_enable = 1; 737 if (min_qp_enable || 738 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 739 i_qp_enable = 1; 740 if (min_qp_enable || 741 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 742 p_qp_enable = 1; 743 if (min_qp_enable || 744 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 745 b_qp_enable = 1; 746 } 747 748 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 749 if (!client_qp_enable) 750 return 0; 751 752 if (inst->codec == V4L2_PIX_FMT_H264) { 753 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 754 inst->fw_caps[MIN_FRAME_QP_H264].value); 755 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 756 inst->fw_caps[MIN_FRAME_QP_H264].value); 757 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 758 inst->fw_caps[MIN_FRAME_QP_H264].value); 759 } else { 760 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 761 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 762 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 763 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 764 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 765 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 766 } 767 768 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 769 770 return hfi_ops->session_set_property(inst, hfi_id, 771 HFI_HOST_FLAGS_NONE, 772 iris_get_port_info(inst, cap_id), 773 HFI_PAYLOAD_32_PACKED, 774 &hfi_val, sizeof(u32)); 775 } 776 777 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 778 { 779 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 780 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 781 u32 max_qp_enable = 0, client_qp_enable; 782 u32 i_frame_qp, p_frame_qp, b_frame_qp; 783 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 784 u32 hfi_val; 785 786 if (inst->codec == V4L2_PIX_FMT_H264) { 787 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 788 max_qp_enable = 1; 789 if (max_qp_enable || 790 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 791 i_qp_enable = 1; 792 if (max_qp_enable || 793 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 794 p_qp_enable = 1; 795 if (max_qp_enable || 796 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 797 b_qp_enable = 1; 798 } else { 799 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 800 max_qp_enable = 1; 801 if (max_qp_enable || 802 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 803 i_qp_enable = 1; 804 if (max_qp_enable || 805 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 806 p_qp_enable = 1; 807 if (max_qp_enable || 808 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 809 b_qp_enable = 1; 810 } 811 812 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 813 if (!client_qp_enable) 814 return 0; 815 816 if (inst->codec == V4L2_PIX_FMT_H264) { 817 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 818 inst->fw_caps[MAX_FRAME_QP_H264].value); 819 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 820 inst->fw_caps[MAX_FRAME_QP_H264].value); 821 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 822 inst->fw_caps[MAX_FRAME_QP_H264].value); 823 } else { 824 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 825 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 826 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 827 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 828 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 829 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 830 } 831 832 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 833 client_qp_enable << 24; 834 835 return hfi_ops->session_set_property(inst, hfi_id, 836 HFI_HOST_FLAGS_NONE, 837 iris_get_port_info(inst, cap_id), 838 HFI_PAYLOAD_32_PACKED, 839 &hfi_val, sizeof(u32)); 840 } 841 842 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 843 { 844 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 845 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 846 u32 i_frame_qp, p_frame_qp, b_frame_qp; 847 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 848 struct vb2_queue *q; 849 u32 hfi_val; 850 851 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 852 if (vb2_is_streaming(q)) { 853 if (inst->hfi_rc_type != HFI_RC_OFF) 854 return 0; 855 } 856 857 if (inst->hfi_rc_type == HFI_RC_OFF) { 858 i_qp_enable = 1; 859 p_qp_enable = 1; 860 b_qp_enable = 1; 861 } else { 862 if (inst->codec == V4L2_PIX_FMT_H264) { 863 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 864 i_qp_enable = 1; 865 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 866 p_qp_enable = 1; 867 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 868 b_qp_enable = 1; 869 } else { 870 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 871 i_qp_enable = 1; 872 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 873 p_qp_enable = 1; 874 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 875 b_qp_enable = 1; 876 } 877 } 878 879 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 880 if (!client_qp_enable) 881 return 0; 882 883 if (inst->codec == V4L2_PIX_FMT_H264) { 884 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 885 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 886 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 887 } else { 888 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 889 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 890 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 891 } 892 893 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 894 client_qp_enable << 24; 895 896 return hfi_ops->session_set_property(inst, hfi_id, 897 HFI_HOST_FLAGS_NONE, 898 iris_get_port_info(inst, cap_id), 899 HFI_PAYLOAD_32_PACKED, 900 &hfi_val, sizeof(u32)); 901 } 902 903 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 904 { 905 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 906 struct hfi_quantization_range_v2 range; 907 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 908 909 if (inst->codec == V4L2_PIX_FMT_HEVC) { 910 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 911 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 912 } else { 913 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 914 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 915 } 916 917 return hfi_ops->session_set_property(inst, hfi_id, 918 HFI_HOST_FLAGS_NONE, 919 iris_get_port_info(inst, cap_id), 920 HFI_PAYLOAD_32_PACKED, 921 &range, sizeof(range)); 922 } 923 924 int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 925 { 926 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 927 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 928 u32 hfi_val; 929 930 switch (inst->fw_caps[cap_id].value) { 931 case 0: 932 hfi_val = HFI_ROTATION_NONE; 933 return 0; 934 case 90: 935 hfi_val = HFI_ROTATION_90; 936 break; 937 case 180: 938 hfi_val = HFI_ROTATION_180; 939 break; 940 case 270: 941 hfi_val = HFI_ROTATION_270; 942 break; 943 default: 944 return -EINVAL; 945 } 946 947 return hfi_ops->session_set_property(inst, hfi_id, 948 HFI_HOST_FLAGS_NONE, 949 iris_get_port_info(inst, cap_id), 950 HFI_PAYLOAD_U32, 951 &hfi_val, sizeof(u32)); 952 } 953 954 int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 955 { 956 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 957 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 958 u32 hfi_val = HFI_DISABLE_FLIP; 959 960 if (inst->fw_caps[HFLIP].value) 961 hfi_val |= HFI_HORIZONTAL_FLIP; 962 963 if (inst->fw_caps[VFLIP].value) 964 hfi_val |= HFI_VERTICAL_FLIP; 965 966 return hfi_ops->session_set_property(inst, hfi_id, 967 HFI_HOST_FLAGS_NONE, 968 iris_get_port_info(inst, cap_id), 969 HFI_PAYLOAD_U32_ENUM, 970 &hfi_val, sizeof(u32)); 971 } 972 973 int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 974 { 975 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 976 struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 977 u32 ir_period = inst->fw_caps[cap_id].value; 978 u32 ir_type = 0; 979 980 if (inst->fw_caps[IR_TYPE].value == 981 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) { 982 if (vb2_is_streaming(q)) 983 return 0; 984 ir_type = HFI_PROP_IR_RANDOM_PERIOD; 985 } else if (inst->fw_caps[IR_TYPE].value == 986 V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) { 987 ir_type = HFI_PROP_IR_CYCLIC_PERIOD; 988 } else { 989 return -EINVAL; 990 } 991 992 return hfi_ops->session_set_property(inst, ir_type, 993 HFI_HOST_FLAGS_NONE, 994 iris_get_port_info(inst, cap_id), 995 HFI_PAYLOAD_U32, 996 &ir_period, sizeof(u32)); 997 } 998 999 int iris_set_properties(struct iris_inst *inst, u32 plane) 1000 { 1001 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 1002 struct platform_inst_fw_cap *cap; 1003 int ret; 1004 u32 i; 1005 1006 ret = hfi_ops->session_set_config_params(inst, plane); 1007 if (ret) 1008 return ret; 1009 1010 for (i = 1; i < INST_FW_CAP_MAX; i++) { 1011 cap = &inst->fw_caps[i]; 1012 if (!iris_valid_cap_id(cap->cap_id)) 1013 continue; 1014 1015 if (cap->cap_id && cap->set) 1016 cap->set(inst, i); 1017 } 1018 1019 return 0; 1020 } 1021