1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <media/v4l2-mem2mem.h> 8 9 #include "iris_ctrls.h" 10 #include "iris_hfi_gen1_defines.h" 11 #include "iris_hfi_gen2_defines.h" 12 #include "iris_instance.h" 13 14 #define CABAC_MAX_BITRATE 160000000 15 #define CAVLC_MAX_BITRATE 220000000 16 17 static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) 18 { 19 return cap_id >= 1 && cap_id < INST_FW_CAP_MAX; 20 } 21 22 static enum platform_inst_fw_cap_type iris_get_cap_id(u32 id) 23 { 24 switch (id) { 25 case V4L2_CID_MPEG_VIDEO_H264_PROFILE: 26 return PROFILE_H264; 27 case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: 28 return PROFILE_HEVC; 29 case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: 30 return PROFILE_VP9; 31 case V4L2_CID_MPEG_VIDEO_H264_LEVEL: 32 return LEVEL_H264; 33 case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: 34 return LEVEL_HEVC; 35 case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: 36 return LEVEL_VP9; 37 case V4L2_CID_MPEG_VIDEO_HEVC_TIER: 38 return TIER; 39 case V4L2_CID_MPEG_VIDEO_HEADER_MODE: 40 return HEADER_MODE; 41 case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: 42 return PREPEND_SPSPPS_TO_IDR; 43 case V4L2_CID_MPEG_VIDEO_BITRATE: 44 return BITRATE; 45 case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: 46 return BITRATE_PEAK; 47 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: 48 return BITRATE_MODE; 49 case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: 50 return FRAME_SKIP_MODE; 51 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: 52 return FRAME_RC_ENABLE; 53 case V4L2_CID_MPEG_VIDEO_GOP_SIZE: 54 return GOP_SIZE; 55 case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: 56 return ENTROPY_MODE; 57 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: 58 return MIN_FRAME_QP_H264; 59 case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: 60 return MIN_FRAME_QP_HEVC; 61 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: 62 return MAX_FRAME_QP_H264; 63 case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: 64 return MAX_FRAME_QP_HEVC; 65 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: 66 return I_FRAME_MIN_QP_H264; 67 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: 68 return I_FRAME_MIN_QP_HEVC; 69 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: 70 return P_FRAME_MIN_QP_H264; 71 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: 72 return P_FRAME_MIN_QP_HEVC; 73 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: 74 return B_FRAME_MIN_QP_H264; 75 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: 76 return B_FRAME_MIN_QP_HEVC; 77 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: 78 return I_FRAME_MAX_QP_H264; 79 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: 80 return I_FRAME_MAX_QP_HEVC; 81 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: 82 return P_FRAME_MAX_QP_H264; 83 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: 84 return P_FRAME_MAX_QP_HEVC; 85 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: 86 return B_FRAME_MAX_QP_H264; 87 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: 88 return B_FRAME_MAX_QP_HEVC; 89 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: 90 return I_FRAME_QP_H264; 91 case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: 92 return I_FRAME_QP_HEVC; 93 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: 94 return P_FRAME_QP_H264; 95 case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: 96 return P_FRAME_QP_HEVC; 97 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: 98 return B_FRAME_QP_H264; 99 case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: 100 return B_FRAME_QP_HEVC; 101 default: 102 return INST_FW_CAP_MAX; 103 } 104 } 105 106 static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_type cap_id) 107 { 108 if (!iris_valid_cap_id(cap_id)) 109 return 0; 110 111 switch (cap_id) { 112 case PROFILE_H264: 113 return V4L2_CID_MPEG_VIDEO_H264_PROFILE; 114 case PROFILE_HEVC: 115 return V4L2_CID_MPEG_VIDEO_HEVC_PROFILE; 116 case PROFILE_VP9: 117 return V4L2_CID_MPEG_VIDEO_VP9_PROFILE; 118 case LEVEL_H264: 119 return V4L2_CID_MPEG_VIDEO_H264_LEVEL; 120 case LEVEL_HEVC: 121 return V4L2_CID_MPEG_VIDEO_HEVC_LEVEL; 122 case LEVEL_VP9: 123 return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; 124 case TIER: 125 return V4L2_CID_MPEG_VIDEO_HEVC_TIER; 126 case HEADER_MODE: 127 return V4L2_CID_MPEG_VIDEO_HEADER_MODE; 128 case PREPEND_SPSPPS_TO_IDR: 129 return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; 130 case BITRATE: 131 return V4L2_CID_MPEG_VIDEO_BITRATE; 132 case BITRATE_PEAK: 133 return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; 134 case BITRATE_MODE: 135 return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; 136 case FRAME_SKIP_MODE: 137 return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; 138 case FRAME_RC_ENABLE: 139 return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; 140 case GOP_SIZE: 141 return V4L2_CID_MPEG_VIDEO_GOP_SIZE; 142 case ENTROPY_MODE: 143 return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; 144 case MIN_FRAME_QP_H264: 145 return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; 146 case MIN_FRAME_QP_HEVC: 147 return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; 148 case MAX_FRAME_QP_H264: 149 return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; 150 case MAX_FRAME_QP_HEVC: 151 return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; 152 case I_FRAME_MIN_QP_H264: 153 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; 154 case I_FRAME_MIN_QP_HEVC: 155 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; 156 case P_FRAME_MIN_QP_H264: 157 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; 158 case P_FRAME_MIN_QP_HEVC: 159 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; 160 case B_FRAME_MIN_QP_H264: 161 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; 162 case B_FRAME_MIN_QP_HEVC: 163 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; 164 case I_FRAME_MAX_QP_H264: 165 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; 166 case I_FRAME_MAX_QP_HEVC: 167 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; 168 case P_FRAME_MAX_QP_H264: 169 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; 170 case P_FRAME_MAX_QP_HEVC: 171 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; 172 case B_FRAME_MAX_QP_H264: 173 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; 174 case B_FRAME_MAX_QP_HEVC: 175 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; 176 case I_FRAME_QP_H264: 177 return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; 178 case I_FRAME_QP_HEVC: 179 return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; 180 case P_FRAME_QP_H264: 181 return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; 182 case P_FRAME_QP_HEVC: 183 return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; 184 case B_FRAME_QP_H264: 185 return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; 186 case B_FRAME_QP_HEVC: 187 return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; 188 default: 189 return 0; 190 } 191 } 192 193 static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) 194 { 195 struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler); 196 enum platform_inst_fw_cap_type cap_id; 197 struct platform_inst_fw_cap *cap; 198 struct vb2_queue *q; 199 200 cap = &inst->fw_caps[0]; 201 cap_id = iris_get_cap_id(ctrl->id); 202 if (!iris_valid_cap_id(cap_id)) 203 return -EINVAL; 204 205 q = v4l2_m2m_get_src_vq(inst->m2m_ctx); 206 if (vb2_is_streaming(q) && 207 (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) 208 return -EINVAL; 209 210 cap[cap_id].flags |= CAP_FLAG_CLIENT_SET; 211 212 inst->fw_caps[cap_id].value = ctrl->val; 213 214 if (vb2_is_streaming(q)) { 215 if (cap[cap_id].set) 216 cap[cap_id].set(inst, cap_id); 217 } 218 219 return 0; 220 } 221 222 static const struct v4l2_ctrl_ops iris_ctrl_ops = { 223 .s_ctrl = iris_op_s_ctrl, 224 }; 225 226 int iris_ctrls_init(struct iris_inst *inst) 227 { 228 struct platform_inst_fw_cap *cap = &inst->fw_caps[0]; 229 u32 num_ctrls = 0, ctrl_idx = 0, idx = 0; 230 u32 v4l2_id; 231 int ret; 232 233 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 234 if (iris_get_v4l2_id(cap[idx].cap_id)) 235 num_ctrls++; 236 } 237 238 /* Adding 1 to num_ctrls to include 239 * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and 240 * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder 241 */ 242 243 ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); 244 if (ret) 245 return ret; 246 247 for (idx = 1; idx < INST_FW_CAP_MAX; idx++) { 248 struct v4l2_ctrl *ctrl; 249 250 v4l2_id = iris_get_v4l2_id(cap[idx].cap_id); 251 if (!v4l2_id) 252 continue; 253 254 if (ctrl_idx >= num_ctrls) { 255 ret = -EINVAL; 256 goto error; 257 } 258 259 if (cap[idx].flags & CAP_FLAG_MENU) { 260 ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler, 261 &iris_ctrl_ops, 262 v4l2_id, 263 cap[idx].max, 264 ~(cap[idx].step_or_mask), 265 cap[idx].value); 266 } else { 267 ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, 268 &iris_ctrl_ops, 269 v4l2_id, 270 cap[idx].min, 271 cap[idx].max, 272 cap[idx].step_or_mask, 273 cap[idx].value); 274 } 275 if (!ctrl) { 276 ret = -EINVAL; 277 goto error; 278 } 279 280 ctrl_idx++; 281 } 282 283 if (inst->domain == DECODER) { 284 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 285 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); 286 } else { 287 v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, 288 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); 289 } 290 291 ret = inst->ctrl_handler.error; 292 if (ret) 293 goto error; 294 295 return 0; 296 error: 297 v4l2_ctrl_handler_free(&inst->ctrl_handler); 298 299 return ret; 300 } 301 302 void iris_session_init_caps(struct iris_core *core) 303 { 304 struct platform_inst_fw_cap *caps; 305 u32 i, num_cap, cap_id; 306 307 caps = core->iris_platform_data->inst_fw_caps_dec; 308 num_cap = core->iris_platform_data->inst_fw_caps_dec_size; 309 310 for (i = 0; i < num_cap; i++) { 311 cap_id = caps[i].cap_id; 312 if (!iris_valid_cap_id(cap_id)) 313 continue; 314 315 core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id; 316 core->inst_fw_caps_dec[cap_id].min = caps[i].min; 317 core->inst_fw_caps_dec[cap_id].max = caps[i].max; 318 core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask; 319 core->inst_fw_caps_dec[cap_id].value = caps[i].value; 320 core->inst_fw_caps_dec[cap_id].flags = caps[i].flags; 321 core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id; 322 core->inst_fw_caps_dec[cap_id].set = caps[i].set; 323 } 324 325 caps = core->iris_platform_data->inst_fw_caps_enc; 326 num_cap = core->iris_platform_data->inst_fw_caps_enc_size; 327 328 for (i = 0; i < num_cap; i++) { 329 cap_id = caps[i].cap_id; 330 if (!iris_valid_cap_id(cap_id)) 331 continue; 332 333 core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id; 334 core->inst_fw_caps_enc[cap_id].min = caps[i].min; 335 core->inst_fw_caps_enc[cap_id].max = caps[i].max; 336 core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask; 337 core->inst_fw_caps_enc[cap_id].value = caps[i].value; 338 core->inst_fw_caps_enc[cap_id].flags = caps[i].flags; 339 core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id; 340 core->inst_fw_caps_enc[cap_id].set = caps[i].set; 341 } 342 } 343 344 static u32 iris_get_port_info(struct iris_inst *inst, 345 enum platform_inst_fw_cap_type cap_id) 346 { 347 if (inst->domain == DECODER) { 348 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 349 return HFI_PORT_BITSTREAM; 350 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 351 return HFI_PORT_RAW; 352 } else { 353 if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) 354 return HFI_PORT_RAW; 355 else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) 356 return HFI_PORT_BITSTREAM; 357 } 358 359 return HFI_PORT_NONE; 360 } 361 362 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 363 { 364 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 365 u32 hfi_value = inst->fw_caps[cap_id].value; 366 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 367 368 return hfi_ops->session_set_property(inst, hfi_id, 369 HFI_HOST_FLAGS_NONE, 370 iris_get_port_info(inst, cap_id), 371 HFI_PAYLOAD_U32_ENUM, 372 &hfi_value, sizeof(u32)); 373 } 374 375 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 376 { 377 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 378 u32 hfi_value = inst->fw_caps[cap_id].value; 379 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 380 381 return hfi_ops->session_set_property(inst, hfi_id, 382 HFI_HOST_FLAGS_NONE, 383 iris_get_port_info(inst, cap_id), 384 HFI_PAYLOAD_U32, 385 &hfi_value, sizeof(u32)); 386 } 387 388 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 389 { 390 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 391 struct v4l2_format *inp_f = inst->fmt_src; 392 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 393 u32 height = inp_f->fmt.pix_mp.height; 394 u32 width = inp_f->fmt.pix_mp.width; 395 u32 work_mode = STAGE_2; 396 397 if (inst->domain == DECODER) { 398 if (iris_res_is_less_than(width, height, 1280, 720)) 399 work_mode = STAGE_1; 400 } 401 402 return hfi_ops->session_set_property(inst, hfi_id, 403 HFI_HOST_FLAGS_NONE, 404 iris_get_port_info(inst, cap_id), 405 HFI_PAYLOAD_U32, 406 &work_mode, sizeof(u32)); 407 } 408 409 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 410 { 411 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 412 u32 work_route = inst->fw_caps[PIPE].value; 413 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 414 415 return hfi_ops->session_set_property(inst, hfi_id, 416 HFI_HOST_FLAGS_NONE, 417 iris_get_port_info(inst, cap_id), 418 HFI_PAYLOAD_U32, 419 &work_route, sizeof(u32)); 420 } 421 422 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 423 { 424 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 425 u32 hfi_id, hfi_value; 426 427 if (inst->codec == V4L2_PIX_FMT_H264) { 428 hfi_id = inst->fw_caps[PROFILE_H264].hfi_id; 429 hfi_value = inst->fw_caps[PROFILE_H264].value; 430 } else { 431 hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id; 432 hfi_value = inst->fw_caps[PROFILE_HEVC].value; 433 } 434 435 return hfi_ops->session_set_property(inst, hfi_id, 436 HFI_HOST_FLAGS_NONE, 437 iris_get_port_info(inst, cap_id), 438 HFI_PAYLOAD_U32_ENUM, 439 &hfi_value, sizeof(u32)); 440 } 441 442 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 443 { 444 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 445 u32 hfi_id, hfi_value; 446 447 if (inst->codec == V4L2_PIX_FMT_H264) { 448 hfi_id = inst->fw_caps[LEVEL_H264].hfi_id; 449 hfi_value = inst->fw_caps[LEVEL_H264].value; 450 } else { 451 hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id; 452 hfi_value = inst->fw_caps[LEVEL_HEVC].value; 453 } 454 455 return hfi_ops->session_set_property(inst, hfi_id, 456 HFI_HOST_FLAGS_NONE, 457 iris_get_port_info(inst, cap_id), 458 HFI_PAYLOAD_U32_ENUM, 459 &hfi_value, sizeof(u32)); 460 } 461 462 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 463 { 464 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 465 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 466 struct hfi_profile_level pl; 467 468 if (inst->codec == V4L2_PIX_FMT_H264) { 469 pl.profile = inst->fw_caps[PROFILE_H264].value; 470 pl.level = inst->fw_caps[LEVEL_H264].value; 471 } else { 472 pl.profile = inst->fw_caps[PROFILE_HEVC].value; 473 pl.level = inst->fw_caps[LEVEL_HEVC].value; 474 } 475 476 return hfi_ops->session_set_property(inst, hfi_id, 477 HFI_HOST_FLAGS_NONE, 478 iris_get_port_info(inst, cap_id), 479 HFI_PAYLOAD_U32_ENUM, 480 &pl, sizeof(u32)); 481 } 482 483 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 484 { 485 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 486 u32 header_mode = inst->fw_caps[cap_id].value; 487 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 488 u32 hfi_val; 489 490 if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) 491 hfi_val = 0; 492 else 493 hfi_val = 1; 494 495 return hfi_ops->session_set_property(inst, hfi_id, 496 HFI_HOST_FLAGS_NONE, 497 iris_get_port_info(inst, cap_id), 498 HFI_PAYLOAD_U32, 499 &hfi_val, sizeof(u32)); 500 } 501 502 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 503 { 504 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 505 u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; 506 u32 header_mode = inst->fw_caps[cap_id].value; 507 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 508 u32 hfi_val; 509 510 if (prepend_sps_pps) 511 hfi_val = HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; 512 else if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME) 513 hfi_val = HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; 514 else 515 hfi_val = HFI_SEQ_HEADER_SEPERATE_FRAME; 516 517 return hfi_ops->session_set_property(inst, hfi_id, 518 HFI_HOST_FLAGS_NONE, 519 iris_get_port_info(inst, cap_id), 520 HFI_PAYLOAD_U32_ENUM, 521 &hfi_val, sizeof(u32)); 522 } 523 524 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 525 { 526 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 527 u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value; 528 u32 bitrate = inst->fw_caps[cap_id].value; 529 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 530 u32 max_bitrate; 531 532 if (inst->codec == V4L2_PIX_FMT_HEVC) 533 max_bitrate = CABAC_MAX_BITRATE; 534 535 if (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 536 max_bitrate = CABAC_MAX_BITRATE; 537 else 538 max_bitrate = CAVLC_MAX_BITRATE; 539 540 bitrate = min(bitrate, max_bitrate); 541 542 return hfi_ops->session_set_property(inst, hfi_id, 543 HFI_HOST_FLAGS_NONE, 544 iris_get_port_info(inst, cap_id), 545 HFI_PAYLOAD_U32, 546 &bitrate, sizeof(u32)); 547 } 548 549 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 550 { 551 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 552 u32 rc_mode = inst->fw_caps[BITRATE_MODE].value; 553 u32 peak_bitrate = inst->fw_caps[cap_id].value; 554 u32 bitrate = inst->fw_caps[BITRATE].value; 555 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 556 557 if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 558 return 0; 559 560 if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { 561 if (peak_bitrate < bitrate) 562 peak_bitrate = bitrate; 563 } else { 564 peak_bitrate = bitrate; 565 } 566 567 inst->fw_caps[cap_id].value = peak_bitrate; 568 569 return hfi_ops->session_set_property(inst, hfi_id, 570 HFI_HOST_FLAGS_NONE, 571 iris_get_port_info(inst, cap_id), 572 HFI_PAYLOAD_U32, 573 &peak_bitrate, sizeof(u32)); 574 } 575 576 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 577 { 578 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 579 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 580 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 581 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 582 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 583 u32 rc_mode = 0; 584 585 if (!frame_rc) 586 rc_mode = HFI_RATE_CONTROL_OFF; 587 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 588 rc_mode = frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR_CFR; 589 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 590 rc_mode = frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR_CFR; 591 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 592 rc_mode = HFI_RATE_CONTROL_CQ; 593 594 inst->hfi_rc_type = rc_mode; 595 596 return hfi_ops->session_set_property(inst, hfi_id, 597 HFI_HOST_FLAGS_NONE, 598 iris_get_port_info(inst, cap_id), 599 HFI_PAYLOAD_U32_ENUM, 600 &rc_mode, sizeof(u32)); 601 } 602 603 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 604 { 605 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 606 u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value; 607 u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value; 608 u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value; 609 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 610 u32 rc_mode = 0; 611 612 if (!frame_rc) 613 rc_mode = HFI_RC_OFF; 614 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) 615 rc_mode = HFI_RC_VBR_CFR; 616 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) 617 rc_mode = frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; 618 else if (bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) 619 rc_mode = HFI_RC_CQ; 620 621 inst->hfi_rc_type = rc_mode; 622 623 return hfi_ops->session_set_property(inst, hfi_id, 624 HFI_HOST_FLAGS_NONE, 625 iris_get_port_info(inst, cap_id), 626 HFI_PAYLOAD_U32_ENUM, 627 &rc_mode, sizeof(u32)); 628 } 629 630 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 631 { 632 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 633 u32 entropy_mode = inst->fw_caps[cap_id].value; 634 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 635 u32 hfi_val; 636 637 if (inst->codec != V4L2_PIX_FMT_H264) 638 return 0; 639 640 hfi_val = (entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) ? 641 HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; 642 643 return hfi_ops->session_set_property(inst, hfi_id, 644 HFI_HOST_FLAGS_NONE, 645 iris_get_port_info(inst, cap_id), 646 HFI_PAYLOAD_U32, 647 &hfi_val, sizeof(u32)); 648 } 649 650 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 651 { 652 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 653 u32 entropy_mode = inst->fw_caps[cap_id].value; 654 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 655 u32 profile; 656 657 if (inst->codec != V4L2_PIX_FMT_H264) 658 return 0; 659 660 profile = inst->fw_caps[PROFILE_H264].value; 661 662 if (profile == V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || 663 profile == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) 664 entropy_mode = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; 665 666 inst->fw_caps[cap_id].value = entropy_mode; 667 668 return hfi_ops->session_set_property(inst, hfi_id, 669 HFI_HOST_FLAGS_NONE, 670 iris_get_port_info(inst, cap_id), 671 HFI_PAYLOAD_U32, 672 &entropy_mode, sizeof(u32)); 673 } 674 675 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 676 { 677 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 678 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 679 u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0; 680 u32 min_qp_enable = 0, client_qp_enable = 0; 681 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 682 u32 hfi_val; 683 684 if (inst->codec == V4L2_PIX_FMT_H264) { 685 if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 686 min_qp_enable = 1; 687 if (min_qp_enable || 688 (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 689 i_qp_enable = 1; 690 if (min_qp_enable || 691 (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 692 p_qp_enable = 1; 693 if (min_qp_enable || 694 (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 695 b_qp_enable = 1; 696 } else { 697 if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 698 min_qp_enable = 1; 699 if (min_qp_enable || 700 (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 701 i_qp_enable = 1; 702 if (min_qp_enable || 703 (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 704 p_qp_enable = 1; 705 if (min_qp_enable || 706 (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 707 b_qp_enable = 1; 708 } 709 710 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 711 if (!client_qp_enable) 712 return 0; 713 714 if (inst->codec == V4L2_PIX_FMT_H264) { 715 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, 716 inst->fw_caps[MIN_FRAME_QP_H264].value); 717 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, 718 inst->fw_caps[MIN_FRAME_QP_H264].value); 719 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, 720 inst->fw_caps[MIN_FRAME_QP_H264].value); 721 } else { 722 i_frame_qp = max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, 723 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 724 p_frame_qp = max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, 725 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 726 b_frame_qp = max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, 727 inst->fw_caps[MIN_FRAME_QP_HEVC].value); 728 } 729 730 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_enable << 24; 731 732 return hfi_ops->session_set_property(inst, hfi_id, 733 HFI_HOST_FLAGS_NONE, 734 iris_get_port_info(inst, cap_id), 735 HFI_PAYLOAD_32_PACKED, 736 &hfi_val, sizeof(u32)); 737 } 738 739 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 740 { 741 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 742 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0; 743 u32 max_qp_enable = 0, client_qp_enable; 744 u32 i_frame_qp, p_frame_qp, b_frame_qp; 745 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 746 u32 hfi_val; 747 748 if (inst->codec == V4L2_PIX_FMT_H264) { 749 if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 750 max_qp_enable = 1; 751 if (max_qp_enable || 752 (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 753 i_qp_enable = 1; 754 if (max_qp_enable || 755 (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 756 p_qp_enable = 1; 757 if (max_qp_enable || 758 (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) 759 b_qp_enable = 1; 760 } else { 761 if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 762 max_qp_enable = 1; 763 if (max_qp_enable || 764 (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 765 i_qp_enable = 1; 766 if (max_qp_enable || 767 (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 768 p_qp_enable = 1; 769 if (max_qp_enable || 770 (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) 771 b_qp_enable = 1; 772 } 773 774 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 775 if (!client_qp_enable) 776 return 0; 777 778 if (inst->codec == V4L2_PIX_FMT_H264) { 779 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, 780 inst->fw_caps[MAX_FRAME_QP_H264].value); 781 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, 782 inst->fw_caps[MAX_FRAME_QP_H264].value); 783 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, 784 inst->fw_caps[MAX_FRAME_QP_H264].value); 785 } else { 786 i_frame_qp = min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, 787 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 788 p_frame_qp = min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, 789 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 790 b_frame_qp = min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, 791 inst->fw_caps[MAX_FRAME_QP_HEVC].value); 792 } 793 794 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 795 client_qp_enable << 24; 796 797 return hfi_ops->session_set_property(inst, hfi_id, 798 HFI_HOST_FLAGS_NONE, 799 iris_get_port_info(inst, cap_id), 800 HFI_PAYLOAD_32_PACKED, 801 &hfi_val, sizeof(u32)); 802 } 803 804 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 805 { 806 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 807 u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable; 808 u32 i_frame_qp, p_frame_qp, b_frame_qp; 809 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 810 struct vb2_queue *q; 811 u32 hfi_val; 812 813 q = v4l2_m2m_get_dst_vq(inst->m2m_ctx); 814 if (vb2_is_streaming(q)) { 815 if (inst->hfi_rc_type != HFI_RC_OFF) 816 return 0; 817 } 818 819 if (inst->hfi_rc_type == HFI_RC_OFF) { 820 i_qp_enable = 1; 821 p_qp_enable = 1; 822 b_qp_enable = 1; 823 } else { 824 if (inst->codec == V4L2_PIX_FMT_H264) { 825 if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 826 i_qp_enable = 1; 827 if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 828 p_qp_enable = 1; 829 if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) 830 b_qp_enable = 1; 831 } else { 832 if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 833 i_qp_enable = 1; 834 if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 835 p_qp_enable = 1; 836 if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) 837 b_qp_enable = 1; 838 } 839 } 840 841 client_qp_enable = i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; 842 if (!client_qp_enable) 843 return 0; 844 845 if (inst->codec == V4L2_PIX_FMT_H264) { 846 i_frame_qp = inst->fw_caps[I_FRAME_QP_H264].value; 847 p_frame_qp = inst->fw_caps[P_FRAME_QP_H264].value; 848 b_frame_qp = inst->fw_caps[B_FRAME_QP_H264].value; 849 } else { 850 i_frame_qp = inst->fw_caps[I_FRAME_QP_HEVC].value; 851 p_frame_qp = inst->fw_caps[P_FRAME_QP_HEVC].value; 852 b_frame_qp = inst->fw_caps[B_FRAME_QP_HEVC].value; 853 } 854 855 hfi_val = i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | 856 client_qp_enable << 24; 857 858 return hfi_ops->session_set_property(inst, hfi_id, 859 HFI_HOST_FLAGS_NONE, 860 iris_get_port_info(inst, cap_id), 861 HFI_PAYLOAD_32_PACKED, 862 &hfi_val, sizeof(u32)); 863 } 864 865 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) 866 { 867 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 868 struct hfi_quantization_range_v2 range; 869 u32 hfi_id = inst->fw_caps[cap_id].hfi_id; 870 871 if (inst->codec == V4L2_PIX_FMT_HEVC) { 872 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value; 873 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_HEVC].value; 874 } else { 875 range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_H264].value; 876 range.max_qp.qp_packed = inst->fw_caps[MAX_FRAME_QP_H264].value; 877 } 878 879 return hfi_ops->session_set_property(inst, hfi_id, 880 HFI_HOST_FLAGS_NONE, 881 iris_get_port_info(inst, cap_id), 882 HFI_PAYLOAD_32_PACKED, 883 &range, sizeof(range)); 884 } 885 886 int iris_set_properties(struct iris_inst *inst, u32 plane) 887 { 888 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops; 889 struct platform_inst_fw_cap *cap; 890 int ret; 891 u32 i; 892 893 ret = hfi_ops->session_set_config_params(inst, plane); 894 if (ret) 895 return ret; 896 897 for (i = 1; i < INST_FW_CAP_MAX; i++) { 898 cap = &inst->fw_caps[i]; 899 if (!iris_valid_cap_id(cap->cap_id)) 900 continue; 901 902 if (cap->cap_id && cap->set) 903 cap->set(inst, i); 904 } 905 906 return 0; 907 } 908