xref: /linux/drivers/media/platform/qcom/iris/iris_buffer.c (revision d22037f3fd33e5956ecbc2ee38b42726fa2cc7a0) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #include <media/v4l2-event.h>
7 #include <media/v4l2-mem2mem.h>
8 
9 #include "iris_buffer.h"
10 #include "iris_instance.h"
11 #include "iris_power.h"
12 #include "iris_vpu_buffer.h"
13 
14 #define PIXELS_4K 4096
15 #define MAX_WIDTH 4096
16 #define MAX_HEIGHT 2304
17 #define Y_STRIDE_ALIGN 128
18 #define UV_STRIDE_ALIGN 128
19 #define Y_SCANLINE_ALIGN 32
20 #define UV_SCANLINE_ALIGN 16
21 #define UV_SCANLINE_ALIGN_QC08C 32
22 #define META_STRIDE_ALIGNED 64
23 #define META_SCANLINE_ALIGNED 16
24 #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16))
25 
26 /*
27  * NV12:
28  * YUV 4:2:0 image with a plane of 8 bit Y samples followed
29  * by an interleaved U/V plane containing 8 bit 2x2 subsampled
30  * colour difference samples.
31  *
32  * <-Y/UV_Stride (aligned to 128)->
33  * <------- Width ------->
34  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  ^           ^
35  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |
36  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  Height      |
37  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |          y_scanlines (aligned to 32)
38  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |
39  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |
40  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  |           |
41  * Y Y Y Y Y Y Y Y Y Y Y Y . . . .  V           |
42  * . . . . . . . . . . . . . . . .              |
43  * . . . . . . . . . . . . . . . .              |
44  * . . . . . . . . . . . . . . . .              |
45  * . . . . . . . . . . . . . . . .              V
46  * U V U V U V U V U V U V . . . .  ^
47  * U V U V U V U V U V U V . . . .  |
48  * U V U V U V U V U V U V . . . .  |
49  * U V U V U V U V U V U V . . . .  uv_scanlines (aligned to 16)
50  * . . . . . . . . . . . . . . . .  |
51  * . . . . . . . . . . . . . . . .  V
52  * . . . . . . . . . . . . . . . .  --> Buffer size aligned to 4K
53  *
54  * y_stride : Width aligned to 128
55  * uv_stride : Width aligned to 128
56  * y_scanlines: Height aligned to 32
57  * uv_scanlines: Height/2 aligned to 16
58  * Total size = align((y_stride * y_scanlines
59  *          + uv_stride * uv_scanlines , 4096)
60  *
61  * Note: All the alignments are hardware requirements.
62  */
63 static u32 iris_yuv_buffer_size_nv12(struct iris_inst *inst)
64 {
65 	u32 y_plane, uv_plane, y_stride, uv_stride, y_scanlines, uv_scanlines;
66 	struct v4l2_format *f;
67 
68 	if (inst->domain == DECODER)
69 		f = inst->fmt_dst;
70 	else
71 		f = inst->fmt_src;
72 
73 	y_stride = ALIGN(f->fmt.pix_mp.width, Y_STRIDE_ALIGN);
74 	uv_stride = ALIGN(f->fmt.pix_mp.width, UV_STRIDE_ALIGN);
75 	y_scanlines = ALIGN(f->fmt.pix_mp.height, Y_SCANLINE_ALIGN);
76 	uv_scanlines = ALIGN((f->fmt.pix_mp.height + 1) >> 1, UV_SCANLINE_ALIGN);
77 	y_plane = y_stride * y_scanlines;
78 	uv_plane = uv_stride * uv_scanlines;
79 
80 	return ALIGN(y_plane + uv_plane, PIXELS_4K);
81 }
82 
83 /*
84  * QC08C:
85  * Compressed Macro-tile format for NV12.
86  * Contains 4 planes in the following order -
87  * (A) Y_Meta_Plane
88  * (B) Y_UBWC_Plane
89  * (C) UV_Meta_Plane
90  * (D) UV_UBWC_Plane
91  *
92  * Y_Meta_Plane consists of meta information to decode compressed
93  * tile data in Y_UBWC_Plane.
94  * Y_UBWC_Plane consists of Y data in compressed macro-tile format.
95  * UBWC decoder block will use the Y_Meta_Plane data together with
96  * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples.
97  *
98  * UV_Meta_Plane consists of meta information to decode compressed
99  * tile data in UV_UBWC_Plane.
100  * UV_UBWC_Plane consists of UV data in compressed macro-tile format.
101  * UBWC decoder block will use UV_Meta_Plane data together with
102  * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2
103  * subsampled color difference samples.
104  *
105  * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
106  * and randomly accessible. There is no dependency between tiles.
107  *
108  * <----- y_meta_stride ----> (aligned to 64)
109  * <-------- Width ------>
110  * M M M M M M M M M M M M . .      ^           ^
111  * M M M M M M M M M M M M . .      |           |
112  * M M M M M M M M M M M M . .      Height      |
113  * M M M M M M M M M M M M . .      |         y_meta_scanlines  (aligned to 16)
114  * M M M M M M M M M M M M . .      |           |
115  * M M M M M M M M M M M M . .      |           |
116  * M M M M M M M M M M M M . .      |           |
117  * M M M M M M M M M M M M . .      V           |
118  * . . . . . . . . . . . . . .                  |
119  * . . . . . . . . . . . . . .                  |
120  * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k
121  * . . . . . . . . . . . . . .                  V
122  * <--Compressed tile y_stride---> (aligned to 128)
123  * <------- Width ------->
124  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  ^           ^
125  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |
126  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  Height      |
127  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |        Macro_tile y_scanlines (aligned to 32)
128  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |
129  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |
130  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  |           |
131  * Y* Y* Y* Y* Y* Y* Y* Y* . . . .  V           |
132  * . . . . . . . . . . . . . . . .              |
133  * . . . . . . . . . . . . . . . .              |
134  * . . . . . . . . . . . . . . . .  -------> Buffer size aligned to 4k
135  * . . . . . . . . . . . . . . . .              V
136  * <----- uv_meta_stride ---->  (aligned to 64)
137  * M M M M M M M M M M M M . .      ^
138  * M M M M M M M M M M M M . .      |
139  * M M M M M M M M M M M M . .      |
140  * M M M M M M M M M M M M . .      uv_meta_scanlines (aligned to 16)
141  * . . . . . . . . . . . . . .      |
142  * . . . . . . . . . . . . . .      V
143  * . . . . . . . . . . . . . .      -------> Buffer size aligned to 4k
144  * <--Compressed tile uv_stride---> (aligned to 128)
145  * U* V* U* V* U* V* U* V* . . . .  ^
146  * U* V* U* V* U* V* U* V* . . . .  |
147  * U* V* U* V* U* V* U* V* . . . .  |
148  * U* V* U* V* U* V* U* V* . . . .  uv_scanlines (aligned to 32)
149  * . . . . . . . . . . . . . . . .  |
150  * . . . . . . . . . . . . . . . .  V
151  * . . . . . . . . . . . . . . . .  -------> Buffer size aligned to 4k
152  *
153  * y_stride: width aligned to 128
154  * uv_stride: width aligned to 128
155  * y_scanlines: height aligned to 32
156  * uv_scanlines: height aligned to 32
157  * y_plane: buffer size aligned to 4096
158  * uv_plane: buffer size aligned to 4096
159  * y_meta_stride: width aligned to 64
160  * y_meta_scanlines: height aligned to 16
161  * y_meta_plane: buffer size aligned to 4096
162  * uv_meta_stride: width aligned to 64
163  * uv_meta_scanlines: height aligned to 16
164  * uv_meta_plane: buffer size aligned to 4096
165  *
166  * Total size = align( y_plane + uv_plane +
167  *           y_meta_plane + uv_meta_plane, 4096)
168  *
169  * Note: All the alignments are hardware requirements.
170  */
171 static u32 iris_yuv_buffer_size_qc08c(struct iris_inst *inst)
172 {
173 	u32 y_plane, uv_plane, y_stride, uv_stride;
174 	struct v4l2_format *f = inst->fmt_dst;
175 	u32 uv_meta_stride, uv_meta_plane;
176 	u32 y_meta_stride, y_meta_plane;
177 
178 	y_meta_stride = ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.width, META_STRIDE_ALIGNED >> 1),
179 			      META_STRIDE_ALIGNED);
180 	y_meta_plane = y_meta_stride * ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.height,
181 							  META_SCANLINE_ALIGNED >> 1),
182 					     META_SCANLINE_ALIGNED);
183 	y_meta_plane = ALIGN(y_meta_plane, PIXELS_4K);
184 
185 	y_stride = ALIGN(f->fmt.pix_mp.width, Y_STRIDE_ALIGN);
186 	y_plane = ALIGN(y_stride * ALIGN(f->fmt.pix_mp.height, Y_SCANLINE_ALIGN), PIXELS_4K);
187 
188 	uv_meta_stride = ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.width / 2, META_STRIDE_ALIGNED >> 2),
189 			       META_STRIDE_ALIGNED);
190 	uv_meta_plane = uv_meta_stride * ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.height / 2,
191 							    META_SCANLINE_ALIGNED >> 1),
192 					       META_SCANLINE_ALIGNED);
193 	uv_meta_plane = ALIGN(uv_meta_plane, PIXELS_4K);
194 
195 	uv_stride = ALIGN(f->fmt.pix_mp.width, UV_STRIDE_ALIGN);
196 	uv_plane = ALIGN(uv_stride * ALIGN(f->fmt.pix_mp.height / 2, UV_SCANLINE_ALIGN_QC08C),
197 			 PIXELS_4K);
198 
199 	return ALIGN(y_meta_plane + y_plane + uv_meta_plane + uv_plane, PIXELS_4K);
200 }
201 
202 static u32 iris_dec_bitstream_buffer_size(struct iris_inst *inst)
203 {
204 	struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
205 	u32 base_res_mbs = NUM_MBS_4K;
206 	u32 frame_size, num_mbs;
207 	u32 div_factor = 2;
208 
209 	num_mbs = iris_get_mbpf(inst);
210 	if (num_mbs > NUM_MBS_4K) {
211 		div_factor = 4;
212 		base_res_mbs = caps->max_mbpf;
213 	} else {
214 		if (inst->codec == V4L2_PIX_FMT_VP9)
215 			div_factor = 1;
216 	}
217 
218 	/*
219 	 * frame_size = YUVsize / div_factor
220 	 * where YUVsize = resolution_in_MBs * MBs_in_pixel * 3 / 2
221 	 */
222 	frame_size = base_res_mbs * (16 * 16) * 3 / 2 / div_factor;
223 
224 	return ALIGN(frame_size, PIXELS_4K);
225 }
226 
227 static u32 iris_enc_bitstream_buffer_size(struct iris_inst *inst)
228 {
229 	u32 aligned_width, aligned_height, bitstream_size, yuv_size;
230 	int bitrate_mode, frame_rc;
231 	struct v4l2_format *f;
232 
233 	f = inst->fmt_dst;
234 
235 	bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
236 	frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
237 
238 	aligned_width = ALIGN(f->fmt.pix_mp.width, 32);
239 	aligned_height = ALIGN(f->fmt.pix_mp.height, 32);
240 	bitstream_size = aligned_width * aligned_height * 3;
241 	yuv_size = (aligned_width * aligned_height * 3) >> 1;
242 	if (aligned_width * aligned_height > (4096 * 2176))
243 		/* bitstream_size = 0.25 * yuv_size; */
244 		bitstream_size = (bitstream_size >> 3);
245 	else if (aligned_width * aligned_height > (1280 * 720))
246 		/* bitstream_size = 0.5 * yuv_size; */
247 		bitstream_size = (bitstream_size >> 2);
248 
249 	if ((!frame_rc || bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) &&
250 	    bitstream_size < yuv_size)
251 		bitstream_size = (bitstream_size << 1);
252 
253 	return ALIGN(bitstream_size, 4096);
254 }
255 
256 int iris_get_buffer_size(struct iris_inst *inst,
257 			 enum iris_buffer_type buffer_type)
258 {
259 	if (inst->domain == DECODER) {
260 		switch (buffer_type) {
261 		case BUF_INPUT:
262 			return iris_dec_bitstream_buffer_size(inst);
263 		case BUF_OUTPUT:
264 			return iris_yuv_buffer_size_nv12(inst);
265 		case BUF_DPB:
266 			return iris_yuv_buffer_size_qc08c(inst);
267 		default:
268 			return 0;
269 		}
270 	} else {
271 		switch (buffer_type) {
272 		case BUF_INPUT:
273 			return iris_yuv_buffer_size_nv12(inst);
274 		case BUF_OUTPUT:
275 			return iris_enc_bitstream_buffer_size(inst);
276 		default:
277 			return 0;
278 		}
279 	}
280 }
281 
282 static void iris_fill_internal_buf_info(struct iris_inst *inst,
283 					enum iris_buffer_type buffer_type)
284 {
285 	struct iris_buffers *buffers = &inst->buffers[buffer_type];
286 
287 	buffers->size = iris_vpu_buf_size(inst, buffer_type);
288 	buffers->min_count = iris_vpu_buf_count(inst, buffer_type);
289 }
290 
291 void iris_get_internal_buffers(struct iris_inst *inst, u32 plane)
292 {
293 	const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
294 	const u32 *internal_buf_type;
295 	u32 internal_buffer_count, i;
296 
297 	if (V4L2_TYPE_IS_OUTPUT(plane)) {
298 		internal_buf_type = platform_data->dec_ip_int_buf_tbl;
299 		internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
300 		for (i = 0; i < internal_buffer_count; i++)
301 			iris_fill_internal_buf_info(inst, internal_buf_type[i]);
302 	} else {
303 		internal_buf_type = platform_data->dec_op_int_buf_tbl;
304 		internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
305 		for (i = 0; i < internal_buffer_count; i++)
306 			iris_fill_internal_buf_info(inst, internal_buf_type[i]);
307 	}
308 }
309 
310 static int iris_create_internal_buffer(struct iris_inst *inst,
311 				       enum iris_buffer_type buffer_type, u32 index)
312 {
313 	struct iris_buffers *buffers = &inst->buffers[buffer_type];
314 	struct iris_core *core = inst->core;
315 	struct iris_buffer *buffer;
316 
317 	if (!buffers->size)
318 		return 0;
319 
320 	buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
321 	if (!buffer)
322 		return -ENOMEM;
323 
324 	INIT_LIST_HEAD(&buffer->list);
325 	buffer->type = buffer_type;
326 	buffer->index = index;
327 	buffer->buffer_size = buffers->size;
328 	buffer->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING;
329 	list_add_tail(&buffer->list, &buffers->list);
330 
331 	buffer->kvaddr = dma_alloc_attrs(core->dev, buffer->buffer_size,
332 					 &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs);
333 	if (!buffer->kvaddr)
334 		return -ENOMEM;
335 
336 	return 0;
337 }
338 
339 int iris_create_internal_buffers(struct iris_inst *inst, u32 plane)
340 {
341 	const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
342 	u32 internal_buffer_count, i, j;
343 	struct iris_buffers *buffers;
344 	const u32 *internal_buf_type;
345 	int ret;
346 
347 	if (V4L2_TYPE_IS_OUTPUT(plane)) {
348 		internal_buf_type = platform_data->dec_ip_int_buf_tbl;
349 		internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
350 	} else {
351 		internal_buf_type = platform_data->dec_op_int_buf_tbl;
352 		internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
353 	}
354 
355 	for (i = 0; i < internal_buffer_count; i++) {
356 		buffers = &inst->buffers[internal_buf_type[i]];
357 		for (j = 0; j < buffers->min_count; j++) {
358 			ret = iris_create_internal_buffer(inst, internal_buf_type[i], j);
359 			if (ret)
360 				return ret;
361 		}
362 	}
363 
364 	return 0;
365 }
366 
367 int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf)
368 {
369 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
370 	int ret;
371 
372 	ret = hfi_ops->session_queue_buf(inst, buf);
373 	if (ret)
374 		return ret;
375 
376 	buf->attr &= ~BUF_ATTR_DEFERRED;
377 	buf->attr |= BUF_ATTR_QUEUED;
378 
379 	return 0;
380 }
381 
382 int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type)
383 {
384 	struct iris_buffer *buffer, *next;
385 	struct iris_buffers *buffers;
386 	int ret = 0;
387 
388 	buffers = &inst->buffers[buffer_type];
389 	list_for_each_entry_safe(buffer, next, &buffers->list, list) {
390 		if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
391 			continue;
392 		if (buffer->attr & BUF_ATTR_QUEUED)
393 			continue;
394 
395 		if (buffer->attr & BUF_ATTR_DEFERRED) {
396 			ret = iris_queue_buffer(inst, buffer);
397 			if (ret)
398 				return ret;
399 		}
400 	}
401 
402 	return ret;
403 }
404 
405 int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane)
406 {
407 	const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
408 	struct iris_buffer *buffer, *next;
409 	struct iris_buffers *buffers;
410 	const u32 *internal_buf_type;
411 	u32 internal_buffer_count, i;
412 	int ret;
413 
414 	if (V4L2_TYPE_IS_OUTPUT(plane)) {
415 		internal_buf_type = platform_data->dec_ip_int_buf_tbl;
416 		internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
417 	} else {
418 		internal_buf_type = platform_data->dec_op_int_buf_tbl;
419 		internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
420 	}
421 
422 	for (i = 0; i < internal_buffer_count; i++) {
423 		buffers = &inst->buffers[internal_buf_type[i]];
424 		list_for_each_entry_safe(buffer, next, &buffers->list, list) {
425 			if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
426 				continue;
427 			if (buffer->attr & BUF_ATTR_QUEUED)
428 				continue;
429 			if (buffer->type == BUF_DPB && inst->state != IRIS_INST_STREAMING) {
430 				buffer->attr |= BUF_ATTR_DEFERRED;
431 				continue;
432 			}
433 			ret = iris_queue_buffer(inst, buffer);
434 			if (ret)
435 				return ret;
436 		}
437 	}
438 
439 	return 0;
440 }
441 
442 int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer)
443 {
444 	struct iris_core *core = inst->core;
445 
446 	list_del(&buffer->list);
447 	dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr,
448 		       buffer->device_addr, buffer->dma_attrs);
449 	kfree(buffer);
450 
451 	return 0;
452 }
453 
454 static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane, bool force)
455 {
456 	const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
457 	struct iris_buffer *buf, *next;
458 	struct iris_buffers *buffers;
459 	const u32 *internal_buf_type;
460 	u32 i, len;
461 	int ret;
462 
463 	if (V4L2_TYPE_IS_OUTPUT(plane)) {
464 		internal_buf_type = platform_data->dec_ip_int_buf_tbl;
465 		len = platform_data->dec_ip_int_buf_tbl_size;
466 	} else {
467 		internal_buf_type = platform_data->dec_op_int_buf_tbl;
468 		len = platform_data->dec_op_int_buf_tbl_size;
469 	}
470 
471 	for (i = 0; i < len; i++) {
472 		buffers = &inst->buffers[internal_buf_type[i]];
473 		list_for_each_entry_safe(buf, next, &buffers->list, list) {
474 			/*
475 			 * during stream on, skip destroying internal(DPB) buffer
476 			 * if firmware did not return it.
477 			 * during close, destroy all buffers irrespectively.
478 			 */
479 			if (!force && buf->attr & BUF_ATTR_QUEUED)
480 				continue;
481 
482 			ret = iris_destroy_internal_buffer(inst, buf);
483 			if (ret)
484 				return ret;
485 		}
486 	}
487 
488 	if (force) {
489 		buffers = &inst->buffers[BUF_PERSIST];
490 
491 		list_for_each_entry_safe(buf, next, &buffers->list, list) {
492 			ret = iris_destroy_internal_buffer(inst, buf);
493 			if (ret)
494 				return ret;
495 		}
496 	}
497 
498 	return 0;
499 }
500 
501 int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane)
502 {
503 	return iris_destroy_internal_buffers(inst, plane, true);
504 }
505 
506 int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane)
507 {
508 	return iris_destroy_internal_buffers(inst, plane, false);
509 }
510 
511 static int iris_release_internal_buffers(struct iris_inst *inst,
512 					 enum iris_buffer_type buffer_type)
513 {
514 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
515 	struct iris_buffers *buffers = &inst->buffers[buffer_type];
516 	struct iris_buffer *buffer, *next;
517 	int ret;
518 
519 	list_for_each_entry_safe(buffer, next, &buffers->list, list) {
520 		if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
521 			continue;
522 		if (!(buffer->attr & BUF_ATTR_QUEUED))
523 			continue;
524 		ret = hfi_ops->session_release_buf(inst, buffer);
525 		if (ret)
526 			return ret;
527 		buffer->attr |= BUF_ATTR_PENDING_RELEASE;
528 	}
529 
530 	return 0;
531 }
532 
533 static int iris_release_input_internal_buffers(struct iris_inst *inst)
534 {
535 	const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
536 	const u32 *internal_buf_type;
537 	u32 internal_buffer_count, i;
538 	int ret;
539 
540 	internal_buf_type = platform_data->dec_ip_int_buf_tbl;
541 	internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
542 
543 	for (i = 0; i < internal_buffer_count; i++) {
544 		ret = iris_release_internal_buffers(inst, internal_buf_type[i]);
545 		if (ret)
546 			return ret;
547 	}
548 
549 	return 0;
550 }
551 
552 int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst)
553 {
554 	struct iris_buffers *buffers = &inst->buffers[BUF_PERSIST];
555 	struct iris_buffer *buffer, *next;
556 	int ret;
557 	u32 i;
558 
559 	if (!list_empty(&buffers->list))
560 		return 0;
561 
562 	iris_fill_internal_buf_info(inst, BUF_PERSIST);
563 
564 	for (i = 0; i < buffers->min_count; i++) {
565 		ret = iris_create_internal_buffer(inst, BUF_PERSIST, i);
566 		if (ret)
567 			return ret;
568 	}
569 
570 	list_for_each_entry_safe(buffer, next, &buffers->list, list) {
571 		if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
572 			continue;
573 		if (buffer->attr & BUF_ATTR_QUEUED)
574 			continue;
575 		ret = iris_queue_buffer(inst, buffer);
576 		if (ret)
577 			return ret;
578 	}
579 
580 	return 0;
581 }
582 
583 int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst)
584 {
585 	int ret;
586 
587 	iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
588 
589 	ret = iris_release_input_internal_buffers(inst);
590 	if (ret)
591 		return ret;
592 
593 	ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
594 	if (ret)
595 		return ret;
596 
597 	return iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
598 }
599 
600 int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buf_type)
601 {
602 	struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
603 	struct v4l2_m2m_buffer *buffer, *n;
604 	struct iris_buffer *buf;
605 	int ret;
606 
607 	iris_scale_power(inst);
608 
609 	if (buf_type == BUF_INPUT) {
610 		v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buffer, n) {
611 			buf = to_iris_buffer(&buffer->vb);
612 			if (!(buf->attr & BUF_ATTR_DEFERRED))
613 				continue;
614 			ret = iris_queue_buffer(inst, buf);
615 			if (ret)
616 				return ret;
617 		}
618 	} else {
619 		v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buffer, n) {
620 			buf = to_iris_buffer(&buffer->vb);
621 			if (!(buf->attr & BUF_ATTR_DEFERRED))
622 				continue;
623 			ret = iris_queue_buffer(inst, buf);
624 			if (ret)
625 				return ret;
626 		}
627 	}
628 
629 	return 0;
630 }
631 
632 void iris_vb2_queue_error(struct iris_inst *inst)
633 {
634 	struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
635 	struct vb2_queue *q;
636 
637 	q = v4l2_m2m_get_src_vq(m2m_ctx);
638 	vb2_queue_error(q);
639 	q = v4l2_m2m_get_dst_vq(m2m_ctx);
640 	vb2_queue_error(q);
641 }
642 
643 static struct vb2_v4l2_buffer *
644 iris_helper_find_buf(struct iris_inst *inst, u32 type, u32 idx)
645 {
646 	struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
647 
648 	if (V4L2_TYPE_IS_OUTPUT(type))
649 		return v4l2_m2m_src_buf_remove_by_idx(m2m_ctx, idx);
650 	else
651 		return v4l2_m2m_dst_buf_remove_by_idx(m2m_ctx, idx);
652 }
653 
654 static void iris_get_ts_metadata(struct iris_inst *inst, u64 timestamp_ns,
655 				 struct vb2_v4l2_buffer *vbuf)
656 {
657 	u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
658 	u32 i;
659 
660 	for (i = 0; i < ARRAY_SIZE(inst->tss); ++i) {
661 		if (inst->tss[i].ts_ns != timestamp_ns)
662 			continue;
663 
664 		vbuf->flags &= ~mask;
665 		vbuf->flags |= inst->tss[i].flags;
666 		vbuf->timecode = inst->tss[i].tc;
667 		return;
668 	}
669 
670 	vbuf->flags &= ~mask;
671 	vbuf->flags |= inst->tss[inst->metadata_idx].flags;
672 	vbuf->timecode = inst->tss[inst->metadata_idx].tc;
673 }
674 
675 int iris_vb2_buffer_done(struct iris_inst *inst, struct iris_buffer *buf)
676 {
677 	struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
678 	struct vb2_v4l2_buffer *vbuf;
679 	struct vb2_buffer *vb2;
680 	u32 type, state;
681 
682 	switch (buf->type) {
683 	case BUF_INPUT:
684 		type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
685 		break;
686 	case BUF_OUTPUT:
687 		type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
688 		break;
689 	default:
690 		return 0; /* Internal DPB Buffers */
691 	}
692 
693 	vbuf = iris_helper_find_buf(inst, type, buf->index);
694 	if (!vbuf)
695 		return -EINVAL;
696 
697 	vb2 = &vbuf->vb2_buf;
698 
699 	vbuf->flags |= buf->flags;
700 
701 	if (buf->flags & V4L2_BUF_FLAG_ERROR) {
702 		state = VB2_BUF_STATE_ERROR;
703 		vb2_set_plane_payload(vb2, 0, 0);
704 		vb2->timestamp = 0;
705 		v4l2_m2m_buf_done(vbuf, state);
706 		return 0;
707 	}
708 
709 	if (V4L2_TYPE_IS_CAPTURE(type)) {
710 		vb2_set_plane_payload(vb2, 0, buf->data_size);
711 		vbuf->sequence = inst->sequence_cap++;
712 		iris_get_ts_metadata(inst, buf->timestamp, vbuf);
713 	} else {
714 		vbuf->sequence = inst->sequence_out++;
715 	}
716 
717 	if (vbuf->flags & V4L2_BUF_FLAG_LAST) {
718 		if (!v4l2_m2m_has_stopped(m2m_ctx)) {
719 			const struct v4l2_event ev = { .type = V4L2_EVENT_EOS };
720 
721 			v4l2_event_queue_fh(&inst->fh, &ev);
722 			v4l2_m2m_mark_stopped(m2m_ctx);
723 		}
724 		inst->last_buffer_dequeued = true;
725 	}
726 
727 	state = VB2_BUF_STATE_DONE;
728 	vb2->timestamp = buf->timestamp;
729 	v4l2_m2m_buf_done(vbuf, state);
730 
731 	return 0;
732 }
733