1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss.c 4 * 5 * Qualcomm MSM Camera Subsystem - Core 6 * 7 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/interconnect.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/media.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pm_domain.h> 21 #include <linux/slab.h> 22 #include <linux/videodev2.h> 23 24 #include <media/media-device.h> 25 #include <media/v4l2-async.h> 26 #include <media/v4l2-device.h> 27 #include <media/v4l2-mc.h> 28 #include <media/v4l2-fwnode.h> 29 30 #include "camss.h" 31 32 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105 33 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 34 35 static const struct camss_subdev_resources csiphy_res_8x16[] = { 36 /* CSIPHY0 */ 37 { 38 .regulators = {}, 39 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 40 .clock_rate = { { 0 }, 41 { 0 }, 42 { 0 }, 43 { 100000000, 200000000 } }, 44 .reg = { "csiphy0", "csiphy0_clk_mux" }, 45 .interrupt = { "csiphy0" }, 46 .ops = &csiphy_ops_2ph_1_0 47 }, 48 49 /* CSIPHY1 */ 50 { 51 .regulators = {}, 52 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 53 .clock_rate = { { 0 }, 54 { 0 }, 55 { 0 }, 56 { 100000000, 200000000 } }, 57 .reg = { "csiphy1", "csiphy1_clk_mux" }, 58 .interrupt = { "csiphy1" }, 59 .ops = &csiphy_ops_2ph_1_0 60 } 61 }; 62 63 static const struct camss_subdev_resources csid_res_8x16[] = { 64 /* CSID0 */ 65 { 66 .regulators = { "vdda" }, 67 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 68 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 69 .clock_rate = { { 0 }, 70 { 0 }, 71 { 0 }, 72 { 0 }, 73 { 100000000, 200000000 }, 74 { 0 }, 75 { 0 }, 76 { 0 } }, 77 .reg = { "csid0" }, 78 .interrupt = { "csid0" }, 79 .ops = &csid_ops_4_1, 80 }, 81 82 /* CSID1 */ 83 { 84 .regulators = { "vdda" }, 85 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 86 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 87 .clock_rate = { { 0 }, 88 { 0 }, 89 { 0 }, 90 { 0 }, 91 { 100000000, 200000000 }, 92 { 0 }, 93 { 0 }, 94 { 0 } }, 95 .reg = { "csid1" }, 96 .interrupt = { "csid1" }, 97 .ops = &csid_ops_4_1, 98 }, 99 }; 100 101 static const struct camss_subdev_resources ispif_res_8x16 = { 102 /* ISPIF */ 103 .clock = { "top_ahb", "ahb", "ispif_ahb", 104 "csi0", "csi0_pix", "csi0_rdi", 105 "csi1", "csi1_pix", "csi1_rdi" }, 106 .clock_for_reset = { "vfe0", "csi_vfe0" }, 107 .reg = { "ispif", "csi_clk_mux" }, 108 .interrupt = { "ispif" } 109 110 }; 111 112 static const struct camss_subdev_resources vfe_res_8x16[] = { 113 /* VFE0 */ 114 { 115 .regulators = {}, 116 .clock = { "top_ahb", "vfe0", "csi_vfe0", 117 "vfe_ahb", "vfe_axi", "ahb" }, 118 .clock_rate = { { 0 }, 119 { 50000000, 80000000, 100000000, 160000000, 120 177780000, 200000000, 266670000, 320000000, 121 400000000, 465000000 }, 122 { 0 }, 123 { 0 }, 124 { 0 }, 125 { 0 }, 126 { 0 }, 127 { 0 }, 128 { 0 } }, 129 .reg = { "vfe0" }, 130 .interrupt = { "vfe0" }, 131 .line_num = 3, 132 .ops = &vfe_ops_4_1 133 } 134 }; 135 136 static const struct camss_subdev_resources csiphy_res_8x96[] = { 137 /* CSIPHY0 */ 138 { 139 .regulators = {}, 140 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 141 .clock_rate = { { 0 }, 142 { 0 }, 143 { 0 }, 144 { 100000000, 200000000, 266666667 } }, 145 .reg = { "csiphy0", "csiphy0_clk_mux" }, 146 .interrupt = { "csiphy0" }, 147 .ops = &csiphy_ops_3ph_1_0 148 }, 149 150 /* CSIPHY1 */ 151 { 152 .regulators = {}, 153 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 154 .clock_rate = { { 0 }, 155 { 0 }, 156 { 0 }, 157 { 100000000, 200000000, 266666667 } }, 158 .reg = { "csiphy1", "csiphy1_clk_mux" }, 159 .interrupt = { "csiphy1" }, 160 .ops = &csiphy_ops_3ph_1_0 161 }, 162 163 /* CSIPHY2 */ 164 { 165 .regulators = {}, 166 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" }, 167 .clock_rate = { { 0 }, 168 { 0 }, 169 { 0 }, 170 { 100000000, 200000000, 266666667 } }, 171 .reg = { "csiphy2", "csiphy2_clk_mux" }, 172 .interrupt = { "csiphy2" }, 173 .ops = &csiphy_ops_3ph_1_0 174 } 175 }; 176 177 static const struct camss_subdev_resources csid_res_8x96[] = { 178 /* CSID0 */ 179 { 180 .regulators = { "vdda" }, 181 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 182 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 183 .clock_rate = { { 0 }, 184 { 0 }, 185 { 0 }, 186 { 0 }, 187 { 100000000, 200000000, 266666667 }, 188 { 0 }, 189 { 0 }, 190 { 0 } }, 191 .reg = { "csid0" }, 192 .interrupt = { "csid0" }, 193 .ops = &csid_ops_4_7, 194 }, 195 196 /* CSID1 */ 197 { 198 .regulators = { "vdda" }, 199 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 200 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 201 .clock_rate = { { 0 }, 202 { 0 }, 203 { 0 }, 204 { 0 }, 205 { 100000000, 200000000, 266666667 }, 206 { 0 }, 207 { 0 }, 208 { 0 } }, 209 .reg = { "csid1" }, 210 .interrupt = { "csid1" }, 211 .ops = &csid_ops_4_7, 212 }, 213 214 /* CSID2 */ 215 { 216 .regulators = { "vdda" }, 217 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 218 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, 219 .clock_rate = { { 0 }, 220 { 0 }, 221 { 0 }, 222 { 0 }, 223 { 100000000, 200000000, 266666667 }, 224 { 0 }, 225 { 0 }, 226 { 0 } }, 227 .reg = { "csid2" }, 228 .interrupt = { "csid2" }, 229 .ops = &csid_ops_4_7, 230 }, 231 232 /* CSID3 */ 233 { 234 .regulators = { "vdda" }, 235 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 236 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" }, 237 .clock_rate = { { 0 }, 238 { 0 }, 239 { 0 }, 240 { 0 }, 241 { 100000000, 200000000, 266666667 }, 242 { 0 }, 243 { 0 }, 244 { 0 } }, 245 .reg = { "csid3" }, 246 .interrupt = { "csid3" }, 247 .ops = &csid_ops_4_7, 248 } 249 }; 250 251 static const struct camss_subdev_resources ispif_res_8x96 = { 252 /* ISPIF */ 253 .clock = { "top_ahb", "ahb", "ispif_ahb", 254 "csi0", "csi0_pix", "csi0_rdi", 255 "csi1", "csi1_pix", "csi1_rdi", 256 "csi2", "csi2_pix", "csi2_rdi", 257 "csi3", "csi3_pix", "csi3_rdi" }, 258 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" }, 259 .reg = { "ispif", "csi_clk_mux" }, 260 .interrupt = { "ispif" } 261 }; 262 263 static const struct camss_subdev_resources vfe_res_8x96[] = { 264 /* VFE0 */ 265 { 266 .regulators = {}, 267 .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb", 268 "vfe0_ahb", "vfe_axi", "vfe0_stream"}, 269 .clock_rate = { { 0 }, 270 { 0 }, 271 { 75000000, 100000000, 300000000, 272 320000000, 480000000, 600000000 }, 273 { 0 }, 274 { 0 }, 275 { 0 }, 276 { 0 }, 277 { 0 } }, 278 .reg = { "vfe0" }, 279 .interrupt = { "vfe0" }, 280 .line_num = 3, 281 .has_pd = true, 282 .ops = &vfe_ops_4_7 283 }, 284 285 /* VFE1 */ 286 { 287 .regulators = {}, 288 .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb", 289 "vfe1_ahb", "vfe_axi", "vfe1_stream"}, 290 .clock_rate = { { 0 }, 291 { 0 }, 292 { 75000000, 100000000, 300000000, 293 320000000, 480000000, 600000000 }, 294 { 0 }, 295 { 0 }, 296 { 0 }, 297 { 0 }, 298 { 0 } }, 299 .reg = { "vfe1" }, 300 .interrupt = { "vfe1" }, 301 .line_num = 3, 302 .has_pd = true, 303 .ops = &vfe_ops_4_7 304 } 305 }; 306 307 static const struct camss_subdev_resources csiphy_res_660[] = { 308 /* CSIPHY0 */ 309 { 310 .regulators = {}, 311 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer", 312 "csi0_phy", "csiphy_ahb2crif" }, 313 .clock_rate = { { 0 }, 314 { 0 }, 315 { 0 }, 316 { 100000000, 200000000, 269333333 }, 317 { 0 } }, 318 .reg = { "csiphy0", "csiphy0_clk_mux" }, 319 .interrupt = { "csiphy0" }, 320 .ops = &csiphy_ops_3ph_1_0 321 }, 322 323 /* CSIPHY1 */ 324 { 325 .regulators = {}, 326 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer", 327 "csi1_phy", "csiphy_ahb2crif" }, 328 .clock_rate = { { 0 }, 329 { 0 }, 330 { 0 }, 331 { 100000000, 200000000, 269333333 }, 332 { 0 } }, 333 .reg = { "csiphy1", "csiphy1_clk_mux" }, 334 .interrupt = { "csiphy1" }, 335 .ops = &csiphy_ops_3ph_1_0 336 }, 337 338 /* CSIPHY2 */ 339 { 340 .regulators = {}, 341 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer", 342 "csi2_phy", "csiphy_ahb2crif" }, 343 .clock_rate = { { 0 }, 344 { 0 }, 345 { 0 }, 346 { 100000000, 200000000, 269333333 }, 347 { 0 } }, 348 .reg = { "csiphy2", "csiphy2_clk_mux" }, 349 .interrupt = { "csiphy2" }, 350 .ops = &csiphy_ops_3ph_1_0 351 } 352 }; 353 354 static const struct camss_subdev_resources csid_res_660[] = { 355 /* CSID0 */ 356 { 357 .regulators = { "vdda", "vdd_sec" }, 358 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 359 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", 360 "cphy_csid0" }, 361 .clock_rate = { { 0 }, 362 { 0 }, 363 { 0 }, 364 { 0 }, 365 { 100000000, 200000000, 310000000, 366 404000000, 465000000 }, 367 { 0 }, 368 { 0 }, 369 { 0 }, 370 { 0 } }, 371 .reg = { "csid0" }, 372 .interrupt = { "csid0" }, 373 .ops = &csid_ops_4_7, 374 }, 375 376 /* CSID1 */ 377 { 378 .regulators = { "vdda", "vdd_sec" }, 379 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 380 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", 381 "cphy_csid1" }, 382 .clock_rate = { { 0 }, 383 { 0 }, 384 { 0 }, 385 { 0 }, 386 { 100000000, 200000000, 310000000, 387 404000000, 465000000 }, 388 { 0 }, 389 { 0 }, 390 { 0 }, 391 { 0 } }, 392 .reg = { "csid1" }, 393 .interrupt = { "csid1" }, 394 .ops = &csid_ops_4_7, 395 }, 396 397 /* CSID2 */ 398 { 399 .regulators = { "vdda", "vdd_sec" }, 400 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 401 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", 402 "cphy_csid2" }, 403 .clock_rate = { { 0 }, 404 { 0 }, 405 { 0 }, 406 { 0 }, 407 { 100000000, 200000000, 310000000, 408 404000000, 465000000 }, 409 { 0 }, 410 { 0 }, 411 { 0 }, 412 { 0 } }, 413 .reg = { "csid2" }, 414 .interrupt = { "csid2" }, 415 .ops = &csid_ops_4_7, 416 }, 417 418 /* CSID3 */ 419 { 420 .regulators = { "vdda", "vdd_sec" }, 421 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 422 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", 423 "cphy_csid3" }, 424 .clock_rate = { { 0 }, 425 { 0 }, 426 { 0 }, 427 { 0 }, 428 { 100000000, 200000000, 310000000, 429 404000000, 465000000 }, 430 { 0 }, 431 { 0 }, 432 { 0 }, 433 { 0 } }, 434 .reg = { "csid3" }, 435 .interrupt = { "csid3" }, 436 .ops = &csid_ops_4_7, 437 } 438 }; 439 440 static const struct camss_subdev_resources ispif_res_660 = { 441 /* ISPIF */ 442 .clock = { "top_ahb", "ahb", "ispif_ahb", 443 "csi0", "csi0_pix", "csi0_rdi", 444 "csi1", "csi1_pix", "csi1_rdi", 445 "csi2", "csi2_pix", "csi2_rdi", 446 "csi3", "csi3_pix", "csi3_rdi" }, 447 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" }, 448 .reg = { "ispif", "csi_clk_mux" }, 449 .interrupt = { "ispif" } 450 }; 451 452 static const struct camss_subdev_resources vfe_res_660[] = { 453 /* VFE0 */ 454 { 455 .regulators = {}, 456 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0", 457 "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi", 458 "vfe0_stream"}, 459 .clock_rate = { { 0 }, 460 { 0 }, 461 { 0 }, 462 { 120000000, 200000000, 256000000, 463 300000000, 404000000, 480000000, 464 540000000, 576000000 }, 465 { 0 }, 466 { 0 }, 467 { 0 }, 468 { 0 }, 469 { 0 } }, 470 .reg = { "vfe0" }, 471 .interrupt = { "vfe0" }, 472 .line_num = 3, 473 .has_pd = true, 474 .ops = &vfe_ops_4_8 475 }, 476 477 /* VFE1 */ 478 { 479 .regulators = {}, 480 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1", 481 "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi", 482 "vfe1_stream"}, 483 .clock_rate = { { 0 }, 484 { 0 }, 485 { 0 }, 486 { 120000000, 200000000, 256000000, 487 300000000, 404000000, 480000000, 488 540000000, 576000000 }, 489 { 0 }, 490 { 0 }, 491 { 0 }, 492 { 0 }, 493 { 0 } }, 494 .reg = { "vfe1" }, 495 .interrupt = { "vfe1" }, 496 .line_num = 3, 497 .has_pd = true, 498 .ops = &vfe_ops_4_8 499 } 500 }; 501 502 static const struct camss_subdev_resources csiphy_res_845[] = { 503 /* CSIPHY0 */ 504 { 505 .regulators = {}, 506 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 507 "cpas_ahb", "cphy_rx_src", "csiphy0", 508 "csiphy0_timer_src", "csiphy0_timer" }, 509 .clock_rate = { { 0 }, 510 { 0 }, 511 { 0 }, 512 { 0 }, 513 { 0 }, 514 { 0 }, 515 { 0 }, 516 { 19200000, 240000000, 269333333 } }, 517 .reg = { "csiphy0" }, 518 .interrupt = { "csiphy0" }, 519 .ops = &csiphy_ops_3ph_1_0 520 }, 521 522 /* CSIPHY1 */ 523 { 524 .regulators = {}, 525 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 526 "cpas_ahb", "cphy_rx_src", "csiphy1", 527 "csiphy1_timer_src", "csiphy1_timer" }, 528 .clock_rate = { { 0 }, 529 { 0 }, 530 { 0 }, 531 { 0 }, 532 { 0 }, 533 { 0 }, 534 { 0 }, 535 { 19200000, 240000000, 269333333 } }, 536 .reg = { "csiphy1" }, 537 .interrupt = { "csiphy1" }, 538 .ops = &csiphy_ops_3ph_1_0 539 }, 540 541 /* CSIPHY2 */ 542 { 543 .regulators = {}, 544 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 545 "cpas_ahb", "cphy_rx_src", "csiphy2", 546 "csiphy2_timer_src", "csiphy2_timer" }, 547 .clock_rate = { { 0 }, 548 { 0 }, 549 { 0 }, 550 { 0 }, 551 { 0 }, 552 { 0 }, 553 { 0 }, 554 { 19200000, 240000000, 269333333 } }, 555 .reg = { "csiphy2" }, 556 .interrupt = { "csiphy2" }, 557 .ops = &csiphy_ops_3ph_1_0 558 }, 559 560 /* CSIPHY3 */ 561 { 562 .regulators = {}, 563 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 564 "cpas_ahb", "cphy_rx_src", "csiphy3", 565 "csiphy3_timer_src", "csiphy3_timer" }, 566 .clock_rate = { { 0 }, 567 { 0 }, 568 { 0 }, 569 { 0 }, 570 { 0 }, 571 { 0 }, 572 { 0 }, 573 { 19200000, 240000000, 269333333 } }, 574 .reg = { "csiphy3" }, 575 .interrupt = { "csiphy3" }, 576 .ops = &csiphy_ops_3ph_1_0 577 } 578 }; 579 580 static const struct camss_subdev_resources csid_res_845[] = { 581 /* CSID0 */ 582 { 583 .regulators = { "vdda-phy", "vdda-pll" }, 584 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 585 "soc_ahb", "vfe0", "vfe0_src", 586 "vfe0_cphy_rx", "csi0", 587 "csi0_src" }, 588 .clock_rate = { { 0 }, 589 { 384000000 }, 590 { 80000000 }, 591 { 0 }, 592 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 593 { 320000000 }, 594 { 0 }, 595 { 19200000, 75000000, 384000000, 538666667 }, 596 { 384000000 } }, 597 .reg = { "csid0" }, 598 .interrupt = { "csid0" }, 599 .ops = &csid_ops_gen2 600 }, 601 602 /* CSID1 */ 603 { 604 .regulators = { "vdda-phy", "vdda-pll" }, 605 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 606 "soc_ahb", "vfe1", "vfe1_src", 607 "vfe1_cphy_rx", "csi1", 608 "csi1_src" }, 609 .clock_rate = { { 0 }, 610 { 384000000 }, 611 { 80000000 }, 612 { 0 }, 613 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 614 { 320000000 }, 615 { 0 }, 616 { 19200000, 75000000, 384000000, 538666667 }, 617 { 384000000 } }, 618 .reg = { "csid1" }, 619 .interrupt = { "csid1" }, 620 .ops = &csid_ops_gen2 621 }, 622 623 /* CSID2 */ 624 { 625 .regulators = { "vdda-phy", "vdda-pll" }, 626 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 627 "soc_ahb", "vfe_lite", "vfe_lite_src", 628 "vfe_lite_cphy_rx", "csi2", 629 "csi2_src" }, 630 .clock_rate = { { 0 }, 631 { 384000000 }, 632 { 80000000 }, 633 { 0 }, 634 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 635 { 320000000 }, 636 { 0 }, 637 { 19200000, 75000000, 384000000, 538666667 }, 638 { 384000000 } }, 639 .reg = { "csid2" }, 640 .interrupt = { "csid2" }, 641 .is_lite = true, 642 .ops = &csid_ops_gen2 643 } 644 }; 645 646 static const struct camss_subdev_resources vfe_res_845[] = { 647 /* VFE0 */ 648 { 649 .regulators = {}, 650 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", 651 "soc_ahb", "vfe0", "vfe0_axi", 652 "vfe0_src", "csi0", 653 "csi0_src"}, 654 .clock_rate = { { 0 }, 655 { 0 }, 656 { 80000000 }, 657 { 0 }, 658 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 659 { 0 }, 660 { 320000000 }, 661 { 19200000, 75000000, 384000000, 538666667 }, 662 { 384000000 } }, 663 .reg = { "vfe0" }, 664 .interrupt = { "vfe0" }, 665 .line_num = 4, 666 .has_pd = true, 667 .ops = &vfe_ops_170 668 }, 669 670 /* VFE1 */ 671 { 672 .regulators = {}, 673 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", 674 "soc_ahb", "vfe1", "vfe1_axi", 675 "vfe1_src", "csi1", 676 "csi1_src"}, 677 .clock_rate = { { 0 }, 678 { 0 }, 679 { 80000000 }, 680 { 0 }, 681 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 682 { 0 }, 683 { 320000000 }, 684 { 19200000, 75000000, 384000000, 538666667 }, 685 { 384000000 } }, 686 .reg = { "vfe1" }, 687 .interrupt = { "vfe1" }, 688 .line_num = 4, 689 .has_pd = true, 690 .ops = &vfe_ops_170 691 }, 692 693 /* VFE-lite */ 694 { 695 .regulators = {}, 696 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", 697 "soc_ahb", "vfe_lite", 698 "vfe_lite_src", "csi2", 699 "csi2_src"}, 700 .clock_rate = { { 0 }, 701 { 0 }, 702 { 80000000 }, 703 { 0 }, 704 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 705 { 320000000 }, 706 { 19200000, 75000000, 384000000, 538666667 }, 707 { 384000000 } }, 708 .reg = { "vfe_lite" }, 709 .interrupt = { "vfe_lite" }, 710 .is_lite = true, 711 .line_num = 4, 712 .ops = &vfe_ops_170 713 } 714 }; 715 716 static const struct camss_subdev_resources csiphy_res_8250[] = { 717 /* CSIPHY0 */ 718 { 719 .regulators = {}, 720 .clock = { "csiphy0", "csiphy0_timer" }, 721 .clock_rate = { { 400000000 }, 722 { 300000000 } }, 723 .reg = { "csiphy0" }, 724 .interrupt = { "csiphy0" }, 725 .ops = &csiphy_ops_3ph_1_0 726 }, 727 /* CSIPHY1 */ 728 { 729 .regulators = {}, 730 .clock = { "csiphy1", "csiphy1_timer" }, 731 .clock_rate = { { 400000000 }, 732 { 300000000 } }, 733 .reg = { "csiphy1" }, 734 .interrupt = { "csiphy1" }, 735 .ops = &csiphy_ops_3ph_1_0 736 }, 737 /* CSIPHY2 */ 738 { 739 .regulators = {}, 740 .clock = { "csiphy2", "csiphy2_timer" }, 741 .clock_rate = { { 400000000 }, 742 { 300000000 } }, 743 .reg = { "csiphy2" }, 744 .interrupt = { "csiphy2" }, 745 .ops = &csiphy_ops_3ph_1_0 746 }, 747 /* CSIPHY3 */ 748 { 749 .regulators = {}, 750 .clock = { "csiphy3", "csiphy3_timer" }, 751 .clock_rate = { { 400000000 }, 752 { 300000000 } }, 753 .reg = { "csiphy3" }, 754 .interrupt = { "csiphy3" }, 755 .ops = &csiphy_ops_3ph_1_0 756 }, 757 /* CSIPHY4 */ 758 { 759 .regulators = {}, 760 .clock = { "csiphy4", "csiphy4_timer" }, 761 .clock_rate = { { 400000000 }, 762 { 300000000 } }, 763 .reg = { "csiphy4" }, 764 .interrupt = { "csiphy4" }, 765 .ops = &csiphy_ops_3ph_1_0 766 }, 767 /* CSIPHY5 */ 768 { 769 .regulators = {}, 770 .clock = { "csiphy5", "csiphy5_timer" }, 771 .clock_rate = { { 400000000 }, 772 { 300000000 } }, 773 .reg = { "csiphy5" }, 774 .interrupt = { "csiphy5" }, 775 .ops = &csiphy_ops_3ph_1_0 776 } 777 }; 778 779 static const struct camss_subdev_resources csid_res_8250[] = { 780 /* CSID0 */ 781 { 782 .regulators = { "vdda-phy", "vdda-pll" }, 783 .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, 784 .clock_rate = { { 400000000 }, 785 { 400000000 }, 786 { 350000000, 475000000, 576000000, 720000000 }, 787 { 100000000, 200000000, 300000000, 400000000 }, 788 { 0 } }, 789 .reg = { "csid0" }, 790 .interrupt = { "csid0" }, 791 .ops = &csid_ops_gen2 792 }, 793 /* CSID1 */ 794 { 795 .regulators = { "vdda-phy", "vdda-pll" }, 796 .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, 797 .clock_rate = { { 400000000 }, 798 { 400000000 }, 799 { 350000000, 475000000, 576000000, 720000000 }, 800 { 100000000, 200000000, 300000000, 400000000 }, 801 { 0 } }, 802 .reg = { "csid1" }, 803 .interrupt = { "csid1" }, 804 .ops = &csid_ops_gen2 805 }, 806 /* CSID2 */ 807 { 808 .regulators = { "vdda-phy", "vdda-pll" }, 809 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, 810 .clock_rate = { { 400000000 }, 811 { 400000000 }, 812 { 400000000, 480000000 }, 813 { 0 } }, 814 .reg = { "csid2" }, 815 .interrupt = { "csid2" }, 816 .is_lite = true, 817 .ops = &csid_ops_gen2 818 }, 819 /* CSID3 */ 820 { 821 .regulators = { "vdda-phy", "vdda-pll" }, 822 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, 823 .clock_rate = { { 400000000 }, 824 { 400000000 }, 825 { 400000000, 480000000 }, 826 { 0 } }, 827 .reg = { "csid3" }, 828 .interrupt = { "csid3" }, 829 .is_lite = true, 830 .ops = &csid_ops_gen2 831 } 832 }; 833 834 static const struct camss_subdev_resources vfe_res_8250[] = { 835 /* VFE0 */ 836 { 837 .regulators = {}, 838 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 839 "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0", 840 "vfe0_axi", "cam_hf_axi" }, 841 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 842 { 19200000, 80000000 }, 843 { 19200000 }, 844 { 0 }, 845 { 0 }, 846 { 100000000, 200000000, 300000000, 400000000 }, 847 { 350000000, 475000000, 576000000, 720000000 }, 848 { 0 }, 849 { 0 } }, 850 .reg = { "vfe0" }, 851 .interrupt = { "vfe0" }, 852 .pd_name = "ife0", 853 .line_num = 3, 854 .has_pd = true, 855 .ops = &vfe_ops_480 856 }, 857 /* VFE1 */ 858 { 859 .regulators = {}, 860 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 861 "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1", 862 "vfe1_axi", "cam_hf_axi" }, 863 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 864 { 19200000, 80000000 }, 865 { 19200000 }, 866 { 0 }, 867 { 0 }, 868 { 100000000, 200000000, 300000000, 400000000 }, 869 { 350000000, 475000000, 576000000, 720000000 }, 870 { 0 }, 871 { 0 } }, 872 .reg = { "vfe1" }, 873 .interrupt = { "vfe1" }, 874 .pd_name = "ife1", 875 .line_num = 3, 876 .has_pd = true, 877 .ops = &vfe_ops_480 878 }, 879 /* VFE2 (lite) */ 880 { 881 .regulators = {}, 882 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 883 "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", 884 "vfe_lite", "cam_hf_axi" }, 885 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 886 { 19200000, 80000000 }, 887 { 19200000 }, 888 { 0 }, 889 { 0 }, 890 { 0 }, 891 { 400000000, 480000000 }, 892 { 0 } }, 893 .reg = { "vfe_lite0" }, 894 .interrupt = { "vfe_lite0" }, 895 .is_lite = true, 896 .line_num = 4, 897 .ops = &vfe_ops_480 898 }, 899 /* VFE3 (lite) */ 900 { 901 .regulators = {}, 902 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 903 "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", 904 "vfe_lite", "cam_hf_axi" }, 905 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 906 { 19200000, 80000000 }, 907 { 19200000 }, 908 { 0 }, 909 { 0 }, 910 { 0 }, 911 { 400000000, 480000000 }, 912 { 0 } }, 913 .reg = { "vfe_lite1" }, 914 .interrupt = { "vfe_lite1" }, 915 .is_lite = true, 916 .line_num = 4, 917 .ops = &vfe_ops_480 918 }, 919 }; 920 921 static const struct resources_icc icc_res_sm8250[] = { 922 { 923 .name = "cam_ahb", 924 .icc_bw_tbl.avg = 38400, 925 .icc_bw_tbl.peak = 76800, 926 }, 927 { 928 .name = "cam_hf_0_mnoc", 929 .icc_bw_tbl.avg = 2097152, 930 .icc_bw_tbl.peak = 2097152, 931 }, 932 { 933 .name = "cam_sf_0_mnoc", 934 .icc_bw_tbl.avg = 0, 935 .icc_bw_tbl.peak = 2097152, 936 }, 937 { 938 .name = "cam_sf_icp_mnoc", 939 .icc_bw_tbl.avg = 2097152, 940 .icc_bw_tbl.peak = 2097152, 941 }, 942 }; 943 944 static const struct camss_subdev_resources csiphy_res_sc8280xp[] = { 945 /* CSIPHY0 */ 946 { 947 .regulators = {}, 948 .clock = { "csiphy0", "csiphy0_timer" }, 949 .clock_rate = { { 400000000 }, 950 { 300000000 } }, 951 .reg = { "csiphy0" }, 952 .interrupt = { "csiphy0" }, 953 .ops = &csiphy_ops_3ph_1_0 954 }, 955 /* CSIPHY1 */ 956 { 957 .regulators = {}, 958 .clock = { "csiphy1", "csiphy1_timer" }, 959 .clock_rate = { { 400000000 }, 960 { 300000000 } }, 961 .reg = { "csiphy1" }, 962 .interrupt = { "csiphy1" }, 963 .ops = &csiphy_ops_3ph_1_0 964 }, 965 /* CSIPHY2 */ 966 { 967 .regulators = {}, 968 .clock = { "csiphy2", "csiphy2_timer" }, 969 .clock_rate = { { 400000000 }, 970 { 300000000 } }, 971 .reg = { "csiphy2" }, 972 .interrupt = { "csiphy2" }, 973 .ops = &csiphy_ops_3ph_1_0 974 }, 975 /* CSIPHY3 */ 976 { 977 .regulators = {}, 978 .clock = { "csiphy3", "csiphy3_timer" }, 979 .clock_rate = { { 400000000 }, 980 { 300000000 } }, 981 .reg = { "csiphy3" }, 982 .interrupt = { "csiphy3" }, 983 .ops = &csiphy_ops_3ph_1_0 984 }, 985 }; 986 987 static const struct camss_subdev_resources csid_res_sc8280xp[] = { 988 /* CSID0 */ 989 { 990 .regulators = { "vdda-phy", "vdda-pll" }, 991 .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" }, 992 .clock_rate = { { 400000000, 480000000, 600000000 }, 993 { 0 }, 994 { 0 }, 995 { 0 } }, 996 .reg = { "csid0" }, 997 .interrupt = { "csid0" }, 998 .ops = &csid_ops_gen2 999 }, 1000 /* CSID1 */ 1001 { 1002 .regulators = { "vdda-phy", "vdda-pll" }, 1003 .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" }, 1004 .clock_rate = { { 400000000, 480000000, 600000000 }, 1005 { 0 }, 1006 { 0 }, 1007 { 0 } }, 1008 .reg = { "csid1" }, 1009 .interrupt = { "csid1" }, 1010 .ops = &csid_ops_gen2 1011 }, 1012 /* CSID2 */ 1013 { 1014 .regulators = { "vdda-phy", "vdda-pll" }, 1015 .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi" }, 1016 .clock_rate = { { 400000000, 480000000, 600000000 }, 1017 { 0 }, 1018 { 0 }, 1019 { 0 } }, 1020 .reg = { "csid2" }, 1021 .interrupt = { "csid2" }, 1022 .ops = &csid_ops_gen2 1023 }, 1024 /* CSID3 */ 1025 { 1026 .regulators = { "vdda-phy", "vdda-pll" }, 1027 .clock = { "vfe3_csid", "vfe3_cphy_rx", "vfe3", "vfe3_axi" }, 1028 .clock_rate = { { 400000000, 480000000, 600000000 }, 1029 { 0 }, 1030 { 0 }, 1031 { 0 } }, 1032 .reg = { "csid3" }, 1033 .interrupt = { "csid3" }, 1034 .ops = &csid_ops_gen2 1035 }, 1036 /* CSID_LITE0 */ 1037 { 1038 .regulators = { "vdda-phy", "vdda-pll" }, 1039 .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, 1040 .clock_rate = { { 400000000, 480000000, 600000000 }, 1041 { 0 }, 1042 { 0 }, }, 1043 .reg = { "csid0_lite" }, 1044 .interrupt = { "csid0_lite" }, 1045 .is_lite = true, 1046 .ops = &csid_ops_gen2 1047 }, 1048 /* CSID_LITE1 */ 1049 { 1050 .regulators = { "vdda-phy", "vdda-pll" }, 1051 .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, 1052 .clock_rate = { { 400000000, 480000000, 600000000 }, 1053 { 0 }, 1054 { 0 }, }, 1055 .reg = { "csid1_lite" }, 1056 .interrupt = { "csid1_lite" }, 1057 .is_lite = true, 1058 .ops = &csid_ops_gen2 1059 }, 1060 /* CSID_LITE2 */ 1061 { 1062 .regulators = { "vdda-phy", "vdda-pll" }, 1063 .clock = { "vfe_lite2_csid", "vfe_lite2_cphy_rx", "vfe_lite2" }, 1064 .clock_rate = { { 400000000, 480000000, 600000000 }, 1065 { 0 }, 1066 { 0 }, }, 1067 .reg = { "csid2_lite" }, 1068 .interrupt = { "csid2_lite" }, 1069 .is_lite = true, 1070 .ops = &csid_ops_gen2 1071 }, 1072 /* CSID_LITE3 */ 1073 { 1074 .regulators = { "vdda-phy", "vdda-pll" }, 1075 .clock = { "vfe_lite3_csid", "vfe_lite3_cphy_rx", "vfe_lite3" }, 1076 .clock_rate = { { 400000000, 480000000, 600000000 }, 1077 { 0 }, 1078 { 0 }, }, 1079 .reg = { "csid3_lite" }, 1080 .interrupt = { "csid3_lite" }, 1081 .is_lite = true, 1082 .ops = &csid_ops_gen2 1083 } 1084 }; 1085 1086 static const struct camss_subdev_resources vfe_res_sc8280xp[] = { 1087 /* VFE0 */ 1088 { 1089 .regulators = {}, 1090 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe0", "vfe0_axi" }, 1091 .clock_rate = { { 0 }, 1092 { 0 }, 1093 { 19200000, 80000000}, 1094 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1095 { 400000000, 558000000, 637000000, 760000000 }, 1096 { 0 }, }, 1097 .reg = { "vfe0" }, 1098 .interrupt = { "vfe0" }, 1099 .pd_name = "ife0", 1100 .line_num = 4, 1101 .ops = &vfe_ops_170 1102 }, 1103 /* VFE1 */ 1104 { 1105 .regulators = {}, 1106 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe1", "vfe1_axi" }, 1107 .clock_rate = { { 0 }, 1108 { 0 }, 1109 { 19200000, 80000000}, 1110 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1111 { 400000000, 558000000, 637000000, 760000000 }, 1112 { 0 }, }, 1113 .reg = { "vfe1" }, 1114 .interrupt = { "vfe1" }, 1115 .pd_name = "ife1", 1116 .line_num = 4, 1117 .ops = &vfe_ops_170 1118 }, 1119 /* VFE2 */ 1120 { 1121 .regulators = {}, 1122 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe2", "vfe2_axi" }, 1123 .clock_rate = { { 0 }, 1124 { 0 }, 1125 { 19200000, 80000000}, 1126 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1127 { 400000000, 558000000, 637000000, 760000000 }, 1128 { 0 }, }, 1129 .reg = { "vfe2" }, 1130 .interrupt = { "vfe2" }, 1131 .pd_name = "ife2", 1132 .line_num = 4, 1133 .ops = &vfe_ops_170 1134 }, 1135 /* VFE3 */ 1136 { 1137 .regulators = {}, 1138 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe3", "vfe3_axi" }, 1139 .clock_rate = { { 0 }, 1140 { 0 }, 1141 { 19200000, 80000000}, 1142 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1143 { 400000000, 558000000, 637000000, 760000000 }, 1144 { 0 }, }, 1145 .reg = { "vfe3" }, 1146 .interrupt = { "vfe3" }, 1147 .pd_name = "ife3", 1148 .line_num = 4, 1149 .ops = &vfe_ops_170 1150 }, 1151 /* VFE_LITE_0 */ 1152 { 1153 .regulators = {}, 1154 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite0" }, 1155 .clock_rate = { { 0 }, 1156 { 0 }, 1157 { 19200000, 80000000}, 1158 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1159 { 320000000, 400000000, 480000000, 600000000 }, }, 1160 .reg = { "vfe_lite0" }, 1161 .interrupt = { "vfe_lite0" }, 1162 .is_lite = true, 1163 .line_num = 4, 1164 .ops = &vfe_ops_170 1165 }, 1166 /* VFE_LITE_1 */ 1167 { 1168 .regulators = {}, 1169 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite1" }, 1170 .clock_rate = { { 0 }, 1171 { 0 }, 1172 { 19200000, 80000000}, 1173 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1174 { 320000000, 400000000, 480000000, 600000000 }, }, 1175 .reg = { "vfe_lite1" }, 1176 .interrupt = { "vfe_lite1" }, 1177 .is_lite = true, 1178 .line_num = 4, 1179 .ops = &vfe_ops_170 1180 }, 1181 /* VFE_LITE_2 */ 1182 { 1183 .regulators = {}, 1184 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite2" }, 1185 .clock_rate = { { 0 }, 1186 { 0 }, 1187 { 19200000, 80000000}, 1188 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1189 { 320000000, 400000000, 480000000, 600000000, }, }, 1190 .reg = { "vfe_lite2" }, 1191 .interrupt = { "vfe_lite2" }, 1192 .is_lite = true, 1193 .line_num = 4, 1194 .ops = &vfe_ops_170 1195 }, 1196 /* VFE_LITE_3 */ 1197 { 1198 .regulators = {}, 1199 .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_lite3" }, 1200 .clock_rate = { { 0 }, 1201 { 0 }, 1202 { 19200000, 80000000}, 1203 { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, 1204 { 320000000, 400000000, 480000000, 600000000 }, }, 1205 .reg = { "vfe_lite3" }, 1206 .interrupt = { "vfe_lite3" }, 1207 .is_lite = true, 1208 .line_num = 4, 1209 .ops = &vfe_ops_170 1210 }, 1211 }; 1212 1213 static const struct resources_icc icc_res_sc8280xp[] = { 1214 { 1215 .name = "cam_ahb", 1216 .icc_bw_tbl.avg = 150000, 1217 .icc_bw_tbl.peak = 300000, 1218 }, 1219 { 1220 .name = "cam_hf_mnoc", 1221 .icc_bw_tbl.avg = 2097152, 1222 .icc_bw_tbl.peak = 2097152, 1223 }, 1224 { 1225 .name = "cam_sf_mnoc", 1226 .icc_bw_tbl.avg = 2097152, 1227 .icc_bw_tbl.peak = 2097152, 1228 }, 1229 { 1230 .name = "cam_sf_icp_mnoc", 1231 .icc_bw_tbl.avg = 2097152, 1232 .icc_bw_tbl.peak = 2097152, 1233 }, 1234 }; 1235 1236 /* 1237 * camss_add_clock_margin - Add margin to clock frequency rate 1238 * @rate: Clock frequency rate 1239 * 1240 * When making calculations with physical clock frequency values 1241 * some safety margin must be added. Add it. 1242 */ 1243 inline void camss_add_clock_margin(u64 *rate) 1244 { 1245 *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR; 1246 *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR); 1247 } 1248 1249 /* 1250 * camss_enable_clocks - Enable multiple clocks 1251 * @nclocks: Number of clocks in clock array 1252 * @clock: Clock array 1253 * @dev: Device 1254 * 1255 * Return 0 on success or a negative error code otherwise 1256 */ 1257 int camss_enable_clocks(int nclocks, struct camss_clock *clock, 1258 struct device *dev) 1259 { 1260 int ret; 1261 int i; 1262 1263 for (i = 0; i < nclocks; i++) { 1264 ret = clk_prepare_enable(clock[i].clk); 1265 if (ret) { 1266 dev_err(dev, "clock enable failed: %d\n", ret); 1267 goto error; 1268 } 1269 } 1270 1271 return 0; 1272 1273 error: 1274 for (i--; i >= 0; i--) 1275 clk_disable_unprepare(clock[i].clk); 1276 1277 return ret; 1278 } 1279 1280 /* 1281 * camss_disable_clocks - Disable multiple clocks 1282 * @nclocks: Number of clocks in clock array 1283 * @clock: Clock array 1284 */ 1285 void camss_disable_clocks(int nclocks, struct camss_clock *clock) 1286 { 1287 int i; 1288 1289 for (i = nclocks - 1; i >= 0; i--) 1290 clk_disable_unprepare(clock[i].clk); 1291 } 1292 1293 /* 1294 * camss_find_sensor - Find a linked media entity which represents a sensor 1295 * @entity: Media entity to start searching from 1296 * 1297 * Return a pointer to sensor media entity or NULL if not found 1298 */ 1299 struct media_entity *camss_find_sensor(struct media_entity *entity) 1300 { 1301 struct media_pad *pad; 1302 1303 while (1) { 1304 pad = &entity->pads[0]; 1305 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 1306 return NULL; 1307 1308 pad = media_pad_remote_pad_first(pad); 1309 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 1310 return NULL; 1311 1312 entity = pad->entity; 1313 1314 if (entity->function == MEDIA_ENT_F_CAM_SENSOR) 1315 return entity; 1316 } 1317 } 1318 1319 /** 1320 * camss_get_link_freq - Get link frequency from sensor 1321 * @entity: Media entity in the current pipeline 1322 * @bpp: Number of bits per pixel for the current format 1323 * @lanes: Number of lanes in the link to the sensor 1324 * 1325 * Return link frequency on success or a negative error code otherwise 1326 */ 1327 s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, 1328 unsigned int lanes) 1329 { 1330 struct media_entity *sensor; 1331 struct v4l2_subdev *subdev; 1332 1333 sensor = camss_find_sensor(entity); 1334 if (!sensor) 1335 return -ENODEV; 1336 1337 subdev = media_entity_to_v4l2_subdev(sensor); 1338 1339 return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes); 1340 } 1341 1342 /* 1343 * camss_get_pixel_clock - Get pixel clock rate from sensor 1344 * @entity: Media entity in the current pipeline 1345 * @pixel_clock: Received pixel clock value 1346 * 1347 * Return 0 on success or a negative error code otherwise 1348 */ 1349 int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock) 1350 { 1351 struct media_entity *sensor; 1352 struct v4l2_subdev *subdev; 1353 struct v4l2_ctrl *ctrl; 1354 1355 sensor = camss_find_sensor(entity); 1356 if (!sensor) 1357 return -ENODEV; 1358 1359 subdev = media_entity_to_v4l2_subdev(sensor); 1360 1361 ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); 1362 1363 if (!ctrl) 1364 return -EINVAL; 1365 1366 *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl); 1367 1368 return 0; 1369 } 1370 1371 int camss_pm_domain_on(struct camss *camss, int id) 1372 { 1373 int ret = 0; 1374 1375 if (id < camss->res->vfe_num) { 1376 struct vfe_device *vfe = &camss->vfe[id]; 1377 1378 ret = vfe->ops->pm_domain_on(vfe); 1379 } 1380 1381 return ret; 1382 } 1383 1384 void camss_pm_domain_off(struct camss *camss, int id) 1385 { 1386 if (id < camss->res->vfe_num) { 1387 struct vfe_device *vfe = &camss->vfe[id]; 1388 1389 vfe->ops->pm_domain_off(vfe); 1390 } 1391 } 1392 1393 /* 1394 * camss_of_parse_endpoint_node - Parse port endpoint node 1395 * @dev: Device 1396 * @node: Device node to be parsed 1397 * @csd: Parsed data from port endpoint node 1398 * 1399 * Return 0 on success or a negative error code on failure 1400 */ 1401 static int camss_of_parse_endpoint_node(struct device *dev, 1402 struct device_node *node, 1403 struct camss_async_subdev *csd) 1404 { 1405 struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg; 1406 struct v4l2_mbus_config_mipi_csi2 *mipi_csi2; 1407 struct v4l2_fwnode_endpoint vep = { { 0 } }; 1408 unsigned int i; 1409 1410 v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep); 1411 1412 csd->interface.csiphy_id = vep.base.port; 1413 1414 mipi_csi2 = &vep.bus.mipi_csi2; 1415 lncfg->clk.pos = mipi_csi2->clock_lane; 1416 lncfg->clk.pol = mipi_csi2->lane_polarities[0]; 1417 lncfg->num_data = mipi_csi2->num_data_lanes; 1418 1419 lncfg->data = devm_kcalloc(dev, 1420 lncfg->num_data, sizeof(*lncfg->data), 1421 GFP_KERNEL); 1422 if (!lncfg->data) 1423 return -ENOMEM; 1424 1425 for (i = 0; i < lncfg->num_data; i++) { 1426 lncfg->data[i].pos = mipi_csi2->data_lanes[i]; 1427 lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1]; 1428 } 1429 1430 return 0; 1431 } 1432 1433 /* 1434 * camss_of_parse_ports - Parse ports node 1435 * @dev: Device 1436 * @notifier: v4l2_device notifier data 1437 * 1438 * Return number of "port" nodes found in "ports" node 1439 */ 1440 static int camss_of_parse_ports(struct camss *camss) 1441 { 1442 struct device *dev = camss->dev; 1443 struct device_node *node = NULL; 1444 struct device_node *remote = NULL; 1445 int ret, num_subdevs = 0; 1446 1447 for_each_endpoint_of_node(dev->of_node, node) { 1448 struct camss_async_subdev *csd; 1449 1450 if (!of_device_is_available(node)) 1451 continue; 1452 1453 remote = of_graph_get_remote_port_parent(node); 1454 if (!remote) { 1455 dev_err(dev, "Cannot get remote parent\n"); 1456 ret = -EINVAL; 1457 goto err_cleanup; 1458 } 1459 1460 csd = v4l2_async_nf_add_fwnode(&camss->notifier, 1461 of_fwnode_handle(remote), 1462 struct camss_async_subdev); 1463 of_node_put(remote); 1464 if (IS_ERR(csd)) { 1465 ret = PTR_ERR(csd); 1466 goto err_cleanup; 1467 } 1468 1469 ret = camss_of_parse_endpoint_node(dev, node, csd); 1470 if (ret < 0) 1471 goto err_cleanup; 1472 1473 num_subdevs++; 1474 } 1475 1476 return num_subdevs; 1477 1478 err_cleanup: 1479 of_node_put(node); 1480 return ret; 1481 } 1482 1483 /* 1484 * camss_init_subdevices - Initialize subdev structures and resources 1485 * @camss: CAMSS device 1486 * 1487 * Return 0 on success or a negative error code on failure 1488 */ 1489 static int camss_init_subdevices(struct camss *camss) 1490 { 1491 const struct camss_resources *res = camss->res; 1492 unsigned int i; 1493 int ret; 1494 1495 for (i = 0; i < camss->res->csiphy_num; i++) { 1496 ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], 1497 &res->csiphy_res[i], i); 1498 if (ret < 0) { 1499 dev_err(camss->dev, 1500 "Failed to init csiphy%d sub-device: %d\n", 1501 i, ret); 1502 return ret; 1503 } 1504 } 1505 1506 /* note: SM8250 requires VFE to be initialized before CSID */ 1507 for (i = 0; i < camss->res->vfe_num; i++) { 1508 ret = msm_vfe_subdev_init(camss, &camss->vfe[i], 1509 &res->vfe_res[i], i); 1510 if (ret < 0) { 1511 dev_err(camss->dev, 1512 "Fail to init vfe%d sub-device: %d\n", i, ret); 1513 return ret; 1514 } 1515 } 1516 1517 for (i = 0; i < camss->res->csid_num; i++) { 1518 ret = msm_csid_subdev_init(camss, &camss->csid[i], 1519 &res->csid_res[i], i); 1520 if (ret < 0) { 1521 dev_err(camss->dev, 1522 "Failed to init csid%d sub-device: %d\n", 1523 i, ret); 1524 return ret; 1525 } 1526 } 1527 1528 ret = msm_ispif_subdev_init(camss, res->ispif_res); 1529 if (ret < 0) { 1530 dev_err(camss->dev, "Failed to init ispif sub-device: %d\n", 1531 ret); 1532 return ret; 1533 } 1534 1535 return 0; 1536 } 1537 1538 /* 1539 * camss_register_entities - Register subdev nodes and create links 1540 * @camss: CAMSS device 1541 * 1542 * Return 0 on success or a negative error code on failure 1543 */ 1544 static int camss_register_entities(struct camss *camss) 1545 { 1546 int i, j, k; 1547 int ret; 1548 1549 for (i = 0; i < camss->res->csiphy_num; i++) { 1550 ret = msm_csiphy_register_entity(&camss->csiphy[i], 1551 &camss->v4l2_dev); 1552 if (ret < 0) { 1553 dev_err(camss->dev, 1554 "Failed to register csiphy%d entity: %d\n", 1555 i, ret); 1556 goto err_reg_csiphy; 1557 } 1558 } 1559 1560 for (i = 0; i < camss->res->csid_num; i++) { 1561 ret = msm_csid_register_entity(&camss->csid[i], 1562 &camss->v4l2_dev); 1563 if (ret < 0) { 1564 dev_err(camss->dev, 1565 "Failed to register csid%d entity: %d\n", 1566 i, ret); 1567 goto err_reg_csid; 1568 } 1569 } 1570 1571 ret = msm_ispif_register_entities(camss->ispif, 1572 &camss->v4l2_dev); 1573 if (ret < 0) { 1574 dev_err(camss->dev, "Failed to register ispif entities: %d\n", 1575 ret); 1576 goto err_reg_ispif; 1577 } 1578 1579 for (i = 0; i < camss->res->vfe_num; i++) { 1580 ret = msm_vfe_register_entities(&camss->vfe[i], 1581 &camss->v4l2_dev); 1582 if (ret < 0) { 1583 dev_err(camss->dev, 1584 "Failed to register vfe%d entities: %d\n", 1585 i, ret); 1586 goto err_reg_vfe; 1587 } 1588 } 1589 1590 for (i = 0; i < camss->res->csiphy_num; i++) { 1591 for (j = 0; j < camss->res->csid_num; j++) { 1592 ret = media_create_pad_link( 1593 &camss->csiphy[i].subdev.entity, 1594 MSM_CSIPHY_PAD_SRC, 1595 &camss->csid[j].subdev.entity, 1596 MSM_CSID_PAD_SINK, 1597 0); 1598 if (ret < 0) { 1599 dev_err(camss->dev, 1600 "Failed to link %s->%s entities: %d\n", 1601 camss->csiphy[i].subdev.entity.name, 1602 camss->csid[j].subdev.entity.name, 1603 ret); 1604 goto err_link; 1605 } 1606 } 1607 } 1608 1609 if (camss->ispif) { 1610 for (i = 0; i < camss->res->csid_num; i++) { 1611 for (j = 0; j < camss->ispif->line_num; j++) { 1612 ret = media_create_pad_link( 1613 &camss->csid[i].subdev.entity, 1614 MSM_CSID_PAD_SRC, 1615 &camss->ispif->line[j].subdev.entity, 1616 MSM_ISPIF_PAD_SINK, 1617 0); 1618 if (ret < 0) { 1619 dev_err(camss->dev, 1620 "Failed to link %s->%s entities: %d\n", 1621 camss->csid[i].subdev.entity.name, 1622 camss->ispif->line[j].subdev.entity.name, 1623 ret); 1624 goto err_link; 1625 } 1626 } 1627 } 1628 1629 for (i = 0; i < camss->ispif->line_num; i++) 1630 for (k = 0; k < camss->res->vfe_num; k++) 1631 for (j = 0; j < camss->vfe[k].line_num; j++) { 1632 struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev; 1633 struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; 1634 1635 ret = media_create_pad_link(&ispif->entity, 1636 MSM_ISPIF_PAD_SRC, 1637 &vfe->entity, 1638 MSM_VFE_PAD_SINK, 1639 0); 1640 if (ret < 0) { 1641 dev_err(camss->dev, 1642 "Failed to link %s->%s entities: %d\n", 1643 ispif->entity.name, 1644 vfe->entity.name, 1645 ret); 1646 goto err_link; 1647 } 1648 } 1649 } else { 1650 for (i = 0; i < camss->res->csid_num; i++) 1651 for (k = 0; k < camss->res->vfe_num; k++) 1652 for (j = 0; j < camss->vfe[k].line_num; j++) { 1653 struct v4l2_subdev *csid = &camss->csid[i].subdev; 1654 struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; 1655 1656 ret = media_create_pad_link(&csid->entity, 1657 MSM_CSID_PAD_FIRST_SRC + j, 1658 &vfe->entity, 1659 MSM_VFE_PAD_SINK, 1660 0); 1661 if (ret < 0) { 1662 dev_err(camss->dev, 1663 "Failed to link %s->%s entities: %d\n", 1664 csid->entity.name, 1665 vfe->entity.name, 1666 ret); 1667 goto err_link; 1668 } 1669 } 1670 } 1671 1672 return 0; 1673 1674 err_link: 1675 i = camss->res->vfe_num; 1676 err_reg_vfe: 1677 for (i--; i >= 0; i--) 1678 msm_vfe_unregister_entities(&camss->vfe[i]); 1679 1680 err_reg_ispif: 1681 msm_ispif_unregister_entities(camss->ispif); 1682 1683 i = camss->res->csid_num; 1684 err_reg_csid: 1685 for (i--; i >= 0; i--) 1686 msm_csid_unregister_entity(&camss->csid[i]); 1687 1688 i = camss->res->csiphy_num; 1689 err_reg_csiphy: 1690 for (i--; i >= 0; i--) 1691 msm_csiphy_unregister_entity(&camss->csiphy[i]); 1692 1693 return ret; 1694 } 1695 1696 /* 1697 * camss_unregister_entities - Unregister subdev nodes 1698 * @camss: CAMSS device 1699 * 1700 * Return 0 on success or a negative error code on failure 1701 */ 1702 static void camss_unregister_entities(struct camss *camss) 1703 { 1704 unsigned int i; 1705 1706 for (i = 0; i < camss->res->csiphy_num; i++) 1707 msm_csiphy_unregister_entity(&camss->csiphy[i]); 1708 1709 for (i = 0; i < camss->res->csid_num; i++) 1710 msm_csid_unregister_entity(&camss->csid[i]); 1711 1712 msm_ispif_unregister_entities(camss->ispif); 1713 1714 for (i = 0; i < camss->res->vfe_num; i++) 1715 msm_vfe_unregister_entities(&camss->vfe[i]); 1716 } 1717 1718 static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async, 1719 struct v4l2_subdev *subdev, 1720 struct v4l2_async_connection *asd) 1721 { 1722 struct camss *camss = container_of(async, struct camss, notifier); 1723 struct camss_async_subdev *csd = 1724 container_of(asd, struct camss_async_subdev, asd); 1725 u8 id = csd->interface.csiphy_id; 1726 struct csiphy_device *csiphy = &camss->csiphy[id]; 1727 1728 csiphy->cfg.csi2 = &csd->interface.csi2; 1729 subdev->host_priv = csiphy; 1730 1731 return 0; 1732 } 1733 1734 static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async) 1735 { 1736 struct camss *camss = container_of(async, struct camss, notifier); 1737 struct v4l2_device *v4l2_dev = &camss->v4l2_dev; 1738 struct v4l2_subdev *sd; 1739 int ret; 1740 1741 list_for_each_entry(sd, &v4l2_dev->subdevs, list) { 1742 if (sd->host_priv) { 1743 struct media_entity *sensor = &sd->entity; 1744 struct csiphy_device *csiphy = 1745 (struct csiphy_device *) sd->host_priv; 1746 struct media_entity *input = &csiphy->subdev.entity; 1747 unsigned int i; 1748 1749 for (i = 0; i < sensor->num_pads; i++) { 1750 if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE) 1751 break; 1752 } 1753 if (i == sensor->num_pads) { 1754 dev_err(camss->dev, 1755 "No source pad in external entity\n"); 1756 return -EINVAL; 1757 } 1758 1759 ret = media_create_pad_link(sensor, i, 1760 input, MSM_CSIPHY_PAD_SINK, 1761 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 1762 if (ret < 0) { 1763 dev_err(camss->dev, 1764 "Failed to link %s->%s entities: %d\n", 1765 sensor->name, input->name, ret); 1766 return ret; 1767 } 1768 } 1769 } 1770 1771 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev); 1772 if (ret < 0) 1773 return ret; 1774 1775 return media_device_register(&camss->media_dev); 1776 } 1777 1778 static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = { 1779 .bound = camss_subdev_notifier_bound, 1780 .complete = camss_subdev_notifier_complete, 1781 }; 1782 1783 static const struct media_device_ops camss_media_ops = { 1784 .link_notify = v4l2_pipeline_link_notify, 1785 }; 1786 1787 static int camss_configure_pd(struct camss *camss) 1788 { 1789 const struct camss_resources *res = camss->res; 1790 struct device *dev = camss->dev; 1791 int vfepd_num; 1792 int i; 1793 int ret; 1794 1795 camss->genpd_num = of_count_phandle_with_args(dev->of_node, 1796 "power-domains", 1797 "#power-domain-cells"); 1798 if (camss->genpd_num < 0) { 1799 dev_err(dev, "Power domains are not defined for camss\n"); 1800 return camss->genpd_num; 1801 } 1802 1803 /* 1804 * If a platform device has just one power domain, then it is attached 1805 * at platform_probe() level, thus there shall be no need and even no 1806 * option to attach it again, this is the case for CAMSS on MSM8916. 1807 */ 1808 if (camss->genpd_num == 1) 1809 return 0; 1810 1811 /* count the # of VFEs which have flagged power-domain */ 1812 for (vfepd_num = i = 0; i < camss->res->vfe_num; i++) { 1813 if (res->vfe_res[i].has_pd) 1814 vfepd_num++; 1815 } 1816 1817 /* 1818 * If the number of power-domains is greater than the number of VFEs 1819 * then the additional power-domain is for the entire CAMSS block. 1820 */ 1821 if (!(camss->genpd_num > vfepd_num)) 1822 return 0; 1823 1824 /* 1825 * If a power-domain name is defined try to use it. 1826 * It is possible we are running a new kernel with an old dtb so 1827 * fallback to indexes even if a pd_name is defined but not found. 1828 */ 1829 if (camss->res->pd_name) { 1830 camss->genpd = dev_pm_domain_attach_by_name(camss->dev, 1831 camss->res->pd_name); 1832 if (IS_ERR(camss->genpd)) { 1833 ret = PTR_ERR(camss->genpd); 1834 goto fail_pm; 1835 } 1836 } 1837 1838 if (!camss->genpd) { 1839 /* 1840 * Legacy magic index. TITAN_TOP GDSC must be the last 1841 * item in the power-domain list. 1842 */ 1843 camss->genpd = dev_pm_domain_attach_by_id(camss->dev, 1844 camss->genpd_num - 1); 1845 } 1846 if (IS_ERR_OR_NULL(camss->genpd)) { 1847 if (!camss->genpd) 1848 ret = -ENODEV; 1849 else 1850 ret = PTR_ERR(camss->genpd); 1851 goto fail_pm; 1852 } 1853 camss->genpd_link = device_link_add(camss->dev, camss->genpd, 1854 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | 1855 DL_FLAG_RPM_ACTIVE); 1856 if (!camss->genpd_link) { 1857 ret = -EINVAL; 1858 goto fail_pm; 1859 } 1860 1861 return 0; 1862 1863 fail_pm: 1864 dev_pm_domain_detach(camss->genpd, true); 1865 1866 return ret; 1867 } 1868 1869 static int camss_icc_get(struct camss *camss) 1870 { 1871 const struct resources_icc *icc_res; 1872 int i; 1873 1874 icc_res = camss->res->icc_res; 1875 1876 for (i = 0; i < camss->res->icc_path_num; i++) { 1877 camss->icc_path[i] = devm_of_icc_get(camss->dev, 1878 icc_res[i].name); 1879 if (IS_ERR(camss->icc_path[i])) 1880 return PTR_ERR(camss->icc_path[i]); 1881 } 1882 1883 return 0; 1884 } 1885 1886 static void camss_genpd_subdevice_cleanup(struct camss *camss) 1887 { 1888 int i; 1889 1890 for (i = 0; i < camss->res->vfe_num; i++) 1891 msm_vfe_genpd_cleanup(&camss->vfe[i]); 1892 } 1893 1894 static void camss_genpd_cleanup(struct camss *camss) 1895 { 1896 if (camss->genpd_num == 1) 1897 return; 1898 1899 camss_genpd_subdevice_cleanup(camss); 1900 1901 if (camss->genpd_link) 1902 device_link_del(camss->genpd_link); 1903 1904 dev_pm_domain_detach(camss->genpd, true); 1905 } 1906 1907 /* 1908 * camss_probe - Probe CAMSS platform device 1909 * @pdev: Pointer to CAMSS platform device 1910 * 1911 * Return 0 on success or a negative error code on failure 1912 */ 1913 static int camss_probe(struct platform_device *pdev) 1914 { 1915 struct device *dev = &pdev->dev; 1916 struct camss *camss; 1917 int num_subdevs; 1918 int ret; 1919 1920 camss = devm_kzalloc(dev, sizeof(*camss), GFP_KERNEL); 1921 if (!camss) 1922 return -ENOMEM; 1923 1924 camss->res = of_device_get_match_data(dev); 1925 1926 atomic_set(&camss->ref_count, 0); 1927 camss->dev = dev; 1928 platform_set_drvdata(pdev, camss); 1929 1930 camss->csiphy = devm_kcalloc(dev, camss->res->csiphy_num, 1931 sizeof(*camss->csiphy), GFP_KERNEL); 1932 if (!camss->csiphy) 1933 return -ENOMEM; 1934 1935 camss->csid = devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->csid), 1936 GFP_KERNEL); 1937 if (!camss->csid) 1938 return -ENOMEM; 1939 1940 if (camss->res->version == CAMSS_8x16 || 1941 camss->res->version == CAMSS_8x96) { 1942 camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL); 1943 if (!camss->ispif) 1944 return -ENOMEM; 1945 } 1946 1947 camss->vfe = devm_kcalloc(dev, camss->res->vfe_num, 1948 sizeof(*camss->vfe), GFP_KERNEL); 1949 if (!camss->vfe) 1950 return -ENOMEM; 1951 1952 ret = camss_icc_get(camss); 1953 if (ret < 0) 1954 return ret; 1955 1956 ret = camss_configure_pd(camss); 1957 if (ret < 0) { 1958 dev_err(dev, "Failed to configure power domains: %d\n", ret); 1959 return ret; 1960 } 1961 1962 ret = camss_init_subdevices(camss); 1963 if (ret < 0) 1964 goto err_genpd_cleanup; 1965 1966 ret = dma_set_mask_and_coherent(dev, 0xffffffff); 1967 if (ret) 1968 goto err_genpd_cleanup; 1969 1970 camss->media_dev.dev = camss->dev; 1971 strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem", 1972 sizeof(camss->media_dev.model)); 1973 camss->media_dev.ops = &camss_media_ops; 1974 media_device_init(&camss->media_dev); 1975 1976 camss->v4l2_dev.mdev = &camss->media_dev; 1977 ret = v4l2_device_register(camss->dev, &camss->v4l2_dev); 1978 if (ret < 0) { 1979 dev_err(dev, "Failed to register V4L2 device: %d\n", ret); 1980 goto err_genpd_cleanup; 1981 } 1982 1983 v4l2_async_nf_init(&camss->notifier, &camss->v4l2_dev); 1984 1985 num_subdevs = camss_of_parse_ports(camss); 1986 if (num_subdevs < 0) { 1987 ret = num_subdevs; 1988 goto err_v4l2_device_unregister; 1989 } 1990 1991 ret = camss_register_entities(camss); 1992 if (ret < 0) 1993 goto err_v4l2_device_unregister; 1994 1995 if (num_subdevs) { 1996 camss->notifier.ops = &camss_subdev_notifier_ops; 1997 1998 ret = v4l2_async_nf_register(&camss->notifier); 1999 if (ret) { 2000 dev_err(dev, 2001 "Failed to register async subdev nodes: %d\n", 2002 ret); 2003 goto err_register_subdevs; 2004 } 2005 } else { 2006 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev); 2007 if (ret < 0) { 2008 dev_err(dev, "Failed to register subdev nodes: %d\n", 2009 ret); 2010 goto err_register_subdevs; 2011 } 2012 2013 ret = media_device_register(&camss->media_dev); 2014 if (ret < 0) { 2015 dev_err(dev, "Failed to register media device: %d\n", 2016 ret); 2017 goto err_register_subdevs; 2018 } 2019 } 2020 2021 pm_runtime_enable(dev); 2022 2023 return 0; 2024 2025 err_register_subdevs: 2026 camss_unregister_entities(camss); 2027 err_v4l2_device_unregister: 2028 v4l2_device_unregister(&camss->v4l2_dev); 2029 v4l2_async_nf_cleanup(&camss->notifier); 2030 err_genpd_cleanup: 2031 camss_genpd_cleanup(camss); 2032 2033 return ret; 2034 } 2035 2036 void camss_delete(struct camss *camss) 2037 { 2038 v4l2_device_unregister(&camss->v4l2_dev); 2039 media_device_unregister(&camss->media_dev); 2040 media_device_cleanup(&camss->media_dev); 2041 2042 pm_runtime_disable(camss->dev); 2043 } 2044 2045 /* 2046 * camss_remove - Remove CAMSS platform device 2047 * @pdev: Pointer to CAMSS platform device 2048 * 2049 * Always returns 0. 2050 */ 2051 static void camss_remove(struct platform_device *pdev) 2052 { 2053 struct camss *camss = platform_get_drvdata(pdev); 2054 2055 v4l2_async_nf_unregister(&camss->notifier); 2056 v4l2_async_nf_cleanup(&camss->notifier); 2057 camss_unregister_entities(camss); 2058 2059 if (atomic_read(&camss->ref_count) == 0) 2060 camss_delete(camss); 2061 2062 camss_genpd_cleanup(camss); 2063 } 2064 2065 static const struct camss_resources msm8916_resources = { 2066 .version = CAMSS_8x16, 2067 .csiphy_res = csiphy_res_8x16, 2068 .csid_res = csid_res_8x16, 2069 .ispif_res = &ispif_res_8x16, 2070 .vfe_res = vfe_res_8x16, 2071 .csiphy_num = ARRAY_SIZE(csiphy_res_8x16), 2072 .csid_num = ARRAY_SIZE(csid_res_8x16), 2073 .vfe_num = ARRAY_SIZE(vfe_res_8x16), 2074 }; 2075 2076 static const struct camss_resources msm8996_resources = { 2077 .version = CAMSS_8x96, 2078 .csiphy_res = csiphy_res_8x96, 2079 .csid_res = csid_res_8x96, 2080 .ispif_res = &ispif_res_8x96, 2081 .vfe_res = vfe_res_8x96, 2082 .csiphy_num = ARRAY_SIZE(csiphy_res_8x96), 2083 .csid_num = ARRAY_SIZE(csid_res_8x96), 2084 .vfe_num = ARRAY_SIZE(vfe_res_8x96), 2085 }; 2086 2087 static const struct camss_resources sdm660_resources = { 2088 .version = CAMSS_660, 2089 .csiphy_res = csiphy_res_660, 2090 .csid_res = csid_res_660, 2091 .ispif_res = &ispif_res_660, 2092 .vfe_res = vfe_res_660, 2093 .csiphy_num = ARRAY_SIZE(csiphy_res_660), 2094 .csid_num = ARRAY_SIZE(csid_res_660), 2095 .vfe_num = ARRAY_SIZE(vfe_res_660), 2096 }; 2097 2098 static const struct camss_resources sdm845_resources = { 2099 .version = CAMSS_845, 2100 .csiphy_res = csiphy_res_845, 2101 .csid_res = csid_res_845, 2102 .vfe_res = vfe_res_845, 2103 .csiphy_num = ARRAY_SIZE(csiphy_res_845), 2104 .csid_num = ARRAY_SIZE(csid_res_845), 2105 .vfe_num = ARRAY_SIZE(vfe_res_845), 2106 }; 2107 2108 static const struct camss_resources sm8250_resources = { 2109 .version = CAMSS_8250, 2110 .pd_name = "top", 2111 .csiphy_res = csiphy_res_8250, 2112 .csid_res = csid_res_8250, 2113 .vfe_res = vfe_res_8250, 2114 .icc_res = icc_res_sm8250, 2115 .icc_path_num = ARRAY_SIZE(icc_res_sm8250), 2116 .csiphy_num = ARRAY_SIZE(csiphy_res_8250), 2117 .csid_num = ARRAY_SIZE(csid_res_8250), 2118 .vfe_num = ARRAY_SIZE(vfe_res_8250), 2119 }; 2120 2121 static const struct camss_resources sc8280xp_resources = { 2122 .version = CAMSS_8280XP, 2123 .pd_name = "top", 2124 .csiphy_res = csiphy_res_sc8280xp, 2125 .csid_res = csid_res_sc8280xp, 2126 .ispif_res = NULL, 2127 .vfe_res = vfe_res_sc8280xp, 2128 .icc_res = icc_res_sc8280xp, 2129 .icc_path_num = ARRAY_SIZE(icc_res_sc8280xp), 2130 .csiphy_num = ARRAY_SIZE(csiphy_res_sc8280xp), 2131 .csid_num = ARRAY_SIZE(csid_res_sc8280xp), 2132 .vfe_num = ARRAY_SIZE(vfe_res_sc8280xp), 2133 }; 2134 2135 static const struct of_device_id camss_dt_match[] = { 2136 { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, 2137 { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, 2138 { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, 2139 { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, 2140 { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, 2141 { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, 2142 { } 2143 }; 2144 2145 MODULE_DEVICE_TABLE(of, camss_dt_match); 2146 2147 static int __maybe_unused camss_runtime_suspend(struct device *dev) 2148 { 2149 struct camss *camss = dev_get_drvdata(dev); 2150 int i; 2151 int ret; 2152 2153 for (i = 0; i < camss->res->icc_path_num; i++) { 2154 ret = icc_set_bw(camss->icc_path[i], 0, 0); 2155 if (ret) 2156 return ret; 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int __maybe_unused camss_runtime_resume(struct device *dev) 2163 { 2164 struct camss *camss = dev_get_drvdata(dev); 2165 const struct resources_icc *icc_res = camss->res->icc_res; 2166 int i; 2167 int ret; 2168 2169 for (i = 0; i < camss->res->icc_path_num; i++) { 2170 ret = icc_set_bw(camss->icc_path[i], 2171 icc_res[i].icc_bw_tbl.avg, 2172 icc_res[i].icc_bw_tbl.peak); 2173 if (ret) 2174 return ret; 2175 } 2176 2177 return 0; 2178 } 2179 2180 static const struct dev_pm_ops camss_pm_ops = { 2181 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2182 pm_runtime_force_resume) 2183 SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL) 2184 }; 2185 2186 static struct platform_driver qcom_camss_driver = { 2187 .probe = camss_probe, 2188 .remove_new = camss_remove, 2189 .driver = { 2190 .name = "qcom-camss", 2191 .of_match_table = camss_dt_match, 2192 .pm = &camss_pm_ops, 2193 }, 2194 }; 2195 2196 module_platform_driver(qcom_camss_driver); 2197 2198 MODULE_ALIAS("platform:qcom-camss"); 2199 MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver"); 2200 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 2201 MODULE_LICENSE("GPL v2"); 2202