1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-480.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v480 (SM8250) 6 * 7 * Copyright (C) 2020-2021 Linaro Ltd. 8 * Copyright (C) 2021 Jonathan Marek 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 15 #include "camss.h" 16 #include "camss-vfe.h" 17 18 #define VFE_GLOBAL_RESET_CMD (vfe_is_lite(vfe) ? 0x0c : 0x1c) 19 #define GLOBAL_RESET_HW_AND_REG (vfe_is_lite(vfe) ? BIT(1) : BIT(0)) 20 21 #define VFE_REG_UPDATE_CMD (vfe_is_lite(vfe) ? 0x20 : 0x34) 22 static inline int reg_update_rdi(struct vfe_device *vfe, int n) 23 { 24 return vfe_is_lite(vfe) ? BIT(n) : BIT(1 + (n)); 25 } 26 27 #define REG_UPDATE_RDI reg_update_rdi 28 #define VFE_IRQ_CMD (vfe_is_lite(vfe) ? 0x24 : 0x38) 29 #define IRQ_CMD_GLOBAL_CLEAR BIT(0) 30 31 #define VFE_IRQ_MASK(n) ((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4) 32 #define IRQ_MASK_0_RESET_ACK (vfe_is_lite(vfe) ? BIT(17) : BIT(0)) 33 #define IRQ_MASK_0_BUS_TOP_IRQ (vfe_is_lite(vfe) ? BIT(4) : BIT(7)) 34 #define VFE_IRQ_CLEAR(n) ((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4) 35 #define VFE_IRQ_STATUS(n) ((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4) 36 37 #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x1a00 : 0xaa00) 38 39 #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) 40 #define WM_CGC_OVERRIDE_ALL (0x3FFFFFF) 41 42 #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xdc) 43 44 #define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) 45 static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n) 46 { 47 return vfe_is_lite(vfe) ? BIT(n) : BIT(3 + (n)); 48 } 49 50 #define BUS_IRQ_MASK_0_RDI_RUP bus_irq_mask_0_rdi_rup 51 static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) 52 { 53 return vfe_is_lite(vfe) ? BIT(4 + (n)) : BIT(6 + (n)); 54 } 55 56 #define BUS_IRQ_MASK_0_COMP_DONE bus_irq_mask_0_comp_done 57 #define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) 58 #define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) 59 #define VFE_BUS_IRQ_CLEAR_GLOBAL (BUS_REG_BASE + 0x30) 60 61 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) 62 #define WM_CFG_EN (0) 63 #define WM_CFG_MODE (16) 64 #define MODE_QCOM_PLAIN (0) 65 #define MODE_MIPI_RAW (1) 66 #define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) 67 #define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) 68 #define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) 69 #define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) 70 #define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100) 71 #define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) 72 #define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) 73 #define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100) 74 #define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100) 75 #define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100) 76 77 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) 78 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) 79 #define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) 80 #define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) 81 82 #define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) 83 #define VFE_BUS_WM_BURST_LIMIT(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) 84 85 /* for titan 480, each bus client is hardcoded to a specific path 86 * and each bus client is part of a hardcoded "comp group" 87 */ 88 #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0 : 23) + (n)) 89 #define RDI_COMP_GROUP(n) ((vfe_is_lite(vfe) ? 0 : 11) + (n)) 90 91 #define MAX_VFE_OUTPUT_LINES 4 92 93 static void vfe_global_reset(struct vfe_device *vfe) 94 { 95 writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); 96 writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); 97 } 98 99 static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) 100 { 101 struct v4l2_pix_format_mplane *pix = 102 &line->video_out.active_fmt.fmt.pix_mp; 103 104 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ 105 106 /* no clock gating at bus input */ 107 writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); 108 109 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); 110 111 writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height, 112 vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); 113 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); 114 writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH, 115 vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); 116 writel_relaxed(pix->plane_fmt[0].bytesperline, 117 vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); 118 writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); 119 120 /* no dropped frames, one irq per frame */ 121 writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); 122 writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); 123 writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); 124 writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); 125 126 writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE, 127 vfe->base + VFE_BUS_WM_CFG(wm)); 128 } 129 130 static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) 131 { 132 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ 133 writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm)); 134 } 135 136 static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, 137 struct vfe_line *line) 138 { 139 wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ 140 writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); 141 } 142 143 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 144 { 145 vfe->reg_update |= REG_UPDATE_RDI(vfe, line_id); 146 writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD); 147 } 148 149 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 150 enum vfe_line_id line_id) 151 { 152 vfe->reg_update &= ~REG_UPDATE_RDI(vfe, line_id); 153 } 154 155 static void vfe_enable_irq(struct vfe_device *vfe) 156 { 157 int i; 158 u32 bus_irq_mask = 0; 159 160 if (!vfe->stream_count) 161 /* enable reset ack IRQ and top BUS status IRQ */ 162 writel(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, 163 vfe->base + VFE_IRQ_MASK(0)); 164 165 for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) { 166 /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */ 167 if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED || 168 vfe->line[i].output.state == VFE_OUTPUT_ON) { 169 bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i) 170 | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)); 171 } 172 } 173 174 writel(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0)); 175 } 176 177 static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id); 178 179 /* 180 * vfe_isr - VFE module interrupt handler 181 * @irq: Interrupt line 182 * @dev: VFE device 183 * 184 * Return IRQ_HANDLED on success 185 */ 186 static irqreturn_t vfe_isr(int irq, void *dev) 187 { 188 struct vfe_device *vfe = dev; 189 u32 status; 190 int i; 191 192 status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0)); 193 writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0)); 194 writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD); 195 196 if (status & IRQ_MASK_0_RESET_ACK) 197 vfe_isr_reset_ack(vfe); 198 199 if (status & IRQ_MASK_0_BUS_TOP_IRQ) { 200 u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0)); 201 202 writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0)); 203 writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL); 204 205 /* Loop through all WMs IRQs */ 206 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) { 207 if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, i)) 208 vfe_isr_reg_update(vfe, i); 209 210 if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i))) 211 vfe_buf_done(vfe, i); 212 } 213 } 214 215 return IRQ_HANDLED; 216 } 217 218 /* 219 * vfe_halt - Trigger halt on VFE module and wait to complete 220 * @vfe: VFE device 221 * 222 * Return 0 on success or a negative error code otherwise 223 */ 224 static int vfe_halt(struct vfe_device *vfe) 225 { 226 /* rely on vfe_disable_output() to stop the VFE */ 227 return 0; 228 } 229 230 /* 231 * vfe_isr_reg_update - Process reg update interrupt 232 * @vfe: VFE Device 233 * @line_id: VFE line 234 */ 235 static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 236 { 237 struct vfe_output *output; 238 unsigned long flags; 239 240 spin_lock_irqsave(&vfe->output_lock, flags); 241 vfe_reg_update_clear(vfe, line_id); 242 243 output = &vfe->line[line_id].output; 244 245 if (output->wait_reg_update) { 246 output->wait_reg_update = 0; 247 complete(&output->reg_update); 248 } 249 250 spin_unlock_irqrestore(&vfe->output_lock, flags); 251 } 252 253 static const struct camss_video_ops vfe_video_ops_480 = { 254 .queue_buffer = vfe_queue_buffer_v2, 255 .flush_buffers = vfe_flush_buffers, 256 }; 257 258 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 259 { 260 vfe->video_ops = vfe_video_ops_480; 261 } 262 263 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 264 { 265 /* nop */ 266 } 267 268 static void vfe_violation_read(struct vfe_device *vfe) 269 { 270 /* nop */ 271 } 272 273 static void vfe_buf_done_480(struct vfe_device *vfe, int port_id) 274 { 275 /* nop */ 276 } 277 278 const struct vfe_hw_ops vfe_ops_480 = { 279 .enable_irq = vfe_enable_irq, 280 .global_reset = vfe_global_reset, 281 .hw_version = vfe_hw_version, 282 .isr = vfe_isr, 283 .isr_read = vfe_isr_read, 284 .reg_update = vfe_reg_update, 285 .reg_update_clear = vfe_reg_update_clear, 286 .pm_domain_off = vfe_pm_domain_off, 287 .pm_domain_on = vfe_pm_domain_on, 288 .subdev_init = vfe_subdev_init, 289 .vfe_disable = vfe_disable, 290 .vfe_enable = vfe_enable_v2, 291 .vfe_halt = vfe_halt, 292 .violation_read = vfe_violation_read, 293 .vfe_wm_start = vfe_wm_start, 294 .vfe_wm_stop = vfe_wm_stop, 295 .vfe_buf_done = vfe_buf_done_480, 296 .vfe_wm_update = vfe_wm_update, 297 }; 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