1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <media/media-entity.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-subdev.h> 21 22 #include "camss-csiphy.h" 23 #include "camss.h" 24 25 #define MSM_CSIPHY_NAME "msm_csiphy" 26 27 struct csiphy_format { 28 u32 code; 29 u8 bpp; 30 }; 31 32 static const struct csiphy_format csiphy_formats_8x16[] = { 33 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 34 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 35 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 36 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 37 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 38 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 39 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 40 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 41 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 42 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 43 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 44 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 45 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 46 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 47 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 48 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 49 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 50 }; 51 52 static const struct csiphy_format csiphy_formats_8x96[] = { 53 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 54 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 55 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 56 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 57 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 58 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 59 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 60 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 61 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 62 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 63 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 64 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 65 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 66 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 67 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 68 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 69 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 70 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 71 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 72 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 73 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 74 }; 75 76 static const struct csiphy_format csiphy_formats_sdm845[] = { 77 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 78 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 79 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 80 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 81 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 82 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 83 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 84 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 85 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 86 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 87 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 88 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 89 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 90 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 91 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 92 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 93 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 94 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 95 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 96 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 97 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 98 }; 99 100 /* 101 * csiphy_get_bpp - map media bus format to bits per pixel 102 * @formats: supported media bus formats array 103 * @nformats: size of @formats array 104 * @code: media bus format code 105 * 106 * Return number of bits per pixel 107 */ 108 static u8 csiphy_get_bpp(const struct csiphy_format *formats, 109 unsigned int nformats, u32 code) 110 { 111 unsigned int i; 112 113 for (i = 0; i < nformats; i++) 114 if (code == formats[i].code) 115 return formats[i].bpp; 116 117 WARN(1, "Unknown format\n"); 118 119 return formats[0].bpp; 120 } 121 122 /* 123 * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module 124 * @csiphy: CSIPHY device 125 */ 126 static int csiphy_set_clock_rates(struct csiphy_device *csiphy) 127 { 128 struct device *dev = csiphy->camss->dev; 129 s64 link_freq; 130 int i, j; 131 int ret; 132 133 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 134 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 135 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 136 137 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 138 if (link_freq < 0) 139 link_freq = 0; 140 141 for (i = 0; i < csiphy->nclocks; i++) { 142 struct camss_clock *clock = &csiphy->clock[i]; 143 144 if (csiphy->rate_set[i]) { 145 u64 min_rate = link_freq / 4; 146 long round_rate; 147 148 camss_add_clock_margin(&min_rate); 149 150 for (j = 0; j < clock->nfreqs; j++) 151 if (min_rate < clock->freq[j]) 152 break; 153 154 if (j == clock->nfreqs) { 155 dev_err(dev, 156 "Pixel clock is too high for CSIPHY\n"); 157 return -EINVAL; 158 } 159 160 /* if sensor pixel clock is not available */ 161 /* set highest possible CSIPHY clock rate */ 162 if (min_rate == 0) 163 j = clock->nfreqs - 1; 164 165 round_rate = clk_round_rate(clock->clk, clock->freq[j]); 166 if (round_rate < 0) { 167 dev_err(dev, "clk round rate failed: %ld\n", 168 round_rate); 169 return -EINVAL; 170 } 171 172 csiphy->timer_clk_rate = round_rate; 173 174 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); 175 if (ret < 0) { 176 dev_err(dev, "clk set rate failed: %d\n", ret); 177 return ret; 178 } 179 } 180 } 181 182 return 0; 183 } 184 185 /* 186 * csiphy_set_power - Power on/off CSIPHY module 187 * @sd: CSIPHY V4L2 subdevice 188 * @on: Requested power state 189 * 190 * Return 0 on success or a negative error code otherwise 191 */ 192 static int csiphy_set_power(struct v4l2_subdev *sd, int on) 193 { 194 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 195 struct device *dev = csiphy->camss->dev; 196 197 if (on) { 198 int ret; 199 200 ret = pm_runtime_resume_and_get(dev); 201 if (ret < 0) 202 return ret; 203 204 ret = csiphy_set_clock_rates(csiphy); 205 if (ret < 0) { 206 pm_runtime_put_sync(dev); 207 return ret; 208 } 209 210 ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev); 211 if (ret < 0) { 212 pm_runtime_put_sync(dev); 213 return ret; 214 } 215 216 enable_irq(csiphy->irq); 217 218 csiphy->ops->reset(csiphy); 219 220 csiphy->ops->hw_version_read(csiphy, dev); 221 } else { 222 disable_irq(csiphy->irq); 223 224 camss_disable_clocks(csiphy->nclocks, csiphy->clock); 225 226 pm_runtime_put_sync(dev); 227 } 228 229 return 0; 230 } 231 232 /* 233 * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter 234 * @lane_cfg - CSI2 lane configuration 235 * 236 * Return lane mask 237 */ 238 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) 239 { 240 u8 lane_mask; 241 int i; 242 243 lane_mask = 1 << lane_cfg->clk.pos; 244 245 for (i = 0; i < lane_cfg->num_data; i++) 246 lane_mask |= 1 << lane_cfg->data[i].pos; 247 248 return lane_mask; 249 } 250 251 /* 252 * csiphy_stream_on - Enable streaming on CSIPHY module 253 * @csiphy: CSIPHY device 254 * 255 * Helper function to enable streaming on CSIPHY module. 256 * Main configuration of CSIPHY module is also done here. 257 * 258 * Return 0 on success or a negative error code otherwise 259 */ 260 static int csiphy_stream_on(struct csiphy_device *csiphy) 261 { 262 struct csiphy_config *cfg = &csiphy->cfg; 263 s64 link_freq; 264 u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); 265 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 266 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 267 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 268 u8 val; 269 270 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 271 272 if (link_freq < 0) { 273 dev_err(csiphy->camss->dev, 274 "Cannot get CSI2 transmitter's link frequency\n"); 275 return -EINVAL; 276 } 277 278 if (csiphy->base_clk_mux) { 279 val = readl_relaxed(csiphy->base_clk_mux); 280 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { 281 val &= ~0xf0; 282 val |= cfg->csid_id << 4; 283 } else { 284 val &= ~0xf; 285 val |= cfg->csid_id; 286 } 287 writel_relaxed(val, csiphy->base_clk_mux); 288 289 /* Enforce reg write ordering between clk mux & lane enabling */ 290 wmb(); 291 } 292 293 csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); 294 295 return 0; 296 } 297 298 /* 299 * csiphy_stream_off - Disable streaming on CSIPHY module 300 * @csiphy: CSIPHY device 301 * 302 * Helper function to disable streaming on CSIPHY module 303 */ 304 static void csiphy_stream_off(struct csiphy_device *csiphy) 305 { 306 csiphy->ops->lanes_disable(csiphy, &csiphy->cfg); 307 } 308 309 310 /* 311 * csiphy_set_stream - Enable/disable streaming on CSIPHY module 312 * @sd: CSIPHY V4L2 subdevice 313 * @enable: Requested streaming state 314 * 315 * Return 0 on success or a negative error code otherwise 316 */ 317 static int csiphy_set_stream(struct v4l2_subdev *sd, int enable) 318 { 319 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 320 int ret = 0; 321 322 if (enable) 323 ret = csiphy_stream_on(csiphy); 324 else 325 csiphy_stream_off(csiphy); 326 327 return ret; 328 } 329 330 /* 331 * __csiphy_get_format - Get pointer to format structure 332 * @csiphy: CSIPHY device 333 * @cfg: V4L2 subdev pad configuration 334 * @pad: pad from which format is requested 335 * @which: TRY or ACTIVE format 336 * 337 * Return pointer to TRY or ACTIVE format structure 338 */ 339 static struct v4l2_mbus_framefmt * 340 __csiphy_get_format(struct csiphy_device *csiphy, 341 struct v4l2_subdev_state *sd_state, 342 unsigned int pad, 343 enum v4l2_subdev_format_whence which) 344 { 345 if (which == V4L2_SUBDEV_FORMAT_TRY) 346 return v4l2_subdev_get_try_format(&csiphy->subdev, sd_state, 347 pad); 348 349 return &csiphy->fmt[pad]; 350 } 351 352 /* 353 * csiphy_try_format - Handle try format by pad subdev method 354 * @csiphy: CSIPHY device 355 * @cfg: V4L2 subdev pad configuration 356 * @pad: pad on which format is requested 357 * @fmt: pointer to v4l2 format structure 358 * @which: wanted subdev format 359 */ 360 static void csiphy_try_format(struct csiphy_device *csiphy, 361 struct v4l2_subdev_state *sd_state, 362 unsigned int pad, 363 struct v4l2_mbus_framefmt *fmt, 364 enum v4l2_subdev_format_whence which) 365 { 366 unsigned int i; 367 368 switch (pad) { 369 case MSM_CSIPHY_PAD_SINK: 370 /* Set format on sink pad */ 371 372 for (i = 0; i < csiphy->nformats; i++) 373 if (fmt->code == csiphy->formats[i].code) 374 break; 375 376 /* If not found, use UYVY as default */ 377 if (i >= csiphy->nformats) 378 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 379 380 fmt->width = clamp_t(u32, fmt->width, 1, 8191); 381 fmt->height = clamp_t(u32, fmt->height, 1, 8191); 382 383 fmt->field = V4L2_FIELD_NONE; 384 fmt->colorspace = V4L2_COLORSPACE_SRGB; 385 386 break; 387 388 case MSM_CSIPHY_PAD_SRC: 389 /* Set and return a format same as sink pad */ 390 391 *fmt = *__csiphy_get_format(csiphy, sd_state, 392 MSM_CSID_PAD_SINK, 393 which); 394 395 break; 396 } 397 } 398 399 /* 400 * csiphy_enum_mbus_code - Handle pixel format enumeration 401 * @sd: CSIPHY V4L2 subdevice 402 * @cfg: V4L2 subdev pad configuration 403 * @code: pointer to v4l2_subdev_mbus_code_enum structure 404 * return -EINVAL or zero on success 405 */ 406 static int csiphy_enum_mbus_code(struct v4l2_subdev *sd, 407 struct v4l2_subdev_state *sd_state, 408 struct v4l2_subdev_mbus_code_enum *code) 409 { 410 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 411 struct v4l2_mbus_framefmt *format; 412 413 if (code->pad == MSM_CSIPHY_PAD_SINK) { 414 if (code->index >= csiphy->nformats) 415 return -EINVAL; 416 417 code->code = csiphy->formats[code->index].code; 418 } else { 419 if (code->index > 0) 420 return -EINVAL; 421 422 format = __csiphy_get_format(csiphy, sd_state, 423 MSM_CSIPHY_PAD_SINK, 424 code->which); 425 426 code->code = format->code; 427 } 428 429 return 0; 430 } 431 432 /* 433 * csiphy_enum_frame_size - Handle frame size enumeration 434 * @sd: CSIPHY V4L2 subdevice 435 * @cfg: V4L2 subdev pad configuration 436 * @fse: pointer to v4l2_subdev_frame_size_enum structure 437 * return -EINVAL or zero on success 438 */ 439 static int csiphy_enum_frame_size(struct v4l2_subdev *sd, 440 struct v4l2_subdev_state *sd_state, 441 struct v4l2_subdev_frame_size_enum *fse) 442 { 443 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 444 struct v4l2_mbus_framefmt format; 445 446 if (fse->index != 0) 447 return -EINVAL; 448 449 format.code = fse->code; 450 format.width = 1; 451 format.height = 1; 452 csiphy_try_format(csiphy, sd_state, fse->pad, &format, fse->which); 453 fse->min_width = format.width; 454 fse->min_height = format.height; 455 456 if (format.code != fse->code) 457 return -EINVAL; 458 459 format.code = fse->code; 460 format.width = -1; 461 format.height = -1; 462 csiphy_try_format(csiphy, sd_state, fse->pad, &format, fse->which); 463 fse->max_width = format.width; 464 fse->max_height = format.height; 465 466 return 0; 467 } 468 469 /* 470 * csiphy_get_format - Handle get format by pads subdev method 471 * @sd: CSIPHY V4L2 subdevice 472 * @cfg: V4L2 subdev pad configuration 473 * @fmt: pointer to v4l2 subdev format structure 474 * 475 * Return -EINVAL or zero on success 476 */ 477 static int csiphy_get_format(struct v4l2_subdev *sd, 478 struct v4l2_subdev_state *sd_state, 479 struct v4l2_subdev_format *fmt) 480 { 481 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 482 struct v4l2_mbus_framefmt *format; 483 484 format = __csiphy_get_format(csiphy, sd_state, fmt->pad, fmt->which); 485 if (format == NULL) 486 return -EINVAL; 487 488 fmt->format = *format; 489 490 return 0; 491 } 492 493 /* 494 * csiphy_set_format - Handle set format by pads subdev method 495 * @sd: CSIPHY V4L2 subdevice 496 * @cfg: V4L2 subdev pad configuration 497 * @fmt: pointer to v4l2 subdev format structure 498 * 499 * Return -EINVAL or zero on success 500 */ 501 static int csiphy_set_format(struct v4l2_subdev *sd, 502 struct v4l2_subdev_state *sd_state, 503 struct v4l2_subdev_format *fmt) 504 { 505 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 506 struct v4l2_mbus_framefmt *format; 507 508 format = __csiphy_get_format(csiphy, sd_state, fmt->pad, fmt->which); 509 if (format == NULL) 510 return -EINVAL; 511 512 csiphy_try_format(csiphy, sd_state, fmt->pad, &fmt->format, 513 fmt->which); 514 *format = fmt->format; 515 516 /* Propagate the format from sink to source */ 517 if (fmt->pad == MSM_CSIPHY_PAD_SINK) { 518 format = __csiphy_get_format(csiphy, sd_state, 519 MSM_CSIPHY_PAD_SRC, 520 fmt->which); 521 522 *format = fmt->format; 523 csiphy_try_format(csiphy, sd_state, MSM_CSIPHY_PAD_SRC, 524 format, 525 fmt->which); 526 } 527 528 return 0; 529 } 530 531 /* 532 * csiphy_init_formats - Initialize formats on all pads 533 * @sd: CSIPHY V4L2 subdevice 534 * @fh: V4L2 subdev file handle 535 * 536 * Initialize all pad formats with default values. 537 * 538 * Return 0 on success or a negative error code otherwise 539 */ 540 static int csiphy_init_formats(struct v4l2_subdev *sd, 541 struct v4l2_subdev_fh *fh) 542 { 543 struct v4l2_subdev_format format = { 544 .pad = MSM_CSIPHY_PAD_SINK, 545 .which = fh ? V4L2_SUBDEV_FORMAT_TRY : 546 V4L2_SUBDEV_FORMAT_ACTIVE, 547 .format = { 548 .code = MEDIA_BUS_FMT_UYVY8_2X8, 549 .width = 1920, 550 .height = 1080 551 } 552 }; 553 554 return csiphy_set_format(sd, fh ? fh->state : NULL, &format); 555 } 556 557 /* 558 * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources 559 * @csiphy: CSIPHY device 560 * @res: CSIPHY module resources table 561 * @id: CSIPHY module id 562 * 563 * Return 0 on success or a negative error code otherwise 564 */ 565 int msm_csiphy_subdev_init(struct camss *camss, 566 struct csiphy_device *csiphy, 567 const struct resources *res, u8 id) 568 { 569 struct device *dev = camss->dev; 570 struct platform_device *pdev = to_platform_device(dev); 571 struct resource *r; 572 int i, j; 573 int ret; 574 575 csiphy->camss = camss; 576 csiphy->id = id; 577 csiphy->cfg.combo_mode = 0; 578 579 if (camss->version == CAMSS_8x16) { 580 csiphy->ops = &csiphy_ops_2ph_1_0; 581 csiphy->formats = csiphy_formats_8x16; 582 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x16); 583 } else if (camss->version == CAMSS_8x96 || 584 camss->version == CAMSS_660) { 585 csiphy->ops = &csiphy_ops_3ph_1_0; 586 csiphy->formats = csiphy_formats_8x96; 587 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96); 588 } else if (camss->version == CAMSS_845) { 589 csiphy->ops = &csiphy_ops_3ph_1_0; 590 csiphy->formats = csiphy_formats_sdm845; 591 csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845); 592 } else { 593 return -EINVAL; 594 } 595 596 /* Memory */ 597 598 csiphy->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]); 599 if (IS_ERR(csiphy->base)) 600 return PTR_ERR(csiphy->base); 601 602 if (camss->version == CAMSS_8x16 || 603 camss->version == CAMSS_8x96) { 604 csiphy->base_clk_mux = 605 devm_platform_ioremap_resource_byname(pdev, res->reg[1]); 606 if (IS_ERR(csiphy->base_clk_mux)) 607 return PTR_ERR(csiphy->base_clk_mux); 608 } else { 609 csiphy->base_clk_mux = NULL; 610 } 611 612 /* Interrupt */ 613 614 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 615 res->interrupt[0]); 616 if (!r) { 617 dev_err(dev, "missing IRQ\n"); 618 return -EINVAL; 619 } 620 621 csiphy->irq = r->start; 622 snprintf(csiphy->irq_name, sizeof(csiphy->irq_name), "%s_%s%d", 623 dev_name(dev), MSM_CSIPHY_NAME, csiphy->id); 624 625 ret = devm_request_irq(dev, csiphy->irq, csiphy->ops->isr, 626 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, 627 csiphy->irq_name, csiphy); 628 if (ret < 0) { 629 dev_err(dev, "request_irq failed: %d\n", ret); 630 return ret; 631 } 632 633 /* Clocks */ 634 635 csiphy->nclocks = 0; 636 while (res->clock[csiphy->nclocks]) 637 csiphy->nclocks++; 638 639 csiphy->clock = devm_kcalloc(dev, 640 csiphy->nclocks, sizeof(*csiphy->clock), 641 GFP_KERNEL); 642 if (!csiphy->clock) 643 return -ENOMEM; 644 645 csiphy->rate_set = devm_kcalloc(dev, 646 csiphy->nclocks, 647 sizeof(*csiphy->rate_set), 648 GFP_KERNEL); 649 if (!csiphy->rate_set) 650 return -ENOMEM; 651 652 for (i = 0; i < csiphy->nclocks; i++) { 653 struct camss_clock *clock = &csiphy->clock[i]; 654 655 clock->clk = devm_clk_get(dev, res->clock[i]); 656 if (IS_ERR(clock->clk)) 657 return PTR_ERR(clock->clk); 658 659 clock->name = res->clock[i]; 660 661 clock->nfreqs = 0; 662 while (res->clock_rate[i][clock->nfreqs]) 663 clock->nfreqs++; 664 665 if (!clock->nfreqs) { 666 clock->freq = NULL; 667 continue; 668 } 669 670 clock->freq = devm_kcalloc(dev, 671 clock->nfreqs, 672 sizeof(*clock->freq), 673 GFP_KERNEL); 674 if (!clock->freq) 675 return -ENOMEM; 676 677 for (j = 0; j < clock->nfreqs; j++) 678 clock->freq[j] = res->clock_rate[i][j]; 679 680 if (!strcmp(clock->name, "csiphy0_timer") || 681 !strcmp(clock->name, "csiphy1_timer") || 682 !strcmp(clock->name, "csiphy2_timer")) 683 csiphy->rate_set[i] = true; 684 685 if (camss->version == CAMSS_660 && 686 (!strcmp(clock->name, "csi0_phy") || 687 !strcmp(clock->name, "csi1_phy") || 688 !strcmp(clock->name, "csi2_phy"))) 689 csiphy->rate_set[i] = true; 690 } 691 692 return 0; 693 } 694 695 /* 696 * csiphy_link_setup - Setup CSIPHY connections 697 * @entity: Pointer to media entity structure 698 * @local: Pointer to local pad 699 * @remote: Pointer to remote pad 700 * @flags: Link flags 701 * 702 * Rreturn 0 on success 703 */ 704 static int csiphy_link_setup(struct media_entity *entity, 705 const struct media_pad *local, 706 const struct media_pad *remote, u32 flags) 707 { 708 if ((local->flags & MEDIA_PAD_FL_SOURCE) && 709 (flags & MEDIA_LNK_FL_ENABLED)) { 710 struct v4l2_subdev *sd; 711 struct csiphy_device *csiphy; 712 struct csid_device *csid; 713 714 if (media_entity_remote_pad(local)) 715 return -EBUSY; 716 717 sd = media_entity_to_v4l2_subdev(entity); 718 csiphy = v4l2_get_subdevdata(sd); 719 720 sd = media_entity_to_v4l2_subdev(remote->entity); 721 csid = v4l2_get_subdevdata(sd); 722 723 csiphy->cfg.csid_id = csid->id; 724 } 725 726 return 0; 727 } 728 729 static const struct v4l2_subdev_core_ops csiphy_core_ops = { 730 .s_power = csiphy_set_power, 731 }; 732 733 static const struct v4l2_subdev_video_ops csiphy_video_ops = { 734 .s_stream = csiphy_set_stream, 735 }; 736 737 static const struct v4l2_subdev_pad_ops csiphy_pad_ops = { 738 .enum_mbus_code = csiphy_enum_mbus_code, 739 .enum_frame_size = csiphy_enum_frame_size, 740 .get_fmt = csiphy_get_format, 741 .set_fmt = csiphy_set_format, 742 }; 743 744 static const struct v4l2_subdev_ops csiphy_v4l2_ops = { 745 .core = &csiphy_core_ops, 746 .video = &csiphy_video_ops, 747 .pad = &csiphy_pad_ops, 748 }; 749 750 static const struct v4l2_subdev_internal_ops csiphy_v4l2_internal_ops = { 751 .open = csiphy_init_formats, 752 }; 753 754 static const struct media_entity_operations csiphy_media_ops = { 755 .link_setup = csiphy_link_setup, 756 .link_validate = v4l2_subdev_link_validate, 757 }; 758 759 /* 760 * msm_csiphy_register_entity - Register subdev node for CSIPHY module 761 * @csiphy: CSIPHY device 762 * @v4l2_dev: V4L2 device 763 * 764 * Return 0 on success or a negative error code otherwise 765 */ 766 int msm_csiphy_register_entity(struct csiphy_device *csiphy, 767 struct v4l2_device *v4l2_dev) 768 { 769 struct v4l2_subdev *sd = &csiphy->subdev; 770 struct media_pad *pads = csiphy->pads; 771 struct device *dev = csiphy->camss->dev; 772 int ret; 773 774 v4l2_subdev_init(sd, &csiphy_v4l2_ops); 775 sd->internal_ops = &csiphy_v4l2_internal_ops; 776 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 777 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", 778 MSM_CSIPHY_NAME, csiphy->id); 779 v4l2_set_subdevdata(sd, csiphy); 780 781 ret = csiphy_init_formats(sd, NULL); 782 if (ret < 0) { 783 dev_err(dev, "Failed to init format: %d\n", ret); 784 return ret; 785 } 786 787 pads[MSM_CSIPHY_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 788 pads[MSM_CSIPHY_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 789 790 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 791 sd->entity.ops = &csiphy_media_ops; 792 ret = media_entity_pads_init(&sd->entity, MSM_CSIPHY_PADS_NUM, pads); 793 if (ret < 0) { 794 dev_err(dev, "Failed to init media entity: %d\n", ret); 795 return ret; 796 } 797 798 ret = v4l2_device_register_subdev(v4l2_dev, sd); 799 if (ret < 0) { 800 dev_err(dev, "Failed to register subdev: %d\n", ret); 801 media_entity_cleanup(&sd->entity); 802 } 803 804 return ret; 805 } 806 807 /* 808 * msm_csiphy_unregister_entity - Unregister CSIPHY module subdev node 809 * @csiphy: CSIPHY device 810 */ 811 void msm_csiphy_unregister_entity(struct csiphy_device *csiphy) 812 { 813 v4l2_device_unregister_subdev(&csiphy->subdev); 814 media_entity_cleanup(&csiphy->subdev.entity); 815 } 816