1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csid-4-7.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module 6 * 7 * Copyright (C) 2020 Linaro Ltd. 8 */ 9 #include <linux/completion.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 15 #include "camss-csid.h" 16 #include "camss-csid-gen1.h" 17 #include "camss.h" 18 19 #define CAMSS_CSID_CORE_CTRL_0 0x004 20 #define CAMSS_CSID_CORE_CTRL_1 0x008 21 #define CAMSS_CSID_RST_CMD 0x010 22 #define CAMSS_CSID_CID_LUT_VC_n(n) (0x014 + 0x4 * (n)) 23 #define CAMSS_CSID_CID_n_CFG(n) (0x024 + 0x4 * (n)) 24 #define CAMSS_CSID_CID_n_CFG_ISPIF_EN BIT(0) 25 #define CAMSS_CSID_CID_n_CFG_RDI_EN BIT(1) 26 #define CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT 4 27 #define CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_8 (PLAIN_FORMAT_PLAIN8 << 8) 28 #define CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_16 (PLAIN_FORMAT_PLAIN16 << 8) 29 #define CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_LSB (0 << 9) 30 #define CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_MSB (1 << 9) 31 #define CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP (0 << 10) 32 #define CAMSS_CSID_CID_n_CFG_RDI_MODE_PLAIN_PACKING (1 << 10) 33 #define CAMSS_CSID_IRQ_CLEAR_CMD 0x064 34 #define CAMSS_CSID_IRQ_MASK 0x068 35 #define CAMSS_CSID_IRQ_STATUS 0x06c 36 #define CAMSS_CSID_TG_CTRL 0x0a8 37 #define CAMSS_CSID_TG_CTRL_DISABLE 0xa06436 38 #define CAMSS_CSID_TG_CTRL_ENABLE 0xa06437 39 #define CAMSS_CSID_TG_VC_CFG 0x0ac 40 #define CAMSS_CSID_TG_VC_CFG_H_BLANKING 0x3ff 41 #define CAMSS_CSID_TG_VC_CFG_V_BLANKING 0x7f 42 #define CAMSS_CSID_TG_DT_n_CGG_0(n) (0x0b4 + 0xc * (n)) 43 #define CAMSS_CSID_TG_DT_n_CGG_1(n) (0x0b8 + 0xc * (n)) 44 #define CAMSS_CSID_TG_DT_n_CGG_2(n) (0x0bc + 0xc * (n)) 45 46 static void csid_configure_stream(struct csid_device *csid, u8 enable) 47 { 48 struct csid_testgen_config *tg = &csid->testgen; 49 u32 sink_code = csid->fmt[MSM_CSID_PAD_SINK].code; 50 u32 src_code = csid->fmt[MSM_CSID_PAD_SRC].code; 51 u32 val; 52 53 if (enable) { 54 struct v4l2_mbus_framefmt *input_format; 55 const struct csid_format_info *format; 56 u8 vc = 0; /* Virtual Channel 0 */ 57 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */ 58 u8 dt_shift; 59 60 if (tg->enabled) { 61 /* Config Test Generator */ 62 u32 num_bytes_per_line, num_lines; 63 64 input_format = &csid->fmt[MSM_CSID_PAD_SRC]; 65 format = csid_get_fmt_entry(csid->res->formats->formats, 66 csid->res->formats->nformats, 67 input_format->code); 68 num_bytes_per_line = input_format->width * format->bpp * format->spp / 8; 69 num_lines = input_format->height; 70 71 /* 31:24 V blank, 23:13 H blank, 3:2 num of active DT */ 72 /* 1:0 VC */ 73 val = ((CAMSS_CSID_TG_VC_CFG_V_BLANKING & 0xff) << 24) | 74 ((CAMSS_CSID_TG_VC_CFG_H_BLANKING & 0x7ff) << 13); 75 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); 76 77 /* 28:16 bytes per lines, 12:0 num of lines */ 78 val = ((num_bytes_per_line & 0x1fff) << 16) | 79 (num_lines & 0x1fff); 80 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); 81 82 /* 5:0 data type */ 83 val = format->data_type; 84 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); 85 86 /* 2:0 output test pattern */ 87 val = tg->mode - 1; 88 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); 89 } else { 90 struct csid_phy_config *phy = &csid->phy; 91 92 input_format = &csid->fmt[MSM_CSID_PAD_SINK]; 93 format = csid_get_fmt_entry(csid->res->formats->formats, 94 csid->res->formats->nformats, 95 input_format->code); 96 97 val = phy->lane_cnt - 1; 98 val |= phy->lane_assign << 4; 99 100 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0); 101 102 val = phy->csiphy_id << 17; 103 val |= 0x9; 104 105 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1); 106 } 107 108 /* Config LUT */ 109 110 dt_shift = (cid % 4) * 8; 111 112 val = readl_relaxed(csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); 113 val &= ~(0xff << dt_shift); 114 val |= format->data_type << dt_shift; 115 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); 116 117 val = CAMSS_CSID_CID_n_CFG_ISPIF_EN; 118 val |= CAMSS_CSID_CID_n_CFG_RDI_EN; 119 val |= format->decode_format << CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT; 120 val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP; 121 122 if ((sink_code == MEDIA_BUS_FMT_SBGGR10_1X10 && 123 src_code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) || 124 (sink_code == MEDIA_BUS_FMT_Y10_1X10 && 125 src_code == MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)) { 126 val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_PLAIN_PACKING; 127 val |= CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_16; 128 val |= CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_LSB; 129 } 130 131 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); 132 133 if (tg->enabled) { 134 val = CAMSS_CSID_TG_CTRL_ENABLE; 135 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); 136 } 137 } else { 138 if (tg->enabled) { 139 val = CAMSS_CSID_TG_CTRL_DISABLE; 140 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); 141 } 142 } 143 } 144 145 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) 146 { 147 if (val > 0 && val <= csid->testgen.nmodes) 148 csid->testgen.mode = val; 149 150 return 0; 151 } 152 153 /* 154 * isr - CSID module interrupt service routine 155 * @irq: Interrupt line 156 * @dev: CSID device 157 * 158 * Return IRQ_HANDLED on success 159 */ 160 static irqreturn_t csid_isr(int irq, void *dev) 161 { 162 struct csid_device *csid = dev; 163 u32 value; 164 165 value = readl_relaxed(csid->base + CAMSS_CSID_IRQ_STATUS); 166 writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD); 167 168 if ((value >> 11) & 0x1) 169 complete(&csid->reset_complete); 170 171 return IRQ_HANDLED; 172 } 173 174 /* 175 * csid_reset - Trigger reset on CSID module and wait to complete 176 * @csid: CSID device 177 * 178 * Return 0 on success or a negative error code otherwise 179 */ 180 static int csid_reset(struct csid_device *csid) 181 { 182 unsigned long time; 183 184 reinit_completion(&csid->reset_complete); 185 186 writel_relaxed(0x7fff, csid->base + CAMSS_CSID_RST_CMD); 187 188 time = wait_for_completion_timeout(&csid->reset_complete, 189 msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); 190 if (!time) { 191 dev_err(csid->camss->dev, "CSID reset timeout\n"); 192 return -EIO; 193 } 194 195 return 0; 196 } 197 198 static void csid_subdev_init(struct csid_device *csid) 199 { 200 csid->testgen.modes = csid_testgen_modes; 201 csid->testgen.nmodes = CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; 202 } 203 204 const struct csid_hw_ops csid_ops_4_7 = { 205 .configure_stream = csid_configure_stream, 206 .configure_testgen_pattern = csid_configure_testgen_pattern, 207 .hw_version = csid_hw_version, 208 .isr = csid_isr, 209 .reset = csid_reset, 210 .src_pad_code = csid_src_pad_code, 211 .subdev_init = csid_subdev_init, 212 }; 213