1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale PXP Register Definitions 4 * 5 * based on pxp_dma_v3.h, Xml Revision: 1.77, Template Revision: 1.3 6 * 7 * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. 8 */ 9 10 #ifndef __IMX_PXP_H__ 11 #define __IMX_PXP_H__ 12 13 #define HW_PXP_CTRL (0x00000000) 14 #define HW_PXP_CTRL_SET (0x00000004) 15 #define HW_PXP_CTRL_CLR (0x00000008) 16 #define HW_PXP_CTRL_TOG (0x0000000c) 17 18 #define BM_PXP_CTRL_SFTRST 0x80000000 19 #define BF_PXP_CTRL_SFTRST(v) \ 20 (((v) << 31) & BM_PXP_CTRL_SFTRST) 21 #define BM_PXP_CTRL_CLKGATE 0x40000000 22 #define BF_PXP_CTRL_CLKGATE(v) \ 23 (((v) << 30) & BM_PXP_CTRL_CLKGATE) 24 #define BM_PXP_CTRL_RSVD4 0x20000000 25 #define BF_PXP_CTRL_RSVD4(v) \ 26 (((v) << 29) & BM_PXP_CTRL_RSVD4) 27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000 28 #define BF_PXP_CTRL_EN_REPEAT(v) \ 29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT) 30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000 31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ 32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1) 33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000 34 #define BF_PXP_CTRL_ENABLE_ROTATE0(v) \ 35 (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0) 36 #define BM_PXP_CTRL_ENABLE_LUT 0x02000000 37 #define BF_PXP_CTRL_ENABLE_LUT(v) \ 38 (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT) 39 #define BM_PXP_CTRL_ENABLE_CSC2 0x01000000 40 #define BF_PXP_CTRL_ENABLE_CSC2(v) \ 41 (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2) 42 #define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 43 #define BF_PXP_CTRL_BLOCK_SIZE(v) \ 44 (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE) 45 #define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 46 #define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 47 #define BM_PXP_CTRL_RSVD1 0x00400000 48 #define BF_PXP_CTRL_RSVD1(v) \ 49 (((v) << 22) & BM_PXP_CTRL_RSVD1) 50 #define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000 51 #define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \ 52 (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B) 53 #define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000 54 #define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \ 55 (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE) 56 #define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000 57 #define BF_PXP_CTRL_ENABLE_WFE_B(v) \ 58 (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B) 59 #define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000 60 #define BF_PXP_CTRL_ENABLE_WFE_A(v) \ 61 (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A) 62 #define BM_PXP_CTRL_ENABLE_DITHER 0x00020000 63 #define BF_PXP_CTRL_ENABLE_DITHER(v) \ 64 (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER) 65 #define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000 66 #define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \ 67 (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT) 68 #define BM_PXP_CTRL_VFLIP1 0x00008000 69 #define BF_PXP_CTRL_VFLIP1(v) \ 70 (((v) << 15) & BM_PXP_CTRL_VFLIP1) 71 #define BM_PXP_CTRL_HFLIP1 0x00004000 72 #define BF_PXP_CTRL_HFLIP1(v) \ 73 (((v) << 14) & BM_PXP_CTRL_HFLIP1) 74 #define BP_PXP_CTRL_ROTATE1 12 75 #define BM_PXP_CTRL_ROTATE1 0x00003000 76 #define BF_PXP_CTRL_ROTATE1(v) \ 77 (((v) << 12) & BM_PXP_CTRL_ROTATE1) 78 #define BV_PXP_CTRL_ROTATE1__ROT_0 0x0 79 #define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 80 #define BV_PXP_CTRL_ROTATE1__ROT_180 0x2 81 #define BV_PXP_CTRL_ROTATE1__ROT_270 0x3 82 #define BM_PXP_CTRL_VFLIP0 0x00000800 83 #define BF_PXP_CTRL_VFLIP0(v) \ 84 (((v) << 11) & BM_PXP_CTRL_VFLIP0) 85 #define BM_PXP_CTRL_HFLIP0 0x00000400 86 #define BF_PXP_CTRL_HFLIP0(v) \ 87 (((v) << 10) & BM_PXP_CTRL_HFLIP0) 88 #define BP_PXP_CTRL_ROTATE0 8 89 #define BM_PXP_CTRL_ROTATE0 0x00000300 90 #define BF_PXP_CTRL_ROTATE0(v) \ 91 (((v) << 8) & BM_PXP_CTRL_ROTATE0) 92 #define BV_PXP_CTRL_ROTATE0__ROT_0 0x0 93 #define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 94 #define BV_PXP_CTRL_ROTATE0__ROT_180 0x2 95 #define BV_PXP_CTRL_ROTATE0__ROT_270 0x3 96 #define BP_PXP_CTRL_RSVD0 6 97 #define BM_PXP_CTRL_RSVD0 0x000000C0 98 #define BF_PXP_CTRL_RSVD0(v) \ 99 (((v) << 6) & BM_PXP_CTRL_RSVD0) 100 #define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020 101 #define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \ 102 (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP) 103 #define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010 104 #define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \ 105 (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE) 106 #define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008 107 #define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \ 108 (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE) 109 #define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 110 #define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \ 111 (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE) 112 #define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 113 #define BF_PXP_CTRL_IRQ_ENABLE(v) \ 114 (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE) 115 #define BM_PXP_CTRL_ENABLE 0x00000001 116 #define BF_PXP_CTRL_ENABLE(v) \ 117 (((v) << 0) & BM_PXP_CTRL_ENABLE) 118 119 #define HW_PXP_STAT (0x00000010) 120 #define HW_PXP_STAT_SET (0x00000014) 121 #define HW_PXP_STAT_CLR (0x00000018) 122 #define HW_PXP_STAT_TOG (0x0000001c) 123 124 #define BP_PXP_STAT_BLOCKX 24 125 #define BM_PXP_STAT_BLOCKX 0xFF000000 126 #define BF_PXP_STAT_BLOCKX(v) \ 127 (((v) << 24) & BM_PXP_STAT_BLOCKX) 128 #define BP_PXP_STAT_BLOCKY 16 129 #define BM_PXP_STAT_BLOCKY 0x00FF0000 130 #define BF_PXP_STAT_BLOCKY(v) \ 131 (((v) << 16) & BM_PXP_STAT_BLOCKY) 132 #define BP_PXP_STAT_AXI_ERROR_ID_1 12 133 #define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000 134 #define BF_PXP_STAT_AXI_ERROR_ID_1(v) \ 135 (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1) 136 #define BM_PXP_STAT_RSVD2 0x00000800 137 #define BF_PXP_STAT_RSVD2(v) \ 138 (((v) << 11) & BM_PXP_STAT_RSVD2) 139 #define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400 140 #define BF_PXP_STAT_AXI_READ_ERROR_1(v) \ 141 (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1) 142 #define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200 143 #define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \ 144 (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1) 145 #define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100 146 #define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \ 147 (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ) 148 #define BP_PXP_STAT_AXI_ERROR_ID_0 4 149 #define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0 150 #define BF_PXP_STAT_AXI_ERROR_ID_0(v) \ 151 (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0) 152 #define BM_PXP_STAT_NEXT_IRQ 0x00000008 153 #define BF_PXP_STAT_NEXT_IRQ(v) \ 154 (((v) << 3) & BM_PXP_STAT_NEXT_IRQ) 155 #define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004 156 #define BF_PXP_STAT_AXI_READ_ERROR_0(v) \ 157 (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0) 158 #define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002 159 #define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \ 160 (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0) 161 #define BM_PXP_STAT_IRQ0 0x00000001 162 #define BF_PXP_STAT_IRQ0(v) \ 163 (((v) << 0) & BM_PXP_STAT_IRQ0) 164 165 #define HW_PXP_OUT_CTRL (0x00000020) 166 #define HW_PXP_OUT_CTRL_SET (0x00000024) 167 #define HW_PXP_OUT_CTRL_CLR (0x00000028) 168 #define HW_PXP_OUT_CTRL_TOG (0x0000002c) 169 170 #define BP_PXP_OUT_CTRL_ALPHA 24 171 #define BM_PXP_OUT_CTRL_ALPHA 0xFF000000 172 #define BF_PXP_OUT_CTRL_ALPHA(v) \ 173 (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA) 174 #define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000 175 #define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \ 176 (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT) 177 #define BP_PXP_OUT_CTRL_RSVD1 10 178 #define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00 179 #define BF_PXP_OUT_CTRL_RSVD1(v) \ 180 (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1) 181 #define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8 182 #define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300 183 #define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \ 184 (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT) 185 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 186 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 187 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 188 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 189 #define BP_PXP_OUT_CTRL_RSVD0 5 190 #define BM_PXP_OUT_CTRL_RSVD0 0x000000E0 191 #define BF_PXP_OUT_CTRL_RSVD0(v) \ 192 (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0) 193 #define BP_PXP_OUT_CTRL_FORMAT 0 194 #define BM_PXP_OUT_CTRL_FORMAT 0x0000001F 195 #define BF_PXP_OUT_CTRL_FORMAT(v) \ 196 (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) 197 #define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0 198 #define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 199 #define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5 200 #define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8 201 #define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9 202 #define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC 203 #define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD 204 #define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE 205 #define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 206 #define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 207 #define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 208 #define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14 209 #define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15 210 #define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18 211 #define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19 212 #define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A 213 #define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B 214 215 #define HW_PXP_OUT_BUF (0x00000030) 216 217 #define BP_PXP_OUT_BUF_ADDR 0 218 #define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF 219 #define BF_PXP_OUT_BUF_ADDR(v) (v) 220 221 #define HW_PXP_OUT_BUF2 (0x00000040) 222 223 #define BP_PXP_OUT_BUF2_ADDR 0 224 #define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF 225 #define BF_PXP_OUT_BUF2_ADDR(v) (v) 226 227 #define HW_PXP_OUT_PITCH (0x00000050) 228 229 #define BP_PXP_OUT_PITCH_RSVD 16 230 #define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000 231 #define BF_PXP_OUT_PITCH_RSVD(v) \ 232 (((v) << 16) & BM_PXP_OUT_PITCH_RSVD) 233 #define BP_PXP_OUT_PITCH_PITCH 0 234 #define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF 235 #define BF_PXP_OUT_PITCH_PITCH(v) \ 236 (((v) << 0) & BM_PXP_OUT_PITCH_PITCH) 237 238 #define HW_PXP_OUT_LRC (0x00000060) 239 240 #define BP_PXP_OUT_LRC_RSVD1 30 241 #define BM_PXP_OUT_LRC_RSVD1 0xC0000000 242 #define BF_PXP_OUT_LRC_RSVD1(v) \ 243 (((v) << 30) & BM_PXP_OUT_LRC_RSVD1) 244 #define BP_PXP_OUT_LRC_X 16 245 #define BM_PXP_OUT_LRC_X 0x3FFF0000 246 #define BF_PXP_OUT_LRC_X(v) \ 247 (((v) << 16) & BM_PXP_OUT_LRC_X) 248 #define BP_PXP_OUT_LRC_RSVD0 14 249 #define BM_PXP_OUT_LRC_RSVD0 0x0000C000 250 #define BF_PXP_OUT_LRC_RSVD0(v) \ 251 (((v) << 14) & BM_PXP_OUT_LRC_RSVD0) 252 #define BP_PXP_OUT_LRC_Y 0 253 #define BM_PXP_OUT_LRC_Y 0x00003FFF 254 #define BF_PXP_OUT_LRC_Y(v) \ 255 (((v) << 0) & BM_PXP_OUT_LRC_Y) 256 257 #define HW_PXP_OUT_PS_ULC (0x00000070) 258 259 #define BP_PXP_OUT_PS_ULC_RSVD1 30 260 #define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000 261 #define BF_PXP_OUT_PS_ULC_RSVD1(v) \ 262 (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1) 263 #define BP_PXP_OUT_PS_ULC_X 16 264 #define BM_PXP_OUT_PS_ULC_X 0x3FFF0000 265 #define BF_PXP_OUT_PS_ULC_X(v) \ 266 (((v) << 16) & BM_PXP_OUT_PS_ULC_X) 267 #define BP_PXP_OUT_PS_ULC_RSVD0 14 268 #define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000 269 #define BF_PXP_OUT_PS_ULC_RSVD0(v) \ 270 (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0) 271 #define BP_PXP_OUT_PS_ULC_Y 0 272 #define BM_PXP_OUT_PS_ULC_Y 0x00003FFF 273 #define BF_PXP_OUT_PS_ULC_Y(v) \ 274 (((v) << 0) & BM_PXP_OUT_PS_ULC_Y) 275 276 #define HW_PXP_OUT_PS_LRC (0x00000080) 277 278 #define BP_PXP_OUT_PS_LRC_RSVD1 30 279 #define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000 280 #define BF_PXP_OUT_PS_LRC_RSVD1(v) \ 281 (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1) 282 #define BP_PXP_OUT_PS_LRC_X 16 283 #define BM_PXP_OUT_PS_LRC_X 0x3FFF0000 284 #define BF_PXP_OUT_PS_LRC_X(v) \ 285 (((v) << 16) & BM_PXP_OUT_PS_LRC_X) 286 #define BP_PXP_OUT_PS_LRC_RSVD0 14 287 #define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000 288 #define BF_PXP_OUT_PS_LRC_RSVD0(v) \ 289 (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0) 290 #define BP_PXP_OUT_PS_LRC_Y 0 291 #define BM_PXP_OUT_PS_LRC_Y 0x00003FFF 292 #define BF_PXP_OUT_PS_LRC_Y(v) \ 293 (((v) << 0) & BM_PXP_OUT_PS_LRC_Y) 294 295 #define HW_PXP_OUT_AS_ULC (0x00000090) 296 297 #define BP_PXP_OUT_AS_ULC_RSVD1 30 298 #define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000 299 #define BF_PXP_OUT_AS_ULC_RSVD1(v) \ 300 (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1) 301 #define BP_PXP_OUT_AS_ULC_X 16 302 #define BM_PXP_OUT_AS_ULC_X 0x3FFF0000 303 #define BF_PXP_OUT_AS_ULC_X(v) \ 304 (((v) << 16) & BM_PXP_OUT_AS_ULC_X) 305 #define BP_PXP_OUT_AS_ULC_RSVD0 14 306 #define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000 307 #define BF_PXP_OUT_AS_ULC_RSVD0(v) \ 308 (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0) 309 #define BP_PXP_OUT_AS_ULC_Y 0 310 #define BM_PXP_OUT_AS_ULC_Y 0x00003FFF 311 #define BF_PXP_OUT_AS_ULC_Y(v) \ 312 (((v) << 0) & BM_PXP_OUT_AS_ULC_Y) 313 314 #define HW_PXP_OUT_AS_LRC (0x000000a0) 315 316 #define BP_PXP_OUT_AS_LRC_RSVD1 30 317 #define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000 318 #define BF_PXP_OUT_AS_LRC_RSVD1(v) \ 319 (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1) 320 #define BP_PXP_OUT_AS_LRC_X 16 321 #define BM_PXP_OUT_AS_LRC_X 0x3FFF0000 322 #define BF_PXP_OUT_AS_LRC_X(v) \ 323 (((v) << 16) & BM_PXP_OUT_AS_LRC_X) 324 #define BP_PXP_OUT_AS_LRC_RSVD0 14 325 #define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000 326 #define BF_PXP_OUT_AS_LRC_RSVD0(v) \ 327 (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0) 328 #define BP_PXP_OUT_AS_LRC_Y 0 329 #define BM_PXP_OUT_AS_LRC_Y 0x00003FFF 330 #define BF_PXP_OUT_AS_LRC_Y(v) \ 331 (((v) << 0) & BM_PXP_OUT_AS_LRC_Y) 332 333 #define HW_PXP_PS_CTRL (0x000000b0) 334 #define HW_PXP_PS_CTRL_SET (0x000000b4) 335 #define HW_PXP_PS_CTRL_CLR (0x000000b8) 336 #define HW_PXP_PS_CTRL_TOG (0x000000bc) 337 338 #define BP_PXP_PS_CTRL_RSVD1 12 339 #define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000 340 #define BF_PXP_PS_CTRL_RSVD1(v) \ 341 (((v) << 12) & BM_PXP_PS_CTRL_RSVD1) 342 #define BP_PXP_PS_CTRL_DECX 10 343 #define BM_PXP_PS_CTRL_DECX 0x00000C00 344 #define BF_PXP_PS_CTRL_DECX(v) \ 345 (((v) << 10) & BM_PXP_PS_CTRL_DECX) 346 #define BV_PXP_PS_CTRL_DECX__DISABLE 0x0 347 #define BV_PXP_PS_CTRL_DECX__DECX2 0x1 348 #define BV_PXP_PS_CTRL_DECX__DECX4 0x2 349 #define BV_PXP_PS_CTRL_DECX__DECX8 0x3 350 #define BP_PXP_PS_CTRL_DECY 8 351 #define BM_PXP_PS_CTRL_DECY 0x00000300 352 #define BF_PXP_PS_CTRL_DECY(v) \ 353 (((v) << 8) & BM_PXP_PS_CTRL_DECY) 354 #define BV_PXP_PS_CTRL_DECY__DISABLE 0x0 355 #define BV_PXP_PS_CTRL_DECY__DECY2 0x1 356 #define BV_PXP_PS_CTRL_DECY__DECY4 0x2 357 #define BV_PXP_PS_CTRL_DECY__DECY8 0x3 358 #define BM_PXP_PS_CTRL_RSVD0 0x00000080 359 #define BF_PXP_PS_CTRL_RSVD0(v) \ 360 (((v) << 7) & BM_PXP_PS_CTRL_RSVD0) 361 #define BM_PXP_PS_CTRL_WB_SWAP 0x00000040 362 #define BF_PXP_PS_CTRL_WB_SWAP(v) \ 363 (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP) 364 #define BP_PXP_PS_CTRL_FORMAT 0 365 #define BM_PXP_PS_CTRL_FORMAT 0x0000003F 366 #define BF_PXP_PS_CTRL_FORMAT(v) \ 367 (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) 368 #define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 369 #define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC 370 #define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD 371 #define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE 372 #define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 373 #define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 374 #define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 375 #define BV_PXP_PS_CTRL_FORMAT__Y8 0x14 376 #define BV_PXP_PS_CTRL_FORMAT__Y4 0x15 377 #define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18 378 #define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19 379 #define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A 380 #define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B 381 #define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E 382 #define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F 383 384 #define HW_PXP_PS_BUF (0x000000c0) 385 386 #define BP_PXP_PS_BUF_ADDR 0 387 #define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF 388 #define BF_PXP_PS_BUF_ADDR(v) (v) 389 390 #define HW_PXP_PS_UBUF (0x000000d0) 391 392 #define BP_PXP_PS_UBUF_ADDR 0 393 #define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF 394 #define BF_PXP_PS_UBUF_ADDR(v) (v) 395 396 #define HW_PXP_PS_VBUF (0x000000e0) 397 398 #define BP_PXP_PS_VBUF_ADDR 0 399 #define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF 400 #define BF_PXP_PS_VBUF_ADDR(v) (v) 401 402 #define HW_PXP_PS_PITCH (0x000000f0) 403 404 #define BP_PXP_PS_PITCH_RSVD 16 405 #define BM_PXP_PS_PITCH_RSVD 0xFFFF0000 406 #define BF_PXP_PS_PITCH_RSVD(v) \ 407 (((v) << 16) & BM_PXP_PS_PITCH_RSVD) 408 #define BP_PXP_PS_PITCH_PITCH 0 409 #define BM_PXP_PS_PITCH_PITCH 0x0000FFFF 410 #define BF_PXP_PS_PITCH_PITCH(v) \ 411 (((v) << 0) & BM_PXP_PS_PITCH_PITCH) 412 413 #define HW_PXP_PS_BACKGROUND_0 (0x00000100) 414 415 #define BP_PXP_PS_BACKGROUND_0_RSVD 24 416 #define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000 417 #define BF_PXP_PS_BACKGROUND_0_RSVD(v) \ 418 (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD) 419 #define BP_PXP_PS_BACKGROUND_0_COLOR 0 420 #define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF 421 #define BF_PXP_PS_BACKGROUND_0_COLOR(v) \ 422 (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR) 423 424 #define HW_PXP_PS_SCALE (0x00000110) 425 426 #define BM_PXP_PS_SCALE_RSVD2 0x80000000 427 #define BF_PXP_PS_SCALE_RSVD2(v) \ 428 (((v) << 31) & BM_PXP_PS_SCALE_RSVD2) 429 #define BP_PXP_PS_SCALE_YSCALE 16 430 #define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 431 #define BF_PXP_PS_SCALE_YSCALE(v) \ 432 (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) 433 #define BM_PXP_PS_SCALE_RSVD1 0x00008000 434 #define BF_PXP_PS_SCALE_RSVD1(v) \ 435 (((v) << 15) & BM_PXP_PS_SCALE_RSVD1) 436 #define BP_PXP_PS_SCALE_XSCALE 0 437 #define BM_PXP_PS_SCALE_XSCALE 0x00007FFF 438 #define BF_PXP_PS_SCALE_XSCALE(v) \ 439 (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) 440 441 #define HW_PXP_PS_OFFSET (0x00000120) 442 443 #define BP_PXP_PS_OFFSET_RSVD2 28 444 #define BM_PXP_PS_OFFSET_RSVD2 0xF0000000 445 #define BF_PXP_PS_OFFSET_RSVD2(v) \ 446 (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2) 447 #define BP_PXP_PS_OFFSET_YOFFSET 16 448 #define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000 449 #define BF_PXP_PS_OFFSET_YOFFSET(v) \ 450 (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET) 451 #define BP_PXP_PS_OFFSET_RSVD1 12 452 #define BM_PXP_PS_OFFSET_RSVD1 0x0000F000 453 #define BF_PXP_PS_OFFSET_RSVD1(v) \ 454 (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1) 455 #define BP_PXP_PS_OFFSET_XOFFSET 0 456 #define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF 457 #define BF_PXP_PS_OFFSET_XOFFSET(v) \ 458 (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET) 459 460 #define HW_PXP_PS_CLRKEYLOW_0 (0x00000130) 461 462 #define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24 463 #define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000 464 #define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \ 465 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1) 466 #define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0 467 #define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF 468 #define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \ 469 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL) 470 471 #define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140) 472 473 #define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24 474 #define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000 475 #define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \ 476 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1) 477 #define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0 478 #define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF 479 #define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \ 480 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL) 481 482 #define HW_PXP_AS_CTRL (0x00000150) 483 484 #define BP_PXP_AS_CTRL_RSVD1 22 485 #define BM_PXP_AS_CTRL_RSVD1 0xFFC00000 486 #define BF_PXP_AS_CTRL_RSVD1(v) \ 487 (((v) << 22) & BM_PXP_AS_CTRL_RSVD1) 488 #define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000 489 #define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \ 490 (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT) 491 #define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000 492 #define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \ 493 (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT) 494 #define BP_PXP_AS_CTRL_ROP 16 495 #define BM_PXP_AS_CTRL_ROP 0x000F0000 496 #define BF_PXP_AS_CTRL_ROP(v) \ 497 (((v) << 16) & BM_PXP_AS_CTRL_ROP) 498 #define BV_PXP_AS_CTRL_ROP__MASKAS 0x0 499 #define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 500 #define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2 501 #define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3 502 #define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4 503 #define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5 504 #define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6 505 #define BV_PXP_AS_CTRL_ROP__NOT 0x7 506 #define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8 507 #define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9 508 #define BV_PXP_AS_CTRL_ROP__XORAS 0xA 509 #define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB 510 #define BP_PXP_AS_CTRL_ALPHA 8 511 #define BM_PXP_AS_CTRL_ALPHA 0x0000FF00 512 #define BF_PXP_AS_CTRL_ALPHA(v) \ 513 (((v) << 8) & BM_PXP_AS_CTRL_ALPHA) 514 #define BP_PXP_AS_CTRL_FORMAT 4 515 #define BM_PXP_AS_CTRL_FORMAT 0x000000F0 516 #define BF_PXP_AS_CTRL_FORMAT(v) \ 517 (((v) << 4) & BM_PXP_AS_CTRL_FORMAT) 518 #define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0 519 #define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 520 #define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4 521 #define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8 522 #define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9 523 #define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC 524 #define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD 525 #define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE 526 #define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008 527 #define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \ 528 (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY) 529 #define BP_PXP_AS_CTRL_ALPHA_CTRL 1 530 #define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006 531 #define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \ 532 (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL) 533 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0 534 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 535 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2 536 #define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3 537 #define BM_PXP_AS_CTRL_RSVD0 0x00000001 538 #define BF_PXP_AS_CTRL_RSVD0(v) \ 539 (((v) << 0) & BM_PXP_AS_CTRL_RSVD0) 540 541 #define HW_PXP_AS_BUF (0x00000160) 542 543 #define BP_PXP_AS_BUF_ADDR 0 544 #define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF 545 #define BF_PXP_AS_BUF_ADDR(v) (v) 546 547 #define HW_PXP_AS_PITCH (0x00000170) 548 549 #define BP_PXP_AS_PITCH_RSVD 16 550 #define BM_PXP_AS_PITCH_RSVD 0xFFFF0000 551 #define BF_PXP_AS_PITCH_RSVD(v) \ 552 (((v) << 16) & BM_PXP_AS_PITCH_RSVD) 553 #define BP_PXP_AS_PITCH_PITCH 0 554 #define BM_PXP_AS_PITCH_PITCH 0x0000FFFF 555 #define BF_PXP_AS_PITCH_PITCH(v) \ 556 (((v) << 0) & BM_PXP_AS_PITCH_PITCH) 557 558 #define HW_PXP_AS_CLRKEYLOW_0 (0x00000180) 559 560 #define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24 561 #define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000 562 #define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \ 563 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1) 564 #define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0 565 #define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF 566 #define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \ 567 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL) 568 569 #define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190) 570 571 #define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24 572 #define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000 573 #define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \ 574 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1) 575 #define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0 576 #define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF 577 #define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \ 578 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL) 579 580 #define HW_PXP_CSC1_COEF0 (0x000001a0) 581 582 #define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000 583 #define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \ 584 (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE) 585 #define BM_PXP_CSC1_COEF0_BYPASS 0x40000000 586 #define BF_PXP_CSC1_COEF0_BYPASS(v) \ 587 (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS) 588 #define BM_PXP_CSC1_COEF0_RSVD1 0x20000000 589 #define BF_PXP_CSC1_COEF0_RSVD1(v) \ 590 (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1) 591 #define BP_PXP_CSC1_COEF0_C0 18 592 #define BM_PXP_CSC1_COEF0_C0 0x1FFC0000 593 #define BF_PXP_CSC1_COEF0_C0(v) \ 594 (((v) << 18) & BM_PXP_CSC1_COEF0_C0) 595 #define BP_PXP_CSC1_COEF0_UV_OFFSET 9 596 #define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00 597 #define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \ 598 (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET) 599 #define BP_PXP_CSC1_COEF0_Y_OFFSET 0 600 #define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF 601 #define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \ 602 (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET) 603 604 #define HW_PXP_CSC1_COEF1 (0x000001b0) 605 606 #define BP_PXP_CSC1_COEF1_RSVD1 27 607 #define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000 608 #define BF_PXP_CSC1_COEF1_RSVD1(v) \ 609 (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1) 610 #define BP_PXP_CSC1_COEF1_C1 16 611 #define BM_PXP_CSC1_COEF1_C1 0x07FF0000 612 #define BF_PXP_CSC1_COEF1_C1(v) \ 613 (((v) << 16) & BM_PXP_CSC1_COEF1_C1) 614 #define BP_PXP_CSC1_COEF1_RSVD0 11 615 #define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800 616 #define BF_PXP_CSC1_COEF1_RSVD0(v) \ 617 (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0) 618 #define BP_PXP_CSC1_COEF1_C4 0 619 #define BM_PXP_CSC1_COEF1_C4 0x000007FF 620 #define BF_PXP_CSC1_COEF1_C4(v) \ 621 (((v) << 0) & BM_PXP_CSC1_COEF1_C4) 622 623 #define HW_PXP_CSC1_COEF2 (0x000001c0) 624 625 #define BP_PXP_CSC1_COEF2_RSVD1 27 626 #define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000 627 #define BF_PXP_CSC1_COEF2_RSVD1(v) \ 628 (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1) 629 #define BP_PXP_CSC1_COEF2_C2 16 630 #define BM_PXP_CSC1_COEF2_C2 0x07FF0000 631 #define BF_PXP_CSC1_COEF2_C2(v) \ 632 (((v) << 16) & BM_PXP_CSC1_COEF2_C2) 633 #define BP_PXP_CSC1_COEF2_RSVD0 11 634 #define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800 635 #define BF_PXP_CSC1_COEF2_RSVD0(v) \ 636 (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0) 637 #define BP_PXP_CSC1_COEF2_C3 0 638 #define BM_PXP_CSC1_COEF2_C3 0x000007FF 639 #define BF_PXP_CSC1_COEF2_C3(v) \ 640 (((v) << 0) & BM_PXP_CSC1_COEF2_C3) 641 642 #define HW_PXP_CSC2_CTRL (0x000001d0) 643 644 #define BP_PXP_CSC2_CTRL_RSVD 3 645 #define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8 646 #define BF_PXP_CSC2_CTRL_RSVD(v) \ 647 (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD) 648 #define BP_PXP_CSC2_CTRL_CSC_MODE 1 649 #define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006 650 #define BF_PXP_CSC2_CTRL_CSC_MODE(v) \ 651 (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE) 652 #define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0 653 #define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 654 #define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2 655 #define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3 656 #define BM_PXP_CSC2_CTRL_BYPASS 0x00000001 657 #define BF_PXP_CSC2_CTRL_BYPASS(v) \ 658 (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS) 659 660 #define HW_PXP_CSC2_COEF0 (0x000001e0) 661 662 #define BP_PXP_CSC2_COEF0_RSVD1 27 663 #define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000 664 #define BF_PXP_CSC2_COEF0_RSVD1(v) \ 665 (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1) 666 #define BP_PXP_CSC2_COEF0_A2 16 667 #define BM_PXP_CSC2_COEF0_A2 0x07FF0000 668 #define BF_PXP_CSC2_COEF0_A2(v) \ 669 (((v) << 16) & BM_PXP_CSC2_COEF0_A2) 670 #define BP_PXP_CSC2_COEF0_RSVD0 11 671 #define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800 672 #define BF_PXP_CSC2_COEF0_RSVD0(v) \ 673 (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0) 674 #define BP_PXP_CSC2_COEF0_A1 0 675 #define BM_PXP_CSC2_COEF0_A1 0x000007FF 676 #define BF_PXP_CSC2_COEF0_A1(v) \ 677 (((v) << 0) & BM_PXP_CSC2_COEF0_A1) 678 679 #define HW_PXP_CSC2_COEF1 (0x000001f0) 680 681 #define BP_PXP_CSC2_COEF1_RSVD1 27 682 #define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000 683 #define BF_PXP_CSC2_COEF1_RSVD1(v) \ 684 (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1) 685 #define BP_PXP_CSC2_COEF1_B1 16 686 #define BM_PXP_CSC2_COEF1_B1 0x07FF0000 687 #define BF_PXP_CSC2_COEF1_B1(v) \ 688 (((v) << 16) & BM_PXP_CSC2_COEF1_B1) 689 #define BP_PXP_CSC2_COEF1_RSVD0 11 690 #define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800 691 #define BF_PXP_CSC2_COEF1_RSVD0(v) \ 692 (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0) 693 #define BP_PXP_CSC2_COEF1_A3 0 694 #define BM_PXP_CSC2_COEF1_A3 0x000007FF 695 #define BF_PXP_CSC2_COEF1_A3(v) \ 696 (((v) << 0) & BM_PXP_CSC2_COEF1_A3) 697 698 #define HW_PXP_CSC2_COEF2 (0x00000200) 699 700 #define BP_PXP_CSC2_COEF2_RSVD1 27 701 #define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000 702 #define BF_PXP_CSC2_COEF2_RSVD1(v) \ 703 (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1) 704 #define BP_PXP_CSC2_COEF2_B3 16 705 #define BM_PXP_CSC2_COEF2_B3 0x07FF0000 706 #define BF_PXP_CSC2_COEF2_B3(v) \ 707 (((v) << 16) & BM_PXP_CSC2_COEF2_B3) 708 #define BP_PXP_CSC2_COEF2_RSVD0 11 709 #define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800 710 #define BF_PXP_CSC2_COEF2_RSVD0(v) \ 711 (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0) 712 #define BP_PXP_CSC2_COEF2_B2 0 713 #define BM_PXP_CSC2_COEF2_B2 0x000007FF 714 #define BF_PXP_CSC2_COEF2_B2(v) \ 715 (((v) << 0) & BM_PXP_CSC2_COEF2_B2) 716 717 #define HW_PXP_CSC2_COEF3 (0x00000210) 718 719 #define BP_PXP_CSC2_COEF3_RSVD1 27 720 #define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000 721 #define BF_PXP_CSC2_COEF3_RSVD1(v) \ 722 (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1) 723 #define BP_PXP_CSC2_COEF3_C2 16 724 #define BM_PXP_CSC2_COEF3_C2 0x07FF0000 725 #define BF_PXP_CSC2_COEF3_C2(v) \ 726 (((v) << 16) & BM_PXP_CSC2_COEF3_C2) 727 #define BP_PXP_CSC2_COEF3_RSVD0 11 728 #define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800 729 #define BF_PXP_CSC2_COEF3_RSVD0(v) \ 730 (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0) 731 #define BP_PXP_CSC2_COEF3_C1 0 732 #define BM_PXP_CSC2_COEF3_C1 0x000007FF 733 #define BF_PXP_CSC2_COEF3_C1(v) \ 734 (((v) << 0) & BM_PXP_CSC2_COEF3_C1) 735 736 #define HW_PXP_CSC2_COEF4 (0x00000220) 737 738 #define BP_PXP_CSC2_COEF4_RSVD1 25 739 #define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000 740 #define BF_PXP_CSC2_COEF4_RSVD1(v) \ 741 (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1) 742 #define BP_PXP_CSC2_COEF4_D1 16 743 #define BM_PXP_CSC2_COEF4_D1 0x01FF0000 744 #define BF_PXP_CSC2_COEF4_D1(v) \ 745 (((v) << 16) & BM_PXP_CSC2_COEF4_D1) 746 #define BP_PXP_CSC2_COEF4_RSVD0 11 747 #define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800 748 #define BF_PXP_CSC2_COEF4_RSVD0(v) \ 749 (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0) 750 #define BP_PXP_CSC2_COEF4_C3 0 751 #define BM_PXP_CSC2_COEF4_C3 0x000007FF 752 #define BF_PXP_CSC2_COEF4_C3(v) \ 753 (((v) << 0) & BM_PXP_CSC2_COEF4_C3) 754 755 #define HW_PXP_CSC2_COEF5 (0x00000230) 756 757 #define BP_PXP_CSC2_COEF5_RSVD1 25 758 #define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000 759 #define BF_PXP_CSC2_COEF5_RSVD1(v) \ 760 (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1) 761 #define BP_PXP_CSC2_COEF5_D3 16 762 #define BM_PXP_CSC2_COEF5_D3 0x01FF0000 763 #define BF_PXP_CSC2_COEF5_D3(v) \ 764 (((v) << 16) & BM_PXP_CSC2_COEF5_D3) 765 #define BP_PXP_CSC2_COEF5_RSVD0 9 766 #define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00 767 #define BF_PXP_CSC2_COEF5_RSVD0(v) \ 768 (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0) 769 #define BP_PXP_CSC2_COEF5_D2 0 770 #define BM_PXP_CSC2_COEF5_D2 0x000001FF 771 #define BF_PXP_CSC2_COEF5_D2(v) \ 772 (((v) << 0) & BM_PXP_CSC2_COEF5_D2) 773 774 #define HW_PXP_LUT_CTRL (0x00000240) 775 776 #define BM_PXP_LUT_CTRL_BYPASS 0x80000000 777 #define BF_PXP_LUT_CTRL_BYPASS(v) \ 778 (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS) 779 #define BP_PXP_LUT_CTRL_RSVD3 26 780 #define BM_PXP_LUT_CTRL_RSVD3 0x7C000000 781 #define BF_PXP_LUT_CTRL_RSVD3(v) \ 782 (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3) 783 #define BP_PXP_LUT_CTRL_LOOKUP_MODE 24 784 #define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000 785 #define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \ 786 (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE) 787 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0 788 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1 789 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2 790 #define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3 791 #define BP_PXP_LUT_CTRL_RSVD2 18 792 #define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000 793 #define BF_PXP_LUT_CTRL_RSVD2(v) \ 794 (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2) 795 #define BP_PXP_LUT_CTRL_OUT_MODE 16 796 #define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000 797 #define BF_PXP_LUT_CTRL_OUT_MODE(v) \ 798 (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE) 799 #define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0 800 #define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1 801 #define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2 802 #define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3 803 #define BP_PXP_LUT_CTRL_RSVD1 11 804 #define BM_PXP_LUT_CTRL_RSVD1 0x0000F800 805 #define BF_PXP_LUT_CTRL_RSVD1(v) \ 806 (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1) 807 #define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400 808 #define BF_PXP_LUT_CTRL_SEL_8KB(v) \ 809 (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB) 810 #define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200 811 #define BF_PXP_LUT_CTRL_LRU_UPD(v) \ 812 (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD) 813 #define BM_PXP_LUT_CTRL_INVALID 0x00000100 814 #define BF_PXP_LUT_CTRL_INVALID(v) \ 815 (((v) << 8) & BM_PXP_LUT_CTRL_INVALID) 816 #define BP_PXP_LUT_CTRL_RSVD0 1 817 #define BM_PXP_LUT_CTRL_RSVD0 0x000000FE 818 #define BF_PXP_LUT_CTRL_RSVD0(v) \ 819 (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0) 820 #define BM_PXP_LUT_CTRL_DMA_START 0x00000001 821 #define BF_PXP_LUT_CTRL_DMA_START(v) \ 822 (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START) 823 824 #define HW_PXP_LUT_ADDR (0x00000250) 825 826 #define BM_PXP_LUT_ADDR_RSVD2 0x80000000 827 #define BF_PXP_LUT_ADDR_RSVD2(v) \ 828 (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2) 829 #define BP_PXP_LUT_ADDR_NUM_BYTES 16 830 #define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000 831 #define BF_PXP_LUT_ADDR_NUM_BYTES(v) \ 832 (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES) 833 #define BP_PXP_LUT_ADDR_RSVD1 14 834 #define BM_PXP_LUT_ADDR_RSVD1 0x0000C000 835 #define BF_PXP_LUT_ADDR_RSVD1(v) \ 836 (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1) 837 #define BP_PXP_LUT_ADDR_ADDR 0 838 #define BM_PXP_LUT_ADDR_ADDR 0x00003FFF 839 #define BF_PXP_LUT_ADDR_ADDR(v) \ 840 (((v) << 0) & BM_PXP_LUT_ADDR_ADDR) 841 842 #define HW_PXP_LUT_DATA (0x00000260) 843 844 #define BP_PXP_LUT_DATA_DATA 0 845 #define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF 846 #define BF_PXP_LUT_DATA_DATA(v) (v) 847 848 #define HW_PXP_LUT_EXTMEM (0x00000270) 849 850 #define BP_PXP_LUT_EXTMEM_ADDR 0 851 #define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF 852 #define BF_PXP_LUT_EXTMEM_ADDR(v) (v) 853 854 #define HW_PXP_CFA (0x00000280) 855 856 #define BP_PXP_CFA_DATA 0 857 #define BM_PXP_CFA_DATA 0xFFFFFFFF 858 #define BF_PXP_CFA_DATA(v) (v) 859 860 #define HW_PXP_ALPHA_A_CTRL (0x00000290) 861 862 #define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24 863 #define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000 864 #define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \ 865 (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA) 866 #define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16 867 #define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 868 #define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \ 869 (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA) 870 #define BP_PXP_ALPHA_A_CTRL_RSVD0 14 871 #define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000 872 #define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \ 873 (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0) 874 #define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000 875 #define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \ 876 (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE) 877 #define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0 878 #define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1 879 #define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000 880 #define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \ 881 (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE) 882 #define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0 883 #define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1 884 #define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10 885 #define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 886 #define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ 887 (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE) 888 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 889 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0 890 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0 891 #define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0 892 #define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8 893 #define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300 894 #define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \ 895 (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE) 896 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0 897 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1 898 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2 899 #define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3 900 #define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080 901 #define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \ 902 (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1) 903 #define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040 904 #define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \ 905 (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE) 906 #define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0 907 #define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1 908 #define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020 909 #define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \ 910 (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE) 911 #define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0 912 #define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1 913 #define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3 914 #define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 915 #define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ 916 (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE) 917 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 918 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 919 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 920 #define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 921 #define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1 922 #define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006 923 #define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \ 924 (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE) 925 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0 926 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1 927 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2 928 #define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3 929 #define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001 930 #define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \ 931 (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE) 932 #define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0 933 #define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1 934 935 #define HW_PXP_ALPHA_B_CTRL (0x000002a0) 936 937 #define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24 938 #define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000 939 #define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \ 940 (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA) 941 #define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16 942 #define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000 943 #define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \ 944 (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA) 945 #define BP_PXP_ALPHA_B_CTRL_RSVD0 14 946 #define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000 947 #define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \ 948 (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0) 949 #define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000 950 #define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \ 951 (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE) 952 #define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0 953 #define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1 954 #define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000 955 #define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \ 956 (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE) 957 #define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0 958 #define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1 959 #define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10 960 #define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00 961 #define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \ 962 (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE) 963 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0 964 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1 965 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2 966 #define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3 967 #define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8 968 #define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300 969 #define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \ 970 (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE) 971 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0 972 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1 973 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2 974 #define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3 975 #define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080 976 #define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \ 977 (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1) 978 #define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040 979 #define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \ 980 (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE) 981 #define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0 982 #define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1 983 #define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020 984 #define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \ 985 (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE) 986 #define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0 987 #define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1 988 #define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3 989 #define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018 990 #define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \ 991 (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE) 992 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0 993 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1 994 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2 995 #define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3 996 #define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1 997 #define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006 998 #define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \ 999 (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE) 1000 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0 1001 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1 1002 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2 1003 #define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3 1004 #define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001 1005 #define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \ 1006 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE) 1007 #define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0 1008 #define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1 1009 1010 #define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0) 1011 1012 #define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8 1013 #define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00 1014 #define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \ 1015 (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0) 1016 #define BP_PXP_ALPHA_B_CTRL_1_ROP 4 1017 #define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0 1018 #define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \ 1019 (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP) 1020 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0 1021 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1 1022 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2 1023 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3 1024 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4 1025 #define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5 1026 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6 1027 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7 1028 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8 1029 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9 1030 #define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA 1031 #define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB 1032 #define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2 1033 #define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C 1034 #define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \ 1035 (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1) 1036 #define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002 1037 #define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \ 1038 (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE) 1039 #define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001 1040 #define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \ 1041 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE) 1042 1043 #define HW_PXP_PS_BACKGROUND_1 (0x000002c0) 1044 1045 #define BP_PXP_PS_BACKGROUND_1_RSVD 24 1046 #define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000 1047 #define BF_PXP_PS_BACKGROUND_1_RSVD(v) \ 1048 (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD) 1049 #define BP_PXP_PS_BACKGROUND_1_COLOR 0 1050 #define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF 1051 #define BF_PXP_PS_BACKGROUND_1_COLOR(v) \ 1052 (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR) 1053 1054 #define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0) 1055 1056 #define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24 1057 #define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000 1058 #define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \ 1059 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1) 1060 #define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0 1061 #define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF 1062 #define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \ 1063 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL) 1064 1065 #define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0) 1066 1067 #define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24 1068 #define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000 1069 #define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \ 1070 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1) 1071 #define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0 1072 #define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF 1073 #define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \ 1074 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL) 1075 1076 #define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0) 1077 1078 #define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24 1079 #define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000 1080 #define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \ 1081 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1) 1082 #define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0 1083 #define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF 1084 #define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \ 1085 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL) 1086 1087 #define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300) 1088 1089 #define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24 1090 #define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000 1091 #define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \ 1092 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1) 1093 #define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0 1094 #define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF 1095 #define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \ 1096 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL) 1097 1098 #define HW_PXP_CTRL2 (0x00000310) 1099 #define HW_PXP_CTRL2_SET (0x00000314) 1100 #define HW_PXP_CTRL2_CLR (0x00000318) 1101 #define HW_PXP_CTRL2_TOG (0x0000031c) 1102 1103 #define BP_PXP_CTRL2_RSVD3 28 1104 #define BM_PXP_CTRL2_RSVD3 0xF0000000 1105 #define BF_PXP_CTRL2_RSVD3(v) \ 1106 (((v) << 28) & BM_PXP_CTRL2_RSVD3) 1107 #define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000 1108 #define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \ 1109 (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1) 1110 #define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000 1111 #define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \ 1112 (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0) 1113 #define BM_PXP_CTRL2_ENABLE_LUT 0x02000000 1114 #define BF_PXP_CTRL2_ENABLE_LUT(v) \ 1115 (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT) 1116 #define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000 1117 #define BF_PXP_CTRL2_ENABLE_CSC2(v) \ 1118 (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2) 1119 #define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000 1120 #define BF_PXP_CTRL2_BLOCK_SIZE(v) \ 1121 (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE) 1122 #define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0 1123 #define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1 1124 #define BM_PXP_CTRL2_RSVD2 0x00400000 1125 #define BF_PXP_CTRL2_RSVD2(v) \ 1126 (((v) << 22) & BM_PXP_CTRL2_RSVD2) 1127 #define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000 1128 #define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \ 1129 (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B) 1130 #define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000 1131 #define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \ 1132 (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE) 1133 #define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000 1134 #define BF_PXP_CTRL2_ENABLE_WFE_B(v) \ 1135 (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B) 1136 #define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000 1137 #define BF_PXP_CTRL2_ENABLE_WFE_A(v) \ 1138 (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A) 1139 #define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000 1140 #define BF_PXP_CTRL2_ENABLE_DITHER(v) \ 1141 (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER) 1142 #define BM_PXP_CTRL2_RSVD1 0x00010000 1143 #define BF_PXP_CTRL2_RSVD1(v) \ 1144 (((v) << 16) & BM_PXP_CTRL2_RSVD1) 1145 #define BM_PXP_CTRL2_VFLIP1 0x00008000 1146 #define BF_PXP_CTRL2_VFLIP1(v) \ 1147 (((v) << 15) & BM_PXP_CTRL2_VFLIP1) 1148 #define BM_PXP_CTRL2_HFLIP1 0x00004000 1149 #define BF_PXP_CTRL2_HFLIP1(v) \ 1150 (((v) << 14) & BM_PXP_CTRL2_HFLIP1) 1151 #define BP_PXP_CTRL2_ROTATE1 12 1152 #define BM_PXP_CTRL2_ROTATE1 0x00003000 1153 #define BF_PXP_CTRL2_ROTATE1(v) \ 1154 (((v) << 12) & BM_PXP_CTRL2_ROTATE1) 1155 #define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0 1156 #define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1 1157 #define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2 1158 #define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3 1159 #define BM_PXP_CTRL2_VFLIP0 0x00000800 1160 #define BF_PXP_CTRL2_VFLIP0(v) \ 1161 (((v) << 11) & BM_PXP_CTRL2_VFLIP0) 1162 #define BM_PXP_CTRL2_HFLIP0 0x00000400 1163 #define BF_PXP_CTRL2_HFLIP0(v) \ 1164 (((v) << 10) & BM_PXP_CTRL2_HFLIP0) 1165 #define BP_PXP_CTRL2_ROTATE0 8 1166 #define BM_PXP_CTRL2_ROTATE0 0x00000300 1167 #define BF_PXP_CTRL2_ROTATE0(v) \ 1168 (((v) << 8) & BM_PXP_CTRL2_ROTATE0) 1169 #define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0 1170 #define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1 1171 #define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2 1172 #define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3 1173 #define BP_PXP_CTRL2_RSVD0 1 1174 #define BM_PXP_CTRL2_RSVD0 0x000000FE 1175 #define BF_PXP_CTRL2_RSVD0(v) \ 1176 (((v) << 1) & BM_PXP_CTRL2_RSVD0) 1177 #define BM_PXP_CTRL2_ENABLE 0x00000001 1178 #define BF_PXP_CTRL2_ENABLE(v) \ 1179 (((v) << 0) & BM_PXP_CTRL2_ENABLE) 1180 1181 #define HW_PXP_POWER_REG0 (0x00000320) 1182 1183 #define BP_PXP_POWER_REG0_CTRL 12 1184 #define BM_PXP_POWER_REG0_CTRL 0xFFFFF000 1185 #define BF_PXP_POWER_REG0_CTRL(v) \ 1186 (((v) << 12) & BM_PXP_POWER_REG0_CTRL) 1187 #define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9 1188 #define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00 1189 #define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \ 1190 (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE) 1191 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0 1192 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1 1193 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2 1194 #define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4 1195 #define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6 1196 #define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0 1197 #define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \ 1198 (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN) 1199 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0 1200 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1 1201 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2 1202 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4 1203 #define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3 1204 #define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038 1205 #define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \ 1206 (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN) 1207 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0 1208 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1 1209 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2 1210 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4 1211 #define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0 1212 #define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007 1213 #define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \ 1214 (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0) 1215 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0 1216 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1 1217 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2 1218 #define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4 1219 1220 #define HW_PXP_POWER_REG1 (0x00000330) 1221 1222 #define BP_PXP_POWER_REG1_RSVD0 24 1223 #define BM_PXP_POWER_REG1_RSVD0 0xFF000000 1224 #define BF_PXP_POWER_REG1_RSVD0(v) \ 1225 (((v) << 24) & BM_PXP_POWER_REG1_RSVD0) 1226 #define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21 1227 #define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000 1228 #define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \ 1229 (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE) 1230 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0 1231 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1 1232 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2 1233 #define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4 1234 #define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18 1235 #define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000 1236 #define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \ 1237 (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE) 1238 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0 1239 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1 1240 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2 1241 #define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4 1242 #define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15 1243 #define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000 1244 #define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \ 1245 (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE) 1246 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0 1247 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1 1248 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2 1249 #define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4 1250 #define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12 1251 #define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000 1252 #define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \ 1253 (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE) 1254 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0 1255 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1 1256 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2 1257 #define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4 1258 #define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9 1259 #define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00 1260 #define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \ 1261 (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE) 1262 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0 1263 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1 1264 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2 1265 #define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4 1266 #define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6 1267 #define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0 1268 #define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \ 1269 (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE) 1270 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0 1271 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1 1272 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2 1273 #define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4 1274 #define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3 1275 #define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038 1276 #define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \ 1277 (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE) 1278 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0 1279 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1 1280 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2 1281 #define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4 1282 #define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0 1283 #define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007 1284 #define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \ 1285 (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE) 1286 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0 1287 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1 1288 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2 1289 #define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4 1290 1291 #define HW_PXP_DATA_PATH_CTRL0 (0x00000340) 1292 #define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344) 1293 #define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348) 1294 #define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c) 1295 1296 #define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30 1297 #define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000 1298 #define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \ 1299 (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL) 1300 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0 1301 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1 1302 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2 1303 #define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3 1304 #define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28 1305 #define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000 1306 #define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \ 1307 (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL) 1308 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0 1309 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1 1310 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2 1311 #define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3 1312 #define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26 1313 #define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000 1314 #define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \ 1315 (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL) 1316 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0 1317 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1 1318 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2 1319 #define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3 1320 #define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24 1321 #define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000 1322 #define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \ 1323 (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL) 1324 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0 1325 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1 1326 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2 1327 #define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3 1328 #define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22 1329 #define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000 1330 #define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \ 1331 (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL) 1332 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0 1333 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1 1334 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2 1335 #define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3 1336 #define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20 1337 #define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000 1338 #define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \ 1339 (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL) 1340 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0 1341 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1 1342 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2 1343 #define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3 1344 #define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18 1345 #define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000 1346 #define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \ 1347 (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL) 1348 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0 1349 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1 1350 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2 1351 #define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3 1352 #define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16 1353 #define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000 1354 #define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \ 1355 (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL) 1356 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0 1357 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1 1358 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2 1359 #define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3 1360 #define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14 1361 #define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000 1362 #define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \ 1363 (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL) 1364 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0 1365 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1 1366 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2 1367 #define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3 1368 #define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12 1369 #define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000 1370 #define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \ 1371 (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL) 1372 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0 1373 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1 1374 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2 1375 #define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3 1376 #define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10 1377 #define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00 1378 #define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \ 1379 (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL) 1380 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0 1381 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1 1382 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2 1383 #define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3 1384 #define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8 1385 #define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300 1386 #define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \ 1387 (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL) 1388 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0 1389 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1 1390 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2 1391 #define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3 1392 #define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6 1393 #define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0 1394 #define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \ 1395 (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL) 1396 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0 1397 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1 1398 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2 1399 #define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3 1400 #define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4 1401 #define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030 1402 #define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \ 1403 (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL) 1404 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0 1405 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1 1406 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2 1407 #define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3 1408 #define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2 1409 #define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C 1410 #define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \ 1411 (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL) 1412 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0 1413 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1 1414 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2 1415 #define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3 1416 #define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0 1417 #define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003 1418 #define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \ 1419 (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL) 1420 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0 1421 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1 1422 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2 1423 #define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3 1424 1425 #define HW_PXP_DATA_PATH_CTRL1 (0x00000350) 1426 #define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354) 1427 #define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358) 1428 #define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c) 1429 1430 #define BP_PXP_DATA_PATH_CTRL1_RSVD0 4 1431 #define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0 1432 #define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \ 1433 (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0) 1434 #define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2 1435 #define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C 1436 #define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \ 1437 (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL) 1438 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0 1439 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1 1440 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2 1441 #define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3 1442 #define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0 1443 #define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003 1444 #define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \ 1445 (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL) 1446 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0 1447 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1 1448 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2 1449 #define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3 1450 1451 #define HW_PXP_INIT_MEM_CTRL (0x00000360) 1452 #define HW_PXP_INIT_MEM_CTRL_SET (0x00000364) 1453 #define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368) 1454 #define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c) 1455 1456 #define BM_PXP_INIT_MEM_CTRL_START 0x80000000 1457 #define BF_PXP_INIT_MEM_CTRL_START(v) \ 1458 (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START) 1459 #define BP_PXP_INIT_MEM_CTRL_SELECT 27 1460 #define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000 1461 #define BF_PXP_INIT_MEM_CTRL_SELECT(v) \ 1462 (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT) 1463 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0 1464 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1 1465 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2 1466 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3 1467 #define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4 1468 #define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5 1469 #define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6 1470 #define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7 1471 #define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8 1472 #define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15 1473 #define BP_PXP_INIT_MEM_CTRL_RSVD0 16 1474 #define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000 1475 #define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \ 1476 (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0) 1477 #define BP_PXP_INIT_MEM_CTRL_ADDR 0 1478 #define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF 1479 #define BF_PXP_INIT_MEM_CTRL_ADDR(v) \ 1480 (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR) 1481 1482 #define HW_PXP_INIT_MEM_DATA (0x00000370) 1483 1484 #define BP_PXP_INIT_MEM_DATA_DATA 0 1485 #define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF 1486 #define BF_PXP_INIT_MEM_DATA_DATA(v) (v) 1487 1488 #define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380) 1489 1490 #define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0 1491 #define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF 1492 #define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v) 1493 1494 #define HW_PXP_IRQ_MASK (0x00000390) 1495 #define HW_PXP_IRQ_MASK_SET (0x00000394) 1496 #define HW_PXP_IRQ_MASK_CLR (0x00000398) 1497 #define HW_PXP_IRQ_MASK_TOG (0x0000039c) 1498 1499 #define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000 1500 #define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \ 1501 (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN) 1502 #define BP_PXP_IRQ_MASK_RSVD1 16 1503 #define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000 1504 #define BF_PXP_IRQ_MASK_RSVD1(v) \ 1505 (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1) 1506 #define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000 1507 #define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \ 1508 (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN) 1509 #define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000 1510 #define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \ 1511 (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN) 1512 #define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000 1513 #define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \ 1514 (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN) 1515 #define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000 1516 #define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \ 1517 (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN) 1518 #define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800 1519 #define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \ 1520 (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN) 1521 #define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400 1522 #define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \ 1523 (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN) 1524 #define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200 1525 #define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \ 1526 (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN) 1527 #define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100 1528 #define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \ 1529 (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN) 1530 #define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080 1531 #define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \ 1532 (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN) 1533 #define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040 1534 #define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \ 1535 (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN) 1536 #define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020 1537 #define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \ 1538 (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN) 1539 #define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010 1540 #define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \ 1541 (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN) 1542 #define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008 1543 #define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \ 1544 (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN) 1545 #define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004 1546 #define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \ 1547 (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN) 1548 #define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002 1549 #define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \ 1550 (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN) 1551 #define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001 1552 #define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \ 1553 (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN) 1554 1555 #define HW_PXP_IRQ (0x000003a0) 1556 #define HW_PXP_IRQ_SET (0x000003a4) 1557 #define HW_PXP_IRQ_CLR (0x000003a8) 1558 #define HW_PXP_IRQ_TOG (0x000003ac) 1559 1560 #define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000 1561 #define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \ 1562 (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ) 1563 #define BP_PXP_IRQ_RSVD1 16 1564 #define BM_PXP_IRQ_RSVD1 0x7FFF0000 1565 #define BF_PXP_IRQ_RSVD1(v) \ 1566 (((v) << 16) & BM_PXP_IRQ_RSVD1) 1567 #define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000 1568 #define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \ 1569 (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ) 1570 #define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000 1571 #define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \ 1572 (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ) 1573 #define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000 1574 #define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \ 1575 (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ) 1576 #define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000 1577 #define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \ 1578 (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ) 1579 #define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800 1580 #define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \ 1581 (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ) 1582 #define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400 1583 #define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \ 1584 (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ) 1585 #define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200 1586 #define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \ 1587 (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ) 1588 #define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100 1589 #define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \ 1590 (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ) 1591 #define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080 1592 #define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \ 1593 (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ) 1594 #define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040 1595 #define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \ 1596 (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ) 1597 #define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020 1598 #define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \ 1599 (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ) 1600 #define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010 1601 #define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \ 1602 (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ) 1603 #define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008 1604 #define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \ 1605 (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ) 1606 #define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004 1607 #define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \ 1608 (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ) 1609 #define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002 1610 #define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \ 1611 (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ) 1612 #define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001 1613 #define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \ 1614 (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ) 1615 1616 #define HW_PXP_NEXT (0x00000400) 1617 1618 #define BP_PXP_NEXT_POINTER 2 1619 #define BM_PXP_NEXT_POINTER 0xFFFFFFFC 1620 #define BF_PXP_NEXT_POINTER(v) \ 1621 (((v) << 2) & BM_PXP_NEXT_POINTER) 1622 #define BM_PXP_NEXT_RSVD 0x00000002 1623 #define BF_PXP_NEXT_RSVD(v) \ 1624 (((v) << 1) & BM_PXP_NEXT_RSVD) 1625 #define BM_PXP_NEXT_ENABLED 0x00000001 1626 #define BF_PXP_NEXT_ENABLED(v) \ 1627 (((v) << 0) & BM_PXP_NEXT_ENABLED) 1628 1629 #define HW_PXP_DEBUGCTRL (0x00000410) 1630 1631 #define BP_PXP_DEBUGCTRL_RSVD 12 1632 #define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000 1633 #define BF_PXP_DEBUGCTRL_RSVD(v) \ 1634 (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD) 1635 #define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8 1636 #define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00 1637 #define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \ 1638 (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT) 1639 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0 1640 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1 1641 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2 1642 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4 1643 #define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8 1644 #define BP_PXP_DEBUGCTRL_SELECT 0 1645 #define BM_PXP_DEBUGCTRL_SELECT 0x000000FF 1646 #define BF_PXP_DEBUGCTRL_SELECT(v) \ 1647 (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) 1648 #define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 1649 #define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 1650 #define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2 1651 #define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3 1652 #define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4 1653 #define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5 1654 #define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 1655 #define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7 1656 #define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8 1657 #define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9 1658 #define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10 1659 #define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11 1660 #define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12 1661 #define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13 1662 #define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14 1663 1664 #define HW_PXP_DEBUG (0x00000420) 1665 1666 #define BP_PXP_DEBUG_DATA 0 1667 #define BM_PXP_DEBUG_DATA 0xFFFFFFFF 1668 #define BF_PXP_DEBUG_DATA(v) (v) 1669 1670 #define HW_PXP_VERSION (0x00000430) 1671 1672 #define BP_PXP_VERSION_MAJOR 24 1673 #define BM_PXP_VERSION_MAJOR 0xFF000000 1674 #define BF_PXP_VERSION_MAJOR(v) \ 1675 (((v) << 24) & BM_PXP_VERSION_MAJOR) 1676 #define BP_PXP_VERSION_MINOR 16 1677 #define BM_PXP_VERSION_MINOR 0x00FF0000 1678 #define BF_PXP_VERSION_MINOR(v) \ 1679 (((v) << 16) & BM_PXP_VERSION_MINOR) 1680 #define BP_PXP_VERSION_STEP 0 1681 #define BM_PXP_VERSION_STEP 0x0000FFFF 1682 #define BF_PXP_VERSION_STEP(v) \ 1683 (((v) << 0) & BM_PXP_VERSION_STEP) 1684 1685 #endif /* __IMX_PXP_H__ */ 1686