1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/spinlock.h> 30 31 #include <media/v4l2-common.h> 32 #include <media/v4l2-device.h> 33 #include <media/v4l2-fwnode.h> 34 #include <media/v4l2-mc.h> 35 #include <media/v4l2-subdev.h> 36 37 #define CSIS_DRIVER_NAME "imx-mipi-csis" 38 39 #define CSIS_PAD_SINK 0 40 #define CSIS_PAD_SOURCE 1 41 #define CSIS_PADS_NUM 2 42 43 #define MIPI_CSIS_DEF_PIX_WIDTH 640 44 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 45 46 /* Register map definition */ 47 48 /* CSIS version */ 49 #define MIPI_CSIS_VERSION 0x00 50 #define MIPI_CSIS_VERSION_IMX7D 0x03030505 51 #define MIPI_CSIS_VERSION_IMX8MP 0x03060301 52 53 /* CSIS common control */ 54 #define MIPI_CSIS_CMN_CTRL 0x04 55 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) 56 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) 57 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 58 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) 59 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) 60 61 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 62 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) 63 64 /* CSIS clock control */ 65 #define MIPI_CSIS_CLK_CTRL 0x08 66 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) 67 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) 68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) 69 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) 70 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) 71 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) 72 73 /* CSIS Interrupt mask */ 74 #define MIPI_CSIS_INT_MSK 0x10 75 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 76 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 77 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 78 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 79 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 80 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 81 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 82 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 83 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 84 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 85 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 86 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 87 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 88 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) 89 90 /* CSIS Interrupt source */ 91 #define MIPI_CSIS_INT_SRC 0x14 92 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 93 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 94 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 95 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 96 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 97 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 98 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 99 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) 100 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) 101 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) 102 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) 103 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) 104 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) 105 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 106 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 107 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 108 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) 109 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 110 111 /* D-PHY status control */ 112 #define MIPI_CSIS_DPHY_STATUS 0x20 113 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 114 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 115 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 116 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 117 118 /* D-PHY common control */ 119 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 120 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 121 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 122 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) 125 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) 126 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 127 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 128 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 129 130 /* D-PHY Master and Slave Control register Low */ 131 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 132 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 133 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 134 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 135 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 136 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 137 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 138 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 139 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 140 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 141 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 143 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 144 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 145 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 149 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 150 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 153 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 154 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 155 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 156 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 157 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 158 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 159 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 160 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 161 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 162 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 163 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 164 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 165 166 /* D-PHY Master and Slave Control register High */ 167 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 168 /* D-PHY Slave Control register Low */ 169 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 170 /* D-PHY Slave Control register High */ 171 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 172 173 /* ISP Configuration register */ 174 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 175 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) 176 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 177 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 178 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 179 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 180 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) 181 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) 182 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) 183 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) 184 185 /* ISP Image Resolution register */ 186 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 187 #define CSIS_MAX_PIX_WIDTH 0xffff 188 #define CSIS_MAX_PIX_HEIGHT 0xffff 189 190 /* ISP SYNC register */ 191 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 192 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 193 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 194 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 195 196 /* ISP shadow registers */ 197 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 198 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 199 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 200 201 /* Debug control register */ 202 #define MIPI_CSIS_DBG_CTRL 0xc0 203 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 204 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 205 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 206 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) 207 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) 208 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) 209 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) 210 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) 211 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) 212 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 213 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 214 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 215 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) 216 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) 217 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) 218 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) 219 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) 220 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) 221 222 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 223 224 /* Non-image packet data buffers */ 225 #define MIPI_CSIS_PKTDATA_ODD 0x2000 226 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 227 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 228 229 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL 230 231 /* MIPI CSI-2 Data Types */ 232 #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18 233 #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19 234 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a 235 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c 236 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d 237 #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e 238 #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f 239 #define MIPI_CSI2_DATA_TYPE_RGB565 0x22 240 #define MIPI_CSI2_DATA_TYPE_RGB666 0x23 241 #define MIPI_CSI2_DATA_TYPE_RGB888 0x24 242 #define MIPI_CSI2_DATA_TYPE_RAW6 0x28 243 #define MIPI_CSI2_DATA_TYPE_RAW7 0x29 244 #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a 245 #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b 246 #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c 247 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d 248 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) 249 250 struct mipi_csis_event { 251 bool debug; 252 u32 mask; 253 const char * const name; 254 unsigned int counter; 255 }; 256 257 static const struct mipi_csis_event mipi_csis_events[] = { 258 /* Errors */ 259 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, 260 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, 261 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, 262 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, 263 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 264 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 265 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 266 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, 267 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 268 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 269 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, 270 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, 271 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, 272 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, 273 /* Non-image data receive events */ 274 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 275 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 276 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 277 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 278 /* Frame start/end */ 279 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, 280 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, 281 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, 282 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, 283 }; 284 285 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 286 287 enum mipi_csis_clk { 288 MIPI_CSIS_CLK_PCLK, 289 MIPI_CSIS_CLK_WRAP, 290 MIPI_CSIS_CLK_PHY, 291 MIPI_CSIS_CLK_AXI, 292 }; 293 294 static const char * const mipi_csis_clk_id[] = { 295 "pclk", 296 "wrap", 297 "phy", 298 "axi", 299 }; 300 301 enum mipi_csis_version { 302 MIPI_CSIS_V3_3, 303 MIPI_CSIS_V3_6_3, 304 }; 305 306 struct mipi_csis_info { 307 enum mipi_csis_version version; 308 unsigned int num_clocks; 309 }; 310 311 struct mipi_csis_device { 312 struct device *dev; 313 void __iomem *regs; 314 struct clk_bulk_data *clks; 315 struct reset_control *mrst; 316 struct regulator *mipi_phy_regulator; 317 const struct mipi_csis_info *info; 318 319 struct v4l2_subdev sd; 320 struct media_pad pads[CSIS_PADS_NUM]; 321 struct v4l2_async_notifier notifier; 322 struct v4l2_subdev *src_sd; 323 324 struct v4l2_mbus_config_mipi_csi2 bus; 325 u32 clk_frequency; 326 u32 hs_settle; 327 u32 clk_settle; 328 329 spinlock_t slock; /* Protect events */ 330 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 331 struct dentry *debugfs_root; 332 struct { 333 bool enable; 334 u32 hs_settle; 335 u32 clk_settle; 336 } debug; 337 }; 338 339 /* ----------------------------------------------------------------------------- 340 * Format helpers 341 */ 342 343 struct csis_pix_format { 344 u32 code; 345 u32 output; 346 u32 data_type; 347 u8 width; 348 }; 349 350 static const struct csis_pix_format mipi_csis_formats[] = { 351 /* YUV formats. */ 352 { 353 .code = MEDIA_BUS_FMT_UYVY8_1X16, 354 .output = MEDIA_BUS_FMT_UYVY8_1X16, 355 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8, 356 .width = 16, 357 }, 358 /* RGB formats. */ 359 { 360 .code = MEDIA_BUS_FMT_RGB565_1X16, 361 .output = MEDIA_BUS_FMT_RGB565_1X16, 362 .data_type = MIPI_CSI2_DATA_TYPE_RGB565, 363 .width = 16, 364 }, { 365 .code = MEDIA_BUS_FMT_BGR888_1X24, 366 .output = MEDIA_BUS_FMT_RGB888_1X24, 367 .data_type = MIPI_CSI2_DATA_TYPE_RGB888, 368 .width = 24, 369 }, 370 /* RAW (Bayer and greyscale) formats. */ 371 { 372 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 373 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 374 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 375 .width = 8, 376 }, { 377 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 378 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 379 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 380 .width = 8, 381 }, { 382 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 383 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 384 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 385 .width = 8, 386 }, { 387 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 388 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 389 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 390 .width = 8, 391 }, { 392 .code = MEDIA_BUS_FMT_Y8_1X8, 393 .output = MEDIA_BUS_FMT_Y8_1X8, 394 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 395 .width = 8, 396 }, { 397 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 398 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 399 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 400 .width = 10, 401 }, { 402 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 403 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 404 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 405 .width = 10, 406 }, { 407 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 408 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 409 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 410 .width = 10, 411 }, { 412 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 413 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 414 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 415 .width = 10, 416 }, { 417 .code = MEDIA_BUS_FMT_Y10_1X10, 418 .output = MEDIA_BUS_FMT_Y10_1X10, 419 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 420 .width = 10, 421 }, { 422 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 423 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 424 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 425 .width = 12, 426 }, { 427 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 428 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 429 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 430 .width = 12, 431 }, { 432 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 433 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 434 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 435 .width = 12, 436 }, { 437 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 438 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 439 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 440 .width = 12, 441 }, { 442 .code = MEDIA_BUS_FMT_Y12_1X12, 443 .output = MEDIA_BUS_FMT_Y12_1X12, 444 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 445 .width = 12, 446 }, { 447 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 448 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 449 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 450 .width = 14, 451 }, { 452 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 453 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 454 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 455 .width = 14, 456 }, { 457 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 458 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 459 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 460 .width = 14, 461 }, { 462 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 463 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 464 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 465 .width = 14, 466 }, 467 /* JPEG */ 468 { 469 .code = MEDIA_BUS_FMT_JPEG_1X8, 470 .output = MEDIA_BUS_FMT_JPEG_1X8, 471 /* 472 * Map JPEG_1X8 to the RAW8 datatype. 473 * 474 * The CSI-2 specification suggests in Annex A "JPEG8 Data 475 * Format (informative)" to transmit JPEG data using one of the 476 * Data Types aimed to represent arbitrary data, such as the 477 * "User Defined Data Type 1" (0x30). 478 * 479 * However, when configured with a User Defined Data Type, the 480 * CSIS outputs data in quad pixel mode regardless of the mode 481 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 482 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 483 * or ISI) support quad pixel mode, so this will never work in 484 * practice. 485 * 486 * Some sensors (such as the OV5640) send JPEG data using the 487 * RAW8 data type. This is usable and works, so map the JPEG 488 * format to RAW8. If the CSIS ends up being integrated in an 489 * SoC that can support quad pixel mode, this will have to be 490 * revisited. 491 */ 492 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 493 .width = 8, 494 } 495 }; 496 497 static const struct csis_pix_format *find_csis_format(u32 code) 498 { 499 unsigned int i; 500 501 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 502 if (code == mipi_csis_formats[i].code) 503 return &mipi_csis_formats[i]; 504 return NULL; 505 } 506 507 /* ----------------------------------------------------------------------------- 508 * Hardware configuration 509 */ 510 511 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 512 { 513 return readl(csis->regs + reg); 514 } 515 516 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 517 u32 val) 518 { 519 writel(val, csis->regs + reg); 520 } 521 522 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 523 { 524 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 525 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 526 } 527 528 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 529 { 530 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 531 532 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 533 val | MIPI_CSIS_CMN_CTRL_RESET); 534 usleep_range(10, 20); 535 } 536 537 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 538 { 539 u32 val, mask; 540 541 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 542 if (on) 543 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 544 else 545 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 546 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 547 548 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 549 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 550 if (on) { 551 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 552 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 553 } 554 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 555 } 556 557 static void __mipi_csis_set_format(struct mipi_csis_device *csis, 558 const struct v4l2_mbus_framefmt *format, 559 const struct csis_pix_format *csis_fmt) 560 { 561 u32 val; 562 563 /* Color format */ 564 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 565 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 566 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 567 568 /* 569 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 570 * (referred to in the documentation as single and dual pixel modes 571 * respectively, although the 8-bit mode transfers half a pixel per 572 * clock sample and the 16-bit mode one pixel). While both mode work 573 * when the CSIS is connected to a receiver that supports either option, 574 * single pixel mode requires clock rates twice as high. As all SoCs 575 * that integrate the CSIS can operate in 16-bit bit mode, and some do 576 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 577 * pixel mode unconditionally. 578 * 579 * TODO: Verify which other formats require DUAL (or QUAD) modes. 580 */ 581 if (csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 582 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 583 584 val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type); 585 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 586 587 /* Pixel resolution */ 588 val = format->width | (format->height << 16); 589 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 590 } 591 592 static int mipi_csis_calculate_params(struct mipi_csis_device *csis, 593 const struct csis_pix_format *csis_fmt) 594 { 595 s64 link_freq; 596 u32 lane_rate; 597 598 /* Calculate the line rate from the pixel rate. */ 599 link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler, 600 csis_fmt->width, 601 csis->bus.num_data_lanes * 2); 602 if (link_freq < 0) { 603 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 604 (int)link_freq); 605 return link_freq; 606 } 607 608 lane_rate = link_freq * 2; 609 610 if (lane_rate < 80000000 || lane_rate > 1500000000) { 611 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 612 return -EINVAL; 613 } 614 615 /* 616 * The HSSETTLE counter value is document in a table, but can also 617 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 618 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 619 * we figure out how to compute it correctly. 620 */ 621 csis->hs_settle = (lane_rate - 5000000) / 45000000; 622 csis->clk_settle = 0; 623 624 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 625 lane_rate, csis->clk_settle, csis->hs_settle); 626 627 if (csis->debug.hs_settle < 0xff) { 628 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 629 csis->debug.hs_settle); 630 csis->hs_settle = csis->debug.hs_settle; 631 } 632 633 if (csis->debug.clk_settle < 4) { 634 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 635 csis->debug.clk_settle); 636 csis->clk_settle = csis->debug.clk_settle; 637 } 638 639 return 0; 640 } 641 642 static void mipi_csis_set_params(struct mipi_csis_device *csis, 643 const struct v4l2_mbus_framefmt *format, 644 const struct csis_pix_format *csis_fmt) 645 { 646 int lanes = csis->bus.num_data_lanes; 647 u32 val; 648 649 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 650 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 651 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 652 if (csis->info->version == MIPI_CSIS_V3_3) 653 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 654 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 655 656 __mipi_csis_set_format(csis, format, csis_fmt); 657 658 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 659 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 660 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 661 662 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 663 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 664 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 665 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 666 667 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 668 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 669 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 670 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 671 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 672 673 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 674 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 675 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 676 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 677 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 678 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 679 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 680 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 681 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 682 683 /* Update the shadow register. */ 684 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 685 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 686 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 687 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 688 } 689 690 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 691 { 692 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 693 } 694 695 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 696 { 697 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 698 } 699 700 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 701 { 702 unsigned int i; 703 int ret; 704 705 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 706 sizeof(*csis->clks), GFP_KERNEL); 707 708 if (!csis->clks) 709 return -ENOMEM; 710 711 for (i = 0; i < csis->info->num_clocks; i++) 712 csis->clks[i].id = mipi_csis_clk_id[i]; 713 714 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 715 csis->clks); 716 if (ret < 0) 717 return ret; 718 719 /* Set clock rate */ 720 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 721 csis->clk_frequency); 722 if (ret < 0) 723 dev_err(csis->dev, "set rate=%d failed: %d\n", 724 csis->clk_frequency, ret); 725 726 return ret; 727 } 728 729 static void mipi_csis_start_stream(struct mipi_csis_device *csis, 730 const struct v4l2_mbus_framefmt *format, 731 const struct csis_pix_format *csis_fmt) 732 { 733 mipi_csis_sw_reset(csis); 734 mipi_csis_set_params(csis, format, csis_fmt); 735 mipi_csis_system_enable(csis, true); 736 mipi_csis_enable_interrupts(csis, true); 737 } 738 739 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 740 { 741 mipi_csis_enable_interrupts(csis, false); 742 mipi_csis_system_enable(csis, false); 743 } 744 745 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 746 { 747 struct mipi_csis_device *csis = dev_id; 748 unsigned long flags; 749 unsigned int i; 750 u32 status; 751 u32 dbg_status; 752 753 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 754 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 755 756 spin_lock_irqsave(&csis->slock, flags); 757 758 /* Update the event/error counters */ 759 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 760 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 761 struct mipi_csis_event *event = &csis->events[i]; 762 763 if ((!event->debug && (status & event->mask)) || 764 (event->debug && (dbg_status & event->mask))) 765 event->counter++; 766 } 767 } 768 spin_unlock_irqrestore(&csis->slock, flags); 769 770 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 771 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 772 773 return IRQ_HANDLED; 774 } 775 776 /* ----------------------------------------------------------------------------- 777 * PHY regulator and reset 778 */ 779 780 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 781 { 782 if (csis->info->version != MIPI_CSIS_V3_3) 783 return 0; 784 785 return regulator_enable(csis->mipi_phy_regulator); 786 } 787 788 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 789 { 790 if (csis->info->version != MIPI_CSIS_V3_3) 791 return 0; 792 793 return regulator_disable(csis->mipi_phy_regulator); 794 } 795 796 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 797 { 798 if (csis->info->version != MIPI_CSIS_V3_3) 799 return; 800 801 reset_control_assert(csis->mrst); 802 msleep(20); 803 reset_control_deassert(csis->mrst); 804 } 805 806 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 807 { 808 if (csis->info->version != MIPI_CSIS_V3_3) 809 return 0; 810 811 /* Get MIPI PHY reset and regulator. */ 812 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 813 if (IS_ERR(csis->mrst)) 814 return PTR_ERR(csis->mrst); 815 816 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 817 if (IS_ERR(csis->mipi_phy_regulator)) 818 return PTR_ERR(csis->mipi_phy_regulator); 819 820 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 821 1000000); 822 } 823 824 /* ----------------------------------------------------------------------------- 825 * Debug 826 */ 827 828 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 829 { 830 unsigned long flags; 831 unsigned int i; 832 833 spin_lock_irqsave(&csis->slock, flags); 834 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 835 csis->events[i].counter = 0; 836 spin_unlock_irqrestore(&csis->slock, flags); 837 } 838 839 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 840 { 841 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 842 : MIPI_CSIS_NUM_EVENTS - 8; 843 unsigned long flags; 844 unsigned int i; 845 846 spin_lock_irqsave(&csis->slock, flags); 847 848 for (i = 0; i < num_events; ++i) { 849 if (csis->events[i].counter > 0 || csis->debug.enable) 850 dev_info(csis->dev, "%s events: %d\n", 851 csis->events[i].name, 852 csis->events[i].counter); 853 } 854 spin_unlock_irqrestore(&csis->slock, flags); 855 } 856 857 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 858 { 859 static const struct { 860 u32 offset; 861 const char * const name; 862 } registers[] = { 863 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, 864 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, 865 { MIPI_CSIS_INT_MSK, "INT_MSK" }, 866 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, 867 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, 868 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, 869 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, 870 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, 871 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, 872 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, 873 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, 874 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, 875 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, 876 }; 877 878 unsigned int i; 879 u32 cfg; 880 881 if (!pm_runtime_get_if_in_use(csis->dev)) 882 return 0; 883 884 dev_info(csis->dev, "--- REGISTERS ---\n"); 885 886 for (i = 0; i < ARRAY_SIZE(registers); i++) { 887 cfg = mipi_csis_read(csis, registers[i].offset); 888 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 889 } 890 891 pm_runtime_put(csis->dev); 892 893 return 0; 894 } 895 896 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 897 { 898 struct mipi_csis_device *csis = m->private; 899 900 return mipi_csis_dump_regs(csis); 901 } 902 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 903 904 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 905 { 906 csis->debug.hs_settle = UINT_MAX; 907 csis->debug.clk_settle = UINT_MAX; 908 909 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 910 911 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 912 &csis->debug.enable); 913 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 914 &mipi_csis_dump_regs_fops); 915 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 916 &csis->debug.clk_settle); 917 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 918 &csis->debug.hs_settle); 919 } 920 921 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 922 { 923 debugfs_remove_recursive(csis->debugfs_root); 924 } 925 926 /* ----------------------------------------------------------------------------- 927 * V4L2 subdev operations 928 */ 929 930 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 931 { 932 return container_of(sdev, struct mipi_csis_device, sd); 933 } 934 935 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 936 { 937 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 938 const struct v4l2_mbus_framefmt *format; 939 const struct csis_pix_format *csis_fmt; 940 struct v4l2_subdev_state *state; 941 int ret; 942 943 if (!enable) { 944 v4l2_subdev_call(csis->src_sd, video, s_stream, 0); 945 946 mipi_csis_stop_stream(csis); 947 if (csis->debug.enable) 948 mipi_csis_log_counters(csis, true); 949 950 pm_runtime_put(csis->dev); 951 952 return 0; 953 } 954 955 state = v4l2_subdev_lock_and_get_active_state(sd); 956 957 format = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SINK); 958 csis_fmt = find_csis_format(format->code); 959 960 ret = mipi_csis_calculate_params(csis, csis_fmt); 961 if (ret < 0) 962 goto err_unlock; 963 964 mipi_csis_clear_counters(csis); 965 966 ret = pm_runtime_resume_and_get(csis->dev); 967 if (ret < 0) 968 goto err_unlock; 969 970 mipi_csis_start_stream(csis, format, csis_fmt); 971 972 ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1); 973 if (ret < 0) 974 goto err_stop; 975 976 mipi_csis_log_counters(csis, true); 977 978 v4l2_subdev_unlock_state(state); 979 980 return 0; 981 982 err_stop: 983 mipi_csis_stop_stream(csis); 984 pm_runtime_put(csis->dev); 985 err_unlock: 986 v4l2_subdev_unlock_state(state); 987 988 return ret; 989 } 990 991 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 992 struct v4l2_subdev_state *sd_state, 993 struct v4l2_subdev_mbus_code_enum *code) 994 { 995 /* 996 * The CSIS can't transcode in any way, the source format is identical 997 * to the sink format. 998 */ 999 if (code->pad == CSIS_PAD_SOURCE) { 1000 struct v4l2_mbus_framefmt *fmt; 1001 1002 if (code->index > 0) 1003 return -EINVAL; 1004 1005 fmt = v4l2_subdev_get_pad_format(sd, sd_state, code->pad); 1006 code->code = fmt->code; 1007 return 0; 1008 } 1009 1010 if (code->pad != CSIS_PAD_SINK) 1011 return -EINVAL; 1012 1013 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1014 return -EINVAL; 1015 1016 code->code = mipi_csis_formats[code->index].code; 1017 1018 return 0; 1019 } 1020 1021 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1022 struct v4l2_subdev_state *sd_state, 1023 struct v4l2_subdev_format *sdformat) 1024 { 1025 struct csis_pix_format const *csis_fmt; 1026 struct v4l2_mbus_framefmt *fmt; 1027 unsigned int align; 1028 1029 /* 1030 * The CSIS can't transcode in any way, the source format can't be 1031 * modified. 1032 */ 1033 if (sdformat->pad == CSIS_PAD_SOURCE) 1034 return v4l2_subdev_get_fmt(sd, sd_state, sdformat); 1035 1036 if (sdformat->pad != CSIS_PAD_SINK) 1037 return -EINVAL; 1038 1039 /* 1040 * Validate the media bus code and clamp and align the size. 1041 * 1042 * The total number of bits per line must be a multiple of 8. We thus 1043 * need to align the width for formats that are not multiples of 8 1044 * bits. 1045 */ 1046 csis_fmt = find_csis_format(sdformat->format.code); 1047 if (!csis_fmt) 1048 csis_fmt = &mipi_csis_formats[0]; 1049 1050 switch (csis_fmt->width % 8) { 1051 case 0: 1052 align = 0; 1053 break; 1054 case 4: 1055 align = 1; 1056 break; 1057 case 2: 1058 case 6: 1059 align = 2; 1060 break; 1061 default: 1062 /* 1, 3, 5, 7 */ 1063 align = 3; 1064 break; 1065 } 1066 1067 v4l_bound_align_image(&sdformat->format.width, 1, 1068 CSIS_MAX_PIX_WIDTH, align, 1069 &sdformat->format.height, 1, 1070 CSIS_MAX_PIX_HEIGHT, 0, 0); 1071 1072 fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat->pad); 1073 1074 fmt->code = csis_fmt->code; 1075 fmt->width = sdformat->format.width; 1076 fmt->height = sdformat->format.height; 1077 fmt->field = V4L2_FIELD_NONE; 1078 fmt->colorspace = sdformat->format.colorspace; 1079 fmt->quantization = sdformat->format.quantization; 1080 fmt->xfer_func = sdformat->format.xfer_func; 1081 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1082 1083 sdformat->format = *fmt; 1084 1085 /* Propagate the format from sink to source. */ 1086 fmt = v4l2_subdev_get_pad_format(sd, sd_state, CSIS_PAD_SOURCE); 1087 *fmt = sdformat->format; 1088 1089 /* The format on the source pad might change due to unpacking. */ 1090 fmt->code = csis_fmt->output; 1091 1092 return 0; 1093 } 1094 1095 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 1096 struct v4l2_mbus_frame_desc *fd) 1097 { 1098 struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0]; 1099 const struct csis_pix_format *csis_fmt; 1100 const struct v4l2_mbus_framefmt *fmt; 1101 struct v4l2_subdev_state *state; 1102 1103 if (pad != CSIS_PAD_SOURCE) 1104 return -EINVAL; 1105 1106 state = v4l2_subdev_lock_and_get_active_state(sd); 1107 fmt = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SOURCE); 1108 csis_fmt = find_csis_format(fmt->code); 1109 v4l2_subdev_unlock_state(state); 1110 1111 if (!csis_fmt) 1112 return -EPIPE; 1113 1114 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL; 1115 fd->num_entries = 1; 1116 1117 memset(entry, 0, sizeof(*entry)); 1118 1119 entry->flags = 0; 1120 entry->pixelcode = csis_fmt->code; 1121 entry->bus.csi2.vc = 0; 1122 entry->bus.csi2.dt = csis_fmt->data_type; 1123 1124 return 0; 1125 } 1126 1127 static int mipi_csis_init_cfg(struct v4l2_subdev *sd, 1128 struct v4l2_subdev_state *sd_state) 1129 { 1130 struct v4l2_subdev_format fmt = { 1131 .pad = CSIS_PAD_SINK, 1132 }; 1133 1134 fmt.format.code = mipi_csis_formats[0].code; 1135 fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH; 1136 fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT; 1137 1138 fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1139 fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace); 1140 fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace); 1141 fmt.format.quantization = 1142 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace, 1143 fmt.format.ycbcr_enc); 1144 1145 return mipi_csis_set_fmt(sd, sd_state, &fmt); 1146 } 1147 1148 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1149 { 1150 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1151 1152 mipi_csis_log_counters(csis, true); 1153 if (csis->debug.enable) 1154 mipi_csis_dump_regs(csis); 1155 1156 return 0; 1157 } 1158 1159 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1160 .log_status = mipi_csis_log_status, 1161 }; 1162 1163 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1164 .s_stream = mipi_csis_s_stream, 1165 }; 1166 1167 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1168 .init_cfg = mipi_csis_init_cfg, 1169 .enum_mbus_code = mipi_csis_enum_mbus_code, 1170 .get_fmt = v4l2_subdev_get_fmt, 1171 .set_fmt = mipi_csis_set_fmt, 1172 .get_frame_desc = mipi_csis_get_frame_desc, 1173 }; 1174 1175 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1176 .core = &mipi_csis_core_ops, 1177 .video = &mipi_csis_video_ops, 1178 .pad = &mipi_csis_pad_ops, 1179 }; 1180 1181 /* ----------------------------------------------------------------------------- 1182 * Media entity operations 1183 */ 1184 1185 static int mipi_csis_link_setup(struct media_entity *entity, 1186 const struct media_pad *local_pad, 1187 const struct media_pad *remote_pad, u32 flags) 1188 { 1189 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1190 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1191 struct v4l2_subdev *remote_sd; 1192 1193 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1194 local_pad->entity->name); 1195 1196 /* We only care about the link to the source. */ 1197 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1198 return 0; 1199 1200 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1201 1202 if (flags & MEDIA_LNK_FL_ENABLED) { 1203 if (csis->src_sd) 1204 return -EBUSY; 1205 1206 csis->src_sd = remote_sd; 1207 } else { 1208 csis->src_sd = NULL; 1209 } 1210 1211 return 0; 1212 } 1213 1214 static const struct media_entity_operations mipi_csis_entity_ops = { 1215 .link_setup = mipi_csis_link_setup, 1216 .link_validate = v4l2_subdev_link_validate, 1217 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1218 }; 1219 1220 /* ----------------------------------------------------------------------------- 1221 * Async subdev notifier 1222 */ 1223 1224 static struct mipi_csis_device * 1225 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1226 { 1227 return container_of(n, struct mipi_csis_device, notifier); 1228 } 1229 1230 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1231 struct v4l2_subdev *sd, 1232 struct v4l2_async_connection *asd) 1233 { 1234 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1235 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1236 1237 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1238 } 1239 1240 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1241 .bound = mipi_csis_notify_bound, 1242 }; 1243 1244 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1245 { 1246 struct v4l2_fwnode_endpoint vep = { 1247 .bus_type = V4L2_MBUS_CSI2_DPHY, 1248 }; 1249 struct v4l2_async_connection *asd; 1250 struct fwnode_handle *ep; 1251 unsigned int i; 1252 int ret; 1253 1254 v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd); 1255 1256 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1257 FWNODE_GRAPH_ENDPOINT_NEXT); 1258 if (!ep) 1259 return -ENOTCONN; 1260 1261 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1262 if (ret) 1263 goto err_parse; 1264 1265 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1266 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1267 dev_err(csis->dev, 1268 "data lanes reordering is not supported"); 1269 ret = -EINVAL; 1270 goto err_parse; 1271 } 1272 } 1273 1274 csis->bus = vep.bus.mipi_csi2; 1275 1276 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1277 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1278 1279 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1280 struct v4l2_async_connection); 1281 if (IS_ERR(asd)) { 1282 ret = PTR_ERR(asd); 1283 goto err_parse; 1284 } 1285 1286 fwnode_handle_put(ep); 1287 1288 csis->notifier.ops = &mipi_csis_notify_ops; 1289 1290 ret = v4l2_async_nf_register(&csis->notifier); 1291 if (ret) 1292 return ret; 1293 1294 return v4l2_async_register_subdev(&csis->sd); 1295 1296 err_parse: 1297 fwnode_handle_put(ep); 1298 1299 return ret; 1300 } 1301 1302 /* ----------------------------------------------------------------------------- 1303 * Suspend/resume 1304 */ 1305 1306 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) 1307 { 1308 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1309 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1310 int ret; 1311 1312 ret = mipi_csis_phy_disable(csis); 1313 if (ret) 1314 return -EAGAIN; 1315 1316 mipi_csis_clk_disable(csis); 1317 1318 return 0; 1319 } 1320 1321 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) 1322 { 1323 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1324 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1325 int ret; 1326 1327 ret = mipi_csis_phy_enable(csis); 1328 if (ret) 1329 return -EAGAIN; 1330 1331 ret = mipi_csis_clk_enable(csis); 1332 if (ret) { 1333 mipi_csis_phy_disable(csis); 1334 return ret; 1335 } 1336 1337 return 0; 1338 } 1339 1340 static const struct dev_pm_ops mipi_csis_pm_ops = { 1341 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1342 NULL) 1343 }; 1344 1345 /* ----------------------------------------------------------------------------- 1346 * Probe/remove & platform driver 1347 */ 1348 1349 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1350 { 1351 struct v4l2_subdev *sd = &csis->sd; 1352 int ret; 1353 1354 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1355 sd->owner = THIS_MODULE; 1356 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1357 dev_name(csis->dev)); 1358 1359 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1360 sd->ctrl_handler = NULL; 1361 1362 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1363 sd->entity.ops = &mipi_csis_entity_ops; 1364 1365 sd->dev = csis->dev; 1366 1367 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1368 | MEDIA_PAD_FL_MUST_CONNECT; 1369 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1370 | MEDIA_PAD_FL_MUST_CONNECT; 1371 ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads); 1372 if (ret) 1373 return ret; 1374 1375 ret = v4l2_subdev_init_finalize(sd); 1376 if (ret) { 1377 media_entity_cleanup(&sd->entity); 1378 return ret; 1379 } 1380 1381 return 0; 1382 } 1383 1384 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1385 { 1386 struct device_node *node = csis->dev->of_node; 1387 1388 if (of_property_read_u32(node, "clock-frequency", 1389 &csis->clk_frequency)) 1390 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1391 1392 return 0; 1393 } 1394 1395 static int mipi_csis_probe(struct platform_device *pdev) 1396 { 1397 struct device *dev = &pdev->dev; 1398 struct mipi_csis_device *csis; 1399 int irq; 1400 int ret; 1401 1402 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1403 if (!csis) 1404 return -ENOMEM; 1405 1406 spin_lock_init(&csis->slock); 1407 1408 csis->dev = dev; 1409 csis->info = of_device_get_match_data(dev); 1410 1411 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1412 1413 /* Parse DT properties. */ 1414 ret = mipi_csis_parse_dt(csis); 1415 if (ret < 0) { 1416 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1417 return ret; 1418 } 1419 1420 /* Acquire resources. */ 1421 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1422 if (IS_ERR(csis->regs)) 1423 return PTR_ERR(csis->regs); 1424 1425 irq = platform_get_irq(pdev, 0); 1426 if (irq < 0) 1427 return irq; 1428 1429 ret = mipi_csis_phy_init(csis); 1430 if (ret < 0) 1431 return ret; 1432 1433 ret = mipi_csis_clk_get(csis); 1434 if (ret < 0) 1435 return ret; 1436 1437 /* Reset PHY and enable the clocks. */ 1438 mipi_csis_phy_reset(csis); 1439 1440 ret = mipi_csis_clk_enable(csis); 1441 if (ret < 0) { 1442 dev_err(csis->dev, "failed to enable clocks: %d\n", ret); 1443 return ret; 1444 } 1445 1446 /* Now that the hardware is initialized, request the interrupt. */ 1447 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1448 dev_name(dev), csis); 1449 if (ret) { 1450 dev_err(dev, "Interrupt request failed\n"); 1451 goto err_disable_clock; 1452 } 1453 1454 /* Initialize and register the subdev. */ 1455 ret = mipi_csis_subdev_init(csis); 1456 if (ret < 0) 1457 goto err_disable_clock; 1458 1459 platform_set_drvdata(pdev, &csis->sd); 1460 1461 ret = mipi_csis_async_register(csis); 1462 if (ret < 0) { 1463 dev_err(dev, "async register failed: %d\n", ret); 1464 goto err_cleanup; 1465 } 1466 1467 /* Initialize debugfs. */ 1468 mipi_csis_debugfs_init(csis); 1469 1470 /* Enable runtime PM. */ 1471 pm_runtime_enable(dev); 1472 if (!pm_runtime_enabled(dev)) { 1473 ret = mipi_csis_runtime_resume(dev); 1474 if (ret < 0) 1475 goto err_unregister_all; 1476 } 1477 1478 dev_info(dev, "lanes: %d, freq: %u\n", 1479 csis->bus.num_data_lanes, csis->clk_frequency); 1480 1481 return 0; 1482 1483 err_unregister_all: 1484 mipi_csis_debugfs_exit(csis); 1485 err_cleanup: 1486 v4l2_subdev_cleanup(&csis->sd); 1487 media_entity_cleanup(&csis->sd.entity); 1488 v4l2_async_nf_unregister(&csis->notifier); 1489 v4l2_async_nf_cleanup(&csis->notifier); 1490 v4l2_async_unregister_subdev(&csis->sd); 1491 err_disable_clock: 1492 mipi_csis_clk_disable(csis); 1493 1494 return ret; 1495 } 1496 1497 static void mipi_csis_remove(struct platform_device *pdev) 1498 { 1499 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1500 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1501 1502 mipi_csis_debugfs_exit(csis); 1503 v4l2_async_nf_unregister(&csis->notifier); 1504 v4l2_async_nf_cleanup(&csis->notifier); 1505 v4l2_async_unregister_subdev(&csis->sd); 1506 1507 pm_runtime_disable(&pdev->dev); 1508 mipi_csis_runtime_suspend(&pdev->dev); 1509 mipi_csis_clk_disable(csis); 1510 v4l2_subdev_cleanup(&csis->sd); 1511 media_entity_cleanup(&csis->sd.entity); 1512 pm_runtime_set_suspended(&pdev->dev); 1513 } 1514 1515 static const struct of_device_id mipi_csis_of_match[] = { 1516 { 1517 .compatible = "fsl,imx7-mipi-csi2", 1518 .data = &(const struct mipi_csis_info){ 1519 .version = MIPI_CSIS_V3_3, 1520 .num_clocks = 3, 1521 }, 1522 }, { 1523 .compatible = "fsl,imx8mm-mipi-csi2", 1524 .data = &(const struct mipi_csis_info){ 1525 .version = MIPI_CSIS_V3_6_3, 1526 .num_clocks = 4, 1527 }, 1528 }, 1529 { /* sentinel */ }, 1530 }; 1531 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1532 1533 static struct platform_driver mipi_csis_driver = { 1534 .probe = mipi_csis_probe, 1535 .remove_new = mipi_csis_remove, 1536 .driver = { 1537 .of_match_table = mipi_csis_of_match, 1538 .name = CSIS_DRIVER_NAME, 1539 .pm = &mipi_csis_pm_ops, 1540 }, 1541 }; 1542 1543 module_platform_driver(mipi_csis_driver); 1544 1545 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1546 MODULE_LICENSE("GPL v2"); 1547 MODULE_ALIAS("platform:imx-mipi-csi2"); 1548