1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/spinlock.h> 30 31 #include <media/mipi-csi2.h> 32 #include <media/v4l2-common.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-event.h> 35 #include <media/v4l2-fwnode.h> 36 #include <media/v4l2-mc.h> 37 #include <media/v4l2-subdev.h> 38 39 #define CSIS_DRIVER_NAME "imx-mipi-csis" 40 41 #define CSIS_PAD_SINK 0 42 #define CSIS_PAD_SOURCE 1 43 #define CSIS_PADS_NUM 2 44 45 #define MIPI_CSIS_DEF_PIX_WIDTH 640 46 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 47 48 /* Register map definition */ 49 50 /* CSIS version */ 51 #define MIPI_CSIS_VERSION 0x00 52 #define MIPI_CSIS_VERSION_IMX7D 0x03030505 53 #define MIPI_CSIS_VERSION_IMX8MP 0x03060301 54 55 /* CSIS common control */ 56 #define MIPI_CSIS_CMN_CTRL 0x04 57 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) 58 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) 59 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 60 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) 61 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) 62 63 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 64 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) 65 66 /* CSIS clock control */ 67 #define MIPI_CSIS_CLK_CTRL 0x08 68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) 69 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) 70 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) 71 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) 72 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) 73 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) 74 75 /* CSIS Interrupt mask */ 76 #define MIPI_CSIS_INT_MSK 0x10 77 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 78 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 79 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 80 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 81 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 82 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 83 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 84 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 85 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 86 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 87 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 88 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 89 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 90 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) 91 92 /* CSIS Interrupt source */ 93 #define MIPI_CSIS_INT_SRC 0x14 94 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 95 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 96 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 97 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 98 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 99 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 100 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 101 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) 102 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) 103 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) 104 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) 105 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) 106 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) 107 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 108 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 109 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 110 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) 111 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 112 113 /* D-PHY status control */ 114 #define MIPI_CSIS_DPHY_STATUS 0x20 115 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 116 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 117 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 118 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 119 120 /* D-PHY common control */ 121 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 122 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 125 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 126 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) 127 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) 128 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 129 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 130 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 131 132 /* D-PHY Master and Slave Control register Low */ 133 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 134 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 135 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 136 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 137 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 138 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 139 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 140 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 141 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 143 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 144 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 145 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 146 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 150 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 151 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 153 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 154 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 156 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 157 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 158 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 159 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 160 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 161 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 162 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 163 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 164 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 165 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 166 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 167 168 /* D-PHY Master and Slave Control register High */ 169 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 170 /* D-PHY Slave Control register Low */ 171 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 172 /* D-PHY Slave Control register High */ 173 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 174 175 /* ISP Configuration register */ 176 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 177 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) 178 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 179 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 180 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 181 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 182 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) 183 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) 184 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) 185 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) 186 187 /* ISP Image Resolution register */ 188 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 189 #define CSIS_MAX_PIX_WIDTH 0xffff 190 #define CSIS_MAX_PIX_HEIGHT 0xffff 191 192 /* ISP SYNC register */ 193 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 194 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 195 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 196 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 197 198 /* ISP shadow registers */ 199 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 200 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 201 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 202 203 /* Debug control register */ 204 #define MIPI_CSIS_DBG_CTRL 0xc0 205 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 206 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 207 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 208 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) 209 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) 210 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) 211 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) 212 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) 213 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) 214 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 215 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 216 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 217 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) 218 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) 219 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) 220 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) 221 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) 222 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) 223 224 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 225 226 /* Non-image packet data buffers */ 227 #define MIPI_CSIS_PKTDATA_ODD 0x2000 228 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 229 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 230 231 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL 232 233 struct mipi_csis_event { 234 bool debug; 235 u32 mask; 236 const char * const name; 237 unsigned int counter; 238 }; 239 240 static const struct mipi_csis_event mipi_csis_events[] = { 241 /* Errors */ 242 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, 243 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, 244 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, 245 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, 246 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 247 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 248 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 249 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, 250 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 251 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 252 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, 253 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, 254 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, 255 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, 256 /* Non-image data receive events */ 257 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 258 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 259 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 260 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 261 /* Frame start/end */ 262 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, 263 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, 264 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, 265 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, 266 }; 267 268 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 269 270 enum mipi_csis_clk { 271 MIPI_CSIS_CLK_PCLK, 272 MIPI_CSIS_CLK_WRAP, 273 MIPI_CSIS_CLK_PHY, 274 MIPI_CSIS_CLK_AXI, 275 }; 276 277 static const char * const mipi_csis_clk_id[] = { 278 "pclk", 279 "wrap", 280 "phy", 281 "axi", 282 }; 283 284 enum mipi_csis_version { 285 MIPI_CSIS_V3_3, 286 MIPI_CSIS_V3_6_3, 287 }; 288 289 struct mipi_csis_info { 290 enum mipi_csis_version version; 291 unsigned int num_clocks; 292 }; 293 294 struct mipi_csis_device { 295 struct device *dev; 296 void __iomem *regs; 297 struct clk_bulk_data *clks; 298 struct reset_control *mrst; 299 struct regulator *mipi_phy_regulator; 300 const struct mipi_csis_info *info; 301 302 struct v4l2_subdev sd; 303 struct media_pad pads[CSIS_PADS_NUM]; 304 struct v4l2_async_notifier notifier; 305 306 struct { 307 struct v4l2_subdev *sd; 308 const struct media_pad *pad; 309 } source; 310 311 struct v4l2_mbus_config_mipi_csi2 bus; 312 u32 clk_frequency; 313 u32 hs_settle; 314 u32 clk_settle; 315 316 spinlock_t slock; /* Protect events */ 317 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 318 struct dentry *debugfs_root; 319 struct { 320 bool enable; 321 u32 hs_settle; 322 u32 clk_settle; 323 } debug; 324 }; 325 326 /* ----------------------------------------------------------------------------- 327 * Format helpers 328 */ 329 330 struct csis_pix_format { 331 u32 code; 332 u32 output; 333 u32 data_type; 334 u8 width; 335 }; 336 337 static const struct csis_pix_format mipi_csis_formats[] = { 338 /* YUV formats. */ 339 { 340 .code = MEDIA_BUS_FMT_UYVY8_1X16, 341 .output = MEDIA_BUS_FMT_UYVY8_1X16, 342 .data_type = MIPI_CSI2_DT_YUV422_8B, 343 .width = 16, 344 }, 345 /* RGB formats. */ 346 { 347 .code = MEDIA_BUS_FMT_RGB565_1X16, 348 .output = MEDIA_BUS_FMT_RGB565_1X16, 349 .data_type = MIPI_CSI2_DT_RGB565, 350 .width = 16, 351 }, { 352 .code = MEDIA_BUS_FMT_BGR888_1X24, 353 .output = MEDIA_BUS_FMT_RGB888_1X24, 354 .data_type = MIPI_CSI2_DT_RGB888, 355 .width = 24, 356 }, 357 /* RAW (Bayer and greyscale) formats. */ 358 { 359 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 360 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 361 .data_type = MIPI_CSI2_DT_RAW8, 362 .width = 8, 363 }, { 364 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 365 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 366 .data_type = MIPI_CSI2_DT_RAW8, 367 .width = 8, 368 }, { 369 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 370 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 371 .data_type = MIPI_CSI2_DT_RAW8, 372 .width = 8, 373 }, { 374 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 375 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 376 .data_type = MIPI_CSI2_DT_RAW8, 377 .width = 8, 378 }, { 379 .code = MEDIA_BUS_FMT_Y8_1X8, 380 .output = MEDIA_BUS_FMT_Y8_1X8, 381 .data_type = MIPI_CSI2_DT_RAW8, 382 .width = 8, 383 }, { 384 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 385 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 386 .data_type = MIPI_CSI2_DT_RAW10, 387 .width = 10, 388 }, { 389 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 390 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 391 .data_type = MIPI_CSI2_DT_RAW10, 392 .width = 10, 393 }, { 394 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 395 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 396 .data_type = MIPI_CSI2_DT_RAW10, 397 .width = 10, 398 }, { 399 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 400 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 401 .data_type = MIPI_CSI2_DT_RAW10, 402 .width = 10, 403 }, { 404 .code = MEDIA_BUS_FMT_Y10_1X10, 405 .output = MEDIA_BUS_FMT_Y10_1X10, 406 .data_type = MIPI_CSI2_DT_RAW10, 407 .width = 10, 408 }, { 409 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 410 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 411 .data_type = MIPI_CSI2_DT_RAW12, 412 .width = 12, 413 }, { 414 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 415 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 416 .data_type = MIPI_CSI2_DT_RAW12, 417 .width = 12, 418 }, { 419 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 420 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 421 .data_type = MIPI_CSI2_DT_RAW12, 422 .width = 12, 423 }, { 424 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 425 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 426 .data_type = MIPI_CSI2_DT_RAW12, 427 .width = 12, 428 }, { 429 .code = MEDIA_BUS_FMT_Y12_1X12, 430 .output = MEDIA_BUS_FMT_Y12_1X12, 431 .data_type = MIPI_CSI2_DT_RAW12, 432 .width = 12, 433 }, { 434 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 435 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 436 .data_type = MIPI_CSI2_DT_RAW14, 437 .width = 14, 438 }, { 439 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 440 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 441 .data_type = MIPI_CSI2_DT_RAW14, 442 .width = 14, 443 }, { 444 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 445 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 446 .data_type = MIPI_CSI2_DT_RAW14, 447 .width = 14, 448 }, { 449 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 450 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 451 .data_type = MIPI_CSI2_DT_RAW14, 452 .width = 14, 453 }, 454 /* JPEG */ 455 { 456 .code = MEDIA_BUS_FMT_JPEG_1X8, 457 .output = MEDIA_BUS_FMT_JPEG_1X8, 458 /* 459 * Map JPEG_1X8 to the RAW8 datatype. 460 * 461 * The CSI-2 specification suggests in Annex A "JPEG8 Data 462 * Format (informative)" to transmit JPEG data using one of the 463 * Data Types aimed to represent arbitrary data, such as the 464 * "User Defined Data Type 1" (0x30). 465 * 466 * However, when configured with a User Defined Data Type, the 467 * CSIS outputs data in quad pixel mode regardless of the mode 468 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 469 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 470 * or ISI) support quad pixel mode, so this will never work in 471 * practice. 472 * 473 * Some sensors (such as the OV5640) send JPEG data using the 474 * RAW8 data type. This is usable and works, so map the JPEG 475 * format to RAW8. If the CSIS ends up being integrated in an 476 * SoC that can support quad pixel mode, this will have to be 477 * revisited. 478 */ 479 .data_type = MIPI_CSI2_DT_RAW8, 480 .width = 8, 481 } 482 }; 483 484 static const struct csis_pix_format *find_csis_format(u32 code) 485 { 486 unsigned int i; 487 488 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 489 if (code == mipi_csis_formats[i].code) 490 return &mipi_csis_formats[i]; 491 return NULL; 492 } 493 494 /* ----------------------------------------------------------------------------- 495 * Hardware configuration 496 */ 497 498 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 499 { 500 return readl(csis->regs + reg); 501 } 502 503 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 504 u32 val) 505 { 506 writel(val, csis->regs + reg); 507 } 508 509 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 510 { 511 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 512 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 513 } 514 515 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 516 { 517 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 518 519 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 520 val | MIPI_CSIS_CMN_CTRL_RESET); 521 usleep_range(10, 20); 522 } 523 524 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 525 { 526 u32 val, mask; 527 528 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 529 if (on) 530 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 531 else 532 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 533 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 534 535 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 536 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 537 if (on) { 538 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 539 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 540 } 541 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 542 } 543 544 static void __mipi_csis_set_format(struct mipi_csis_device *csis, 545 const struct v4l2_mbus_framefmt *format, 546 const struct csis_pix_format *csis_fmt) 547 { 548 u32 val; 549 550 /* Color format */ 551 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 552 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 553 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 554 555 /* 556 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 557 * (referred to in the documentation as single and dual pixel modes 558 * respectively, although the 8-bit mode transfers half a pixel per 559 * clock sample and the 16-bit mode one pixel). While both mode work 560 * when the CSIS is connected to a receiver that supports either option, 561 * single pixel mode requires clock rates twice as high. As all SoCs 562 * that integrate the CSIS can operate in 16-bit bit mode, and some do 563 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 564 * pixel mode unconditionally. 565 * 566 * TODO: Verify which other formats require DUAL (or QUAD) modes. 567 */ 568 if (csis_fmt->data_type == MIPI_CSI2_DT_YUV422_8B) 569 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 570 571 val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type); 572 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 573 574 /* Pixel resolution */ 575 val = format->width | (format->height << 16); 576 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 577 } 578 579 static int mipi_csis_calculate_params(struct mipi_csis_device *csis, 580 const struct csis_pix_format *csis_fmt) 581 { 582 struct media_pad *src_pad = 583 &csis->source.sd->entity.pads[csis->source.pad->index]; 584 s64 link_freq; 585 u32 lane_rate; 586 587 /* Calculate the line rate from the pixel rate. */ 588 link_freq = v4l2_get_link_freq(src_pad, csis_fmt->width, 589 csis->bus.num_data_lanes * 2); 590 if (link_freq < 0) { 591 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 592 (int)link_freq); 593 return link_freq; 594 } 595 596 lane_rate = link_freq * 2; 597 598 if (lane_rate < 80000000 || lane_rate > 1500000000) { 599 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 600 return -EINVAL; 601 } 602 603 /* 604 * The HSSETTLE counter value is document in a table, but can also 605 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 606 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 607 * we figure out how to compute it correctly. 608 */ 609 csis->hs_settle = (lane_rate - 5000000) / 45000000; 610 csis->clk_settle = 0; 611 612 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 613 lane_rate, csis->clk_settle, csis->hs_settle); 614 615 if (csis->debug.hs_settle < 0xff) { 616 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 617 csis->debug.hs_settle); 618 csis->hs_settle = csis->debug.hs_settle; 619 } 620 621 if (csis->debug.clk_settle < 4) { 622 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 623 csis->debug.clk_settle); 624 csis->clk_settle = csis->debug.clk_settle; 625 } 626 627 return 0; 628 } 629 630 static void mipi_csis_set_params(struct mipi_csis_device *csis, 631 const struct v4l2_mbus_framefmt *format, 632 const struct csis_pix_format *csis_fmt) 633 { 634 int lanes = csis->bus.num_data_lanes; 635 u32 val; 636 637 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 638 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 639 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 640 if (csis->info->version == MIPI_CSIS_V3_3) 641 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 642 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 643 644 __mipi_csis_set_format(csis, format, csis_fmt); 645 646 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 647 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 648 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 649 650 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 651 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 652 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 653 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 654 655 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 656 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 657 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 658 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 659 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 660 661 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 662 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 663 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 664 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 665 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 666 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 667 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 668 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 669 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 670 671 /* Update the shadow register. */ 672 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 673 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 674 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 675 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 676 } 677 678 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 679 { 680 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 681 } 682 683 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 684 { 685 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 686 } 687 688 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 689 { 690 unsigned int i; 691 int ret; 692 693 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 694 sizeof(*csis->clks), GFP_KERNEL); 695 696 if (!csis->clks) 697 return -ENOMEM; 698 699 for (i = 0; i < csis->info->num_clocks; i++) 700 csis->clks[i].id = mipi_csis_clk_id[i]; 701 702 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 703 csis->clks); 704 if (ret < 0) 705 return ret; 706 707 /* Set clock rate */ 708 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 709 csis->clk_frequency); 710 if (ret < 0) 711 dev_err(csis->dev, "set rate=%d failed: %d\n", 712 csis->clk_frequency, ret); 713 714 return ret; 715 } 716 717 static void mipi_csis_start_stream(struct mipi_csis_device *csis, 718 const struct v4l2_mbus_framefmt *format, 719 const struct csis_pix_format *csis_fmt) 720 { 721 mipi_csis_sw_reset(csis); 722 mipi_csis_set_params(csis, format, csis_fmt); 723 mipi_csis_system_enable(csis, true); 724 mipi_csis_enable_interrupts(csis, true); 725 } 726 727 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 728 { 729 mipi_csis_enable_interrupts(csis, false); 730 mipi_csis_system_enable(csis, false); 731 } 732 733 static void mipi_csis_queue_event_sof(struct mipi_csis_device *csis) 734 { 735 struct v4l2_event event = { 736 .type = V4L2_EVENT_FRAME_SYNC, 737 }; 738 u32 frame; 739 740 frame = mipi_csis_read(csis, MIPI_CSIS_FRAME_COUNTER_CH(0)); 741 event.u.frame_sync.frame_sequence = frame; 742 v4l2_event_queue(csis->sd.devnode, &event); 743 } 744 745 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 746 { 747 struct mipi_csis_device *csis = dev_id; 748 unsigned long flags; 749 unsigned int i; 750 u32 status; 751 u32 dbg_status; 752 753 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 754 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 755 756 spin_lock_irqsave(&csis->slock, flags); 757 758 /* Update the event/error counters */ 759 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 760 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 761 struct mipi_csis_event *event = &csis->events[i]; 762 763 if ((!event->debug && (status & event->mask)) || 764 (event->debug && (dbg_status & event->mask))) 765 event->counter++; 766 } 767 } 768 769 if (status & MIPI_CSIS_INT_SRC_FRAME_START) 770 mipi_csis_queue_event_sof(csis); 771 772 spin_unlock_irqrestore(&csis->slock, flags); 773 774 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 775 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 776 777 return IRQ_HANDLED; 778 } 779 780 /* ----------------------------------------------------------------------------- 781 * PHY regulator and reset 782 */ 783 784 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 785 { 786 if (csis->info->version != MIPI_CSIS_V3_3) 787 return 0; 788 789 return regulator_enable(csis->mipi_phy_regulator); 790 } 791 792 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 793 { 794 if (csis->info->version != MIPI_CSIS_V3_3) 795 return 0; 796 797 return regulator_disable(csis->mipi_phy_regulator); 798 } 799 800 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 801 { 802 if (csis->info->version != MIPI_CSIS_V3_3) 803 return; 804 805 reset_control_assert(csis->mrst); 806 msleep(20); 807 reset_control_deassert(csis->mrst); 808 } 809 810 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 811 { 812 if (csis->info->version != MIPI_CSIS_V3_3) 813 return 0; 814 815 /* Get MIPI PHY reset and regulator. */ 816 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 817 if (IS_ERR(csis->mrst)) 818 return PTR_ERR(csis->mrst); 819 820 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 821 if (IS_ERR(csis->mipi_phy_regulator)) 822 return PTR_ERR(csis->mipi_phy_regulator); 823 824 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 825 1000000); 826 } 827 828 /* ----------------------------------------------------------------------------- 829 * Debug 830 */ 831 832 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 833 { 834 unsigned long flags; 835 unsigned int i; 836 837 spin_lock_irqsave(&csis->slock, flags); 838 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 839 csis->events[i].counter = 0; 840 spin_unlock_irqrestore(&csis->slock, flags); 841 } 842 843 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 844 { 845 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 846 : MIPI_CSIS_NUM_EVENTS - 8; 847 unsigned int counters[MIPI_CSIS_NUM_EVENTS]; 848 unsigned long flags; 849 unsigned int i; 850 851 spin_lock_irqsave(&csis->slock, flags); 852 for (i = 0; i < num_events; ++i) 853 counters[i] = csis->events[i].counter; 854 spin_unlock_irqrestore(&csis->slock, flags); 855 856 for (i = 0; i < num_events; ++i) { 857 if (counters[i] > 0 || csis->debug.enable) 858 dev_info(csis->dev, "%s events: %d\n", 859 csis->events[i].name, 860 counters[i]); 861 } 862 } 863 864 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 865 { 866 static const struct { 867 u32 offset; 868 const char * const name; 869 } registers[] = { 870 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, 871 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, 872 { MIPI_CSIS_INT_MSK, "INT_MSK" }, 873 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, 874 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, 875 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, 876 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, 877 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, 878 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, 879 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, 880 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, 881 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, 882 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, 883 }; 884 885 unsigned int i; 886 u32 cfg; 887 888 if (!pm_runtime_get_if_in_use(csis->dev)) 889 return 0; 890 891 dev_info(csis->dev, "--- REGISTERS ---\n"); 892 893 for (i = 0; i < ARRAY_SIZE(registers); i++) { 894 cfg = mipi_csis_read(csis, registers[i].offset); 895 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 896 } 897 898 pm_runtime_put(csis->dev); 899 900 return 0; 901 } 902 903 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 904 { 905 struct mipi_csis_device *csis = m->private; 906 907 return mipi_csis_dump_regs(csis); 908 } 909 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 910 911 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 912 { 913 csis->debug.hs_settle = UINT_MAX; 914 csis->debug.clk_settle = UINT_MAX; 915 916 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 917 918 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 919 &csis->debug.enable); 920 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 921 &mipi_csis_dump_regs_fops); 922 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 923 &csis->debug.clk_settle); 924 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 925 &csis->debug.hs_settle); 926 } 927 928 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 929 { 930 debugfs_remove_recursive(csis->debugfs_root); 931 } 932 933 /* ----------------------------------------------------------------------------- 934 * V4L2 subdev operations 935 */ 936 937 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 938 { 939 return container_of(sdev, struct mipi_csis_device, sd); 940 } 941 942 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 943 { 944 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 945 const struct v4l2_mbus_framefmt *format; 946 const struct csis_pix_format *csis_fmt; 947 struct v4l2_subdev_state *state; 948 int ret; 949 950 if (!enable) { 951 v4l2_subdev_disable_streams(csis->source.sd, 952 csis->source.pad->index, BIT(0)); 953 954 mipi_csis_stop_stream(csis); 955 if (csis->debug.enable) 956 mipi_csis_log_counters(csis, true); 957 958 pm_runtime_put(csis->dev); 959 960 return 0; 961 } 962 963 state = v4l2_subdev_lock_and_get_active_state(sd); 964 965 format = v4l2_subdev_state_get_format(state, CSIS_PAD_SINK); 966 csis_fmt = find_csis_format(format->code); 967 968 ret = mipi_csis_calculate_params(csis, csis_fmt); 969 if (ret < 0) 970 goto err_unlock; 971 972 mipi_csis_clear_counters(csis); 973 974 ret = pm_runtime_resume_and_get(csis->dev); 975 if (ret < 0) 976 goto err_unlock; 977 978 mipi_csis_start_stream(csis, format, csis_fmt); 979 980 ret = v4l2_subdev_enable_streams(csis->source.sd, 981 csis->source.pad->index, BIT(0)); 982 if (ret < 0) 983 goto err_stop; 984 985 mipi_csis_log_counters(csis, true); 986 987 v4l2_subdev_unlock_state(state); 988 989 return 0; 990 991 err_stop: 992 mipi_csis_stop_stream(csis); 993 pm_runtime_put(csis->dev); 994 err_unlock: 995 v4l2_subdev_unlock_state(state); 996 997 return ret; 998 } 999 1000 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 1001 struct v4l2_subdev_state *sd_state, 1002 struct v4l2_subdev_mbus_code_enum *code) 1003 { 1004 /* 1005 * The CSIS can't transcode in any way, the source format is identical 1006 * to the sink format. 1007 */ 1008 if (code->pad == CSIS_PAD_SOURCE) { 1009 struct v4l2_mbus_framefmt *fmt; 1010 1011 if (code->index > 0) 1012 return -EINVAL; 1013 1014 fmt = v4l2_subdev_state_get_format(sd_state, code->pad); 1015 code->code = fmt->code; 1016 return 0; 1017 } 1018 1019 if (code->pad != CSIS_PAD_SINK) 1020 return -EINVAL; 1021 1022 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1023 return -EINVAL; 1024 1025 code->code = mipi_csis_formats[code->index].code; 1026 1027 return 0; 1028 } 1029 1030 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1031 struct v4l2_subdev_state *sd_state, 1032 struct v4l2_subdev_format *sdformat) 1033 { 1034 struct csis_pix_format const *csis_fmt; 1035 struct v4l2_mbus_framefmt *fmt; 1036 unsigned int align; 1037 1038 /* 1039 * The CSIS can't transcode in any way, the source format can't be 1040 * modified. 1041 */ 1042 if (sdformat->pad == CSIS_PAD_SOURCE) 1043 return v4l2_subdev_get_fmt(sd, sd_state, sdformat); 1044 1045 if (sdformat->pad != CSIS_PAD_SINK) 1046 return -EINVAL; 1047 1048 /* 1049 * Validate the media bus code and clamp and align the size. 1050 * 1051 * The total number of bits per line must be a multiple of 8. We thus 1052 * need to align the width for formats that are not multiples of 8 1053 * bits. 1054 */ 1055 csis_fmt = find_csis_format(sdformat->format.code); 1056 if (!csis_fmt) 1057 csis_fmt = &mipi_csis_formats[0]; 1058 1059 switch (csis_fmt->width % 8) { 1060 case 0: 1061 align = 0; 1062 break; 1063 case 4: 1064 align = 1; 1065 break; 1066 case 2: 1067 case 6: 1068 align = 2; 1069 break; 1070 default: 1071 /* 1, 3, 5, 7 */ 1072 align = 3; 1073 break; 1074 } 1075 1076 v4l_bound_align_image(&sdformat->format.width, 1, 1077 CSIS_MAX_PIX_WIDTH, align, 1078 &sdformat->format.height, 1, 1079 CSIS_MAX_PIX_HEIGHT, 0, 0); 1080 1081 fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad); 1082 1083 fmt->code = csis_fmt->code; 1084 fmt->width = sdformat->format.width; 1085 fmt->height = sdformat->format.height; 1086 fmt->field = V4L2_FIELD_NONE; 1087 fmt->colorspace = sdformat->format.colorspace; 1088 fmt->quantization = sdformat->format.quantization; 1089 fmt->xfer_func = sdformat->format.xfer_func; 1090 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1091 1092 sdformat->format = *fmt; 1093 1094 /* Propagate the format from sink to source. */ 1095 fmt = v4l2_subdev_state_get_format(sd_state, CSIS_PAD_SOURCE); 1096 *fmt = sdformat->format; 1097 1098 /* The format on the source pad might change due to unpacking. */ 1099 fmt->code = csis_fmt->output; 1100 1101 return 0; 1102 } 1103 1104 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 1105 struct v4l2_mbus_frame_desc *fd) 1106 { 1107 struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0]; 1108 const struct csis_pix_format *csis_fmt; 1109 const struct v4l2_mbus_framefmt *fmt; 1110 struct v4l2_subdev_state *state; 1111 1112 if (pad != CSIS_PAD_SOURCE) 1113 return -EINVAL; 1114 1115 state = v4l2_subdev_lock_and_get_active_state(sd); 1116 fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE); 1117 csis_fmt = find_csis_format(fmt->code); 1118 v4l2_subdev_unlock_state(state); 1119 1120 if (!csis_fmt) 1121 return -EPIPE; 1122 1123 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL; 1124 fd->num_entries = 1; 1125 1126 entry->flags = 0; 1127 entry->pixelcode = csis_fmt->code; 1128 entry->bus.csi2.vc = 0; 1129 entry->bus.csi2.dt = csis_fmt->data_type; 1130 1131 return 0; 1132 } 1133 1134 static int mipi_csis_init_state(struct v4l2_subdev *sd, 1135 struct v4l2_subdev_state *sd_state) 1136 { 1137 struct v4l2_subdev_format fmt = { 1138 .pad = CSIS_PAD_SINK, 1139 }; 1140 1141 fmt.format.code = mipi_csis_formats[0].code; 1142 fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH; 1143 fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT; 1144 1145 fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1146 fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace); 1147 fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace); 1148 fmt.format.quantization = 1149 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace, 1150 fmt.format.ycbcr_enc); 1151 1152 return mipi_csis_set_fmt(sd, sd_state, &fmt); 1153 } 1154 1155 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1156 { 1157 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1158 1159 mipi_csis_log_counters(csis, true); 1160 if (csis->debug.enable) 1161 mipi_csis_dump_regs(csis); 1162 1163 return 0; 1164 } 1165 1166 static int mipi_csis_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1167 struct v4l2_event_subscription *sub) 1168 { 1169 if (sub->type != V4L2_EVENT_FRAME_SYNC) 1170 return -EINVAL; 1171 1172 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */ 1173 if (sub->id != 0) 1174 return -EINVAL; 1175 1176 return v4l2_event_subscribe(fh, sub, 0, NULL); 1177 } 1178 1179 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1180 .log_status = mipi_csis_log_status, 1181 .subscribe_event = mipi_csis_subscribe_event, 1182 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1183 }; 1184 1185 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1186 .s_stream = mipi_csis_s_stream, 1187 }; 1188 1189 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1190 .enum_mbus_code = mipi_csis_enum_mbus_code, 1191 .get_fmt = v4l2_subdev_get_fmt, 1192 .set_fmt = mipi_csis_set_fmt, 1193 .get_frame_desc = mipi_csis_get_frame_desc, 1194 }; 1195 1196 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1197 .core = &mipi_csis_core_ops, 1198 .video = &mipi_csis_video_ops, 1199 .pad = &mipi_csis_pad_ops, 1200 }; 1201 1202 static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = { 1203 .init_state = mipi_csis_init_state, 1204 }; 1205 1206 /* ----------------------------------------------------------------------------- 1207 * Media entity operations 1208 */ 1209 1210 static int mipi_csis_link_setup(struct media_entity *entity, 1211 const struct media_pad *local_pad, 1212 const struct media_pad *remote_pad, u32 flags) 1213 { 1214 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1215 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1216 struct v4l2_subdev *remote_sd; 1217 1218 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1219 local_pad->entity->name); 1220 1221 /* We only care about the link to the source. */ 1222 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1223 return 0; 1224 1225 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1226 1227 if (flags & MEDIA_LNK_FL_ENABLED) { 1228 if (csis->source.sd) 1229 return -EBUSY; 1230 1231 csis->source.sd = remote_sd; 1232 csis->source.pad = remote_pad; 1233 } else { 1234 csis->source.sd = NULL; 1235 csis->source.pad = NULL; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static const struct media_entity_operations mipi_csis_entity_ops = { 1242 .link_setup = mipi_csis_link_setup, 1243 .link_validate = v4l2_subdev_link_validate, 1244 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1245 }; 1246 1247 /* ----------------------------------------------------------------------------- 1248 * Async subdev notifier 1249 */ 1250 1251 static struct mipi_csis_device * 1252 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1253 { 1254 return container_of(n, struct mipi_csis_device, notifier); 1255 } 1256 1257 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1258 struct v4l2_subdev *sd, 1259 struct v4l2_async_connection *asd) 1260 { 1261 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1262 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1263 1264 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1265 } 1266 1267 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1268 .bound = mipi_csis_notify_bound, 1269 }; 1270 1271 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1272 { 1273 struct v4l2_fwnode_endpoint vep = { 1274 .bus_type = V4L2_MBUS_CSI2_DPHY, 1275 }; 1276 struct v4l2_async_connection *asd; 1277 struct fwnode_handle *ep; 1278 unsigned int i; 1279 int ret; 1280 1281 v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd); 1282 1283 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1284 FWNODE_GRAPH_ENDPOINT_NEXT); 1285 if (!ep) 1286 return -ENOTCONN; 1287 1288 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1289 if (ret) 1290 goto err_parse; 1291 1292 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1293 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1294 dev_err(csis->dev, 1295 "data lanes reordering is not supported"); 1296 ret = -EINVAL; 1297 goto err_parse; 1298 } 1299 } 1300 1301 csis->bus = vep.bus.mipi_csi2; 1302 1303 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1304 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1305 1306 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1307 struct v4l2_async_connection); 1308 if (IS_ERR(asd)) { 1309 ret = PTR_ERR(asd); 1310 goto err_parse; 1311 } 1312 1313 fwnode_handle_put(ep); 1314 1315 csis->notifier.ops = &mipi_csis_notify_ops; 1316 1317 ret = v4l2_async_nf_register(&csis->notifier); 1318 if (ret) 1319 return ret; 1320 1321 return v4l2_async_register_subdev(&csis->sd); 1322 1323 err_parse: 1324 fwnode_handle_put(ep); 1325 1326 return ret; 1327 } 1328 1329 /* ----------------------------------------------------------------------------- 1330 * Suspend/resume 1331 */ 1332 1333 static int mipi_csis_runtime_suspend(struct device *dev) 1334 { 1335 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1336 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1337 int ret; 1338 1339 ret = mipi_csis_phy_disable(csis); 1340 if (ret) 1341 return -EAGAIN; 1342 1343 mipi_csis_clk_disable(csis); 1344 1345 return 0; 1346 } 1347 1348 static int mipi_csis_runtime_resume(struct device *dev) 1349 { 1350 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1351 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1352 int ret; 1353 1354 ret = mipi_csis_phy_enable(csis); 1355 if (ret) 1356 return -EAGAIN; 1357 1358 ret = mipi_csis_clk_enable(csis); 1359 if (ret) { 1360 mipi_csis_phy_disable(csis); 1361 return ret; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static const struct dev_pm_ops mipi_csis_pm_ops = { 1368 RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1369 NULL) 1370 }; 1371 1372 /* ----------------------------------------------------------------------------- 1373 * Probe/remove & platform driver 1374 */ 1375 1376 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1377 { 1378 struct v4l2_subdev *sd = &csis->sd; 1379 int ret; 1380 1381 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1382 sd->internal_ops = &mipi_csis_internal_ops; 1383 sd->owner = THIS_MODULE; 1384 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1385 dev_name(csis->dev)); 1386 1387 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1388 sd->ctrl_handler = NULL; 1389 1390 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1391 sd->entity.ops = &mipi_csis_entity_ops; 1392 1393 sd->dev = csis->dev; 1394 1395 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1396 | MEDIA_PAD_FL_MUST_CONNECT; 1397 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1398 | MEDIA_PAD_FL_MUST_CONNECT; 1399 ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads); 1400 if (ret) 1401 return ret; 1402 1403 ret = v4l2_subdev_init_finalize(sd); 1404 if (ret) { 1405 media_entity_cleanup(&sd->entity); 1406 return ret; 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1413 { 1414 struct device_node *node = csis->dev->of_node; 1415 1416 if (of_property_read_u32(node, "clock-frequency", 1417 &csis->clk_frequency)) 1418 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1419 1420 return 0; 1421 } 1422 1423 static int mipi_csis_probe(struct platform_device *pdev) 1424 { 1425 struct device *dev = &pdev->dev; 1426 struct mipi_csis_device *csis; 1427 int irq; 1428 int ret; 1429 1430 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1431 if (!csis) 1432 return -ENOMEM; 1433 1434 spin_lock_init(&csis->slock); 1435 1436 csis->dev = dev; 1437 csis->info = of_device_get_match_data(dev); 1438 1439 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1440 1441 /* Parse DT properties. */ 1442 ret = mipi_csis_parse_dt(csis); 1443 if (ret < 0) { 1444 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1445 return ret; 1446 } 1447 1448 /* Acquire resources. */ 1449 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1450 if (IS_ERR(csis->regs)) 1451 return PTR_ERR(csis->regs); 1452 1453 irq = platform_get_irq(pdev, 0); 1454 if (irq < 0) 1455 return irq; 1456 1457 ret = mipi_csis_phy_init(csis); 1458 if (ret < 0) 1459 return ret; 1460 1461 ret = mipi_csis_clk_get(csis); 1462 if (ret < 0) 1463 return ret; 1464 1465 /* Reset PHY and enable the clocks. */ 1466 mipi_csis_phy_reset(csis); 1467 1468 /* Now that the hardware is initialized, request the interrupt. */ 1469 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1470 dev_name(dev), csis); 1471 if (ret) { 1472 dev_err(dev, "Interrupt request failed\n"); 1473 return ret; 1474 } 1475 1476 /* Initialize and register the subdev. */ 1477 ret = mipi_csis_subdev_init(csis); 1478 if (ret < 0) 1479 return ret; 1480 1481 platform_set_drvdata(pdev, &csis->sd); 1482 1483 ret = mipi_csis_async_register(csis); 1484 if (ret < 0) { 1485 dev_err(dev, "async register failed: %d\n", ret); 1486 goto err_cleanup; 1487 } 1488 1489 /* Initialize debugfs. */ 1490 mipi_csis_debugfs_init(csis); 1491 1492 /* Enable runtime PM. */ 1493 pm_runtime_enable(dev); 1494 if (!pm_runtime_enabled(dev)) { 1495 ret = mipi_csis_runtime_resume(dev); 1496 if (ret < 0) 1497 goto err_unregister_all; 1498 } 1499 1500 dev_info(dev, "lanes: %d, freq: %u\n", 1501 csis->bus.num_data_lanes, csis->clk_frequency); 1502 1503 return 0; 1504 1505 err_unregister_all: 1506 mipi_csis_debugfs_exit(csis); 1507 err_cleanup: 1508 v4l2_subdev_cleanup(&csis->sd); 1509 media_entity_cleanup(&csis->sd.entity); 1510 v4l2_async_nf_unregister(&csis->notifier); 1511 v4l2_async_nf_cleanup(&csis->notifier); 1512 v4l2_async_unregister_subdev(&csis->sd); 1513 1514 return ret; 1515 } 1516 1517 static void mipi_csis_remove(struct platform_device *pdev) 1518 { 1519 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1520 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1521 1522 mipi_csis_debugfs_exit(csis); 1523 v4l2_async_nf_unregister(&csis->notifier); 1524 v4l2_async_nf_cleanup(&csis->notifier); 1525 v4l2_async_unregister_subdev(&csis->sd); 1526 1527 if (!pm_runtime_enabled(&pdev->dev)) 1528 mipi_csis_runtime_suspend(&pdev->dev); 1529 1530 pm_runtime_disable(&pdev->dev); 1531 v4l2_subdev_cleanup(&csis->sd); 1532 media_entity_cleanup(&csis->sd.entity); 1533 pm_runtime_set_suspended(&pdev->dev); 1534 } 1535 1536 static const struct of_device_id mipi_csis_of_match[] = { 1537 { 1538 .compatible = "fsl,imx7-mipi-csi2", 1539 .data = &(const struct mipi_csis_info){ 1540 .version = MIPI_CSIS_V3_3, 1541 .num_clocks = 3, 1542 }, 1543 }, { 1544 .compatible = "fsl,imx8mm-mipi-csi2", 1545 .data = &(const struct mipi_csis_info){ 1546 .version = MIPI_CSIS_V3_6_3, 1547 .num_clocks = 4, 1548 }, 1549 }, 1550 { /* sentinel */ }, 1551 }; 1552 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1553 1554 static struct platform_driver mipi_csis_driver = { 1555 .probe = mipi_csis_probe, 1556 .remove = mipi_csis_remove, 1557 .driver = { 1558 .of_match_table = mipi_csis_of_match, 1559 .name = CSIS_DRIVER_NAME, 1560 .pm = pm_ptr(&mipi_csis_pm_ops), 1561 }, 1562 }; 1563 1564 module_platform_driver(mipi_csis_driver); 1565 1566 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1567 MODULE_LICENSE("GPL v2"); 1568 MODULE_ALIAS("platform:imx-mipi-csi2"); 1569