1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/spinlock.h> 30 31 #include <media/mipi-csi2.h> 32 #include <media/v4l2-common.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-event.h> 35 #include <media/v4l2-fwnode.h> 36 #include <media/v4l2-mc.h> 37 #include <media/v4l2-subdev.h> 38 39 #define CSIS_DRIVER_NAME "imx-mipi-csis" 40 41 #define CSIS_PAD_SINK 0 42 #define CSIS_PAD_SOURCE 1 43 #define CSIS_PADS_NUM 2 44 45 #define MIPI_CSIS_DEF_PIX_WIDTH 640 46 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 47 48 /* Register map definition */ 49 50 /* CSIS version */ 51 #define MIPI_CSIS_VERSION 0x00 52 #define MIPI_CSIS_VERSION_IMX7D 0x03030505 53 #define MIPI_CSIS_VERSION_IMX8MP 0x03060301 54 55 /* CSIS common control */ 56 #define MIPI_CSIS_CMN_CTRL 0x04 57 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n) BIT((n) + 16) 58 #define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT BIT(10) 59 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n) ((n) << 8) 60 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK GENMASK(9, 8) 61 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 62 #define MIPI_CSIS_CMN_CTRL_SW_RESET BIT(1) 63 #define MIPI_CSIS_CMN_CTRL_CSI_EN BIT(0) 64 65 /* CSIS clock control */ 66 #define MIPI_CSIS_CLK_CTRL 0x08 67 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(n, x) ((x) << ((n) * 4 + 16)) 68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK GENMASK(7, 4) 69 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC(n) BIT(n) 70 71 /* CSIS Interrupt mask */ 72 #define MIPI_CSIS_INT_MSK 0x10 73 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 74 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 75 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 76 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 77 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 78 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 79 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 80 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 81 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 82 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 83 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 84 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 85 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 86 #define MIPI_CSIS_INT_MSK_ERR_ID BIT(0) 87 88 /* CSIS Interrupt source */ 89 #define MIPI_CSIS_INT_SRC 0x14 90 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 91 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 92 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 93 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 94 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 95 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 96 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 97 #define MIPI_CSIS_INT_SRC_FRAME_START(n) BIT((n) + 24) 98 #define MIPI_CSIS_INT_SRC_FRAME_END(n) BIT((n) + 20) 99 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n) BIT((n) + 16) 100 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n) BIT((n) + 12) 101 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n) BIT((n) + 8) 102 #define MIPI_CSIS_INT_SRC_ERR_OVER(n) BIT((n) + 4) 103 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 104 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 105 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 106 #define MIPI_CSIS_INT_SRC_ERR_ID BIT(0) 107 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 108 109 /* D-PHY status control */ 110 #define MIPI_CSIS_DPHY_STATUS 0x20 111 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 112 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 113 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 114 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 115 116 /* D-PHY common control */ 117 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 118 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 119 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 120 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 121 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 122 #define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK BIT(6) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT BIT(5) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 125 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 126 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 127 128 /* D-PHY Master and Slave Control register Low */ 129 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 130 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 131 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 132 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 133 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 134 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 135 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 136 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 137 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 138 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 139 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 140 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 141 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 143 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 144 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 145 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 147 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 150 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 153 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 154 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 155 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 156 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 157 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 158 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 159 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 160 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 161 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 162 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 163 164 /* D-PHY Master and Slave Control register High */ 165 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 166 /* D-PHY Slave Control register Low */ 167 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 168 /* D-PHY Slave Control register High */ 169 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 170 171 /* ISP Configuration register */ 172 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 173 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MASK GENMASK(31, 24) 174 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 175 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 176 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 177 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 178 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK GENMASK(13, 12) 179 #define MIPI_CSIS_ISPCFG_PARALLEL BIT(11) 180 #define MIPI_CSIS_ISPCFG_DATAFORMAT(fmt) ((fmt) << 2) 181 #define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK GENMASK(7, 2) 182 183 /* ISP Image Resolution register */ 184 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 185 #define MIPI_CSIS_ISP_RESOL_VRESOL(n) ((n) << 16) 186 #define MIPI_CSIS_ISP_RESOL_HRESOL(n) ((n) << 0) 187 #define CSIS_MAX_PIX_WIDTH 0xffff 188 #define CSIS_MAX_PIX_HEIGHT 0xffff 189 190 /* ISP SYNC register */ 191 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 192 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(n) ((n) << 18) 193 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(n) ((n) << 12) 194 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(n) ((n) << 0) 195 196 /* ISP shadow registers */ 197 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 198 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 199 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 200 201 /* Debug control register */ 202 #define MIPI_CSIS_DBG_CTRL 0xc0 203 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 204 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 205 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 206 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n) BIT((n) + 20) 207 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n) BIT((n) + 16) 208 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n) BIT((n) + 12) 209 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n) BIT((n) + 8) 210 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n) BIT((n) + 4) 211 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n) BIT((n) + 0) 212 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 213 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 214 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 215 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n) BIT((n) + 20) 216 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n) BIT((n) + 16) 217 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n) BIT((n) + 12) 218 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n) BIT((n) + 8) 219 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n) BIT((n) + 4) 220 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n) BIT((n) + 0) 221 222 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 223 224 /* Non-image packet data buffers */ 225 #define MIPI_CSIS_PKTDATA_ODD 0x2000 226 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 227 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 228 229 #define MIPI_CSIS_MAX_CHANNELS 4 230 231 struct mipi_csis_event { 232 bool debug; 233 unsigned int channel; 234 u32 mask; 235 const char * const name; 236 unsigned int counter; 237 }; 238 239 static const struct mipi_csis_event mipi_csis_events[] = { 240 /* Errors */ 241 { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0), "SOT 0 Error" }, 242 { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1), "SOT 1 Error" }, 243 { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2), "SOT 2 Error" }, 244 { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3), "SOT 3 Error" }, 245 { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0), "Lost Frame Start Error 0" }, 246 { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1), "Lost Frame Start Error 1" }, 247 { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2), "Lost Frame Start Error 2" }, 248 { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3), "Lost Frame Start Error 3" }, 249 { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0), "Lost Frame End Error 0" }, 250 { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1), "Lost Frame End Error 1" }, 251 { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2), "Lost Frame End Error 2" }, 252 { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3), "Lost Frame End Error 3" }, 253 { false, 0, MIPI_CSIS_INT_SRC_ERR_OVER(0), "FIFO Overflow Error 0" }, 254 { false, 1, MIPI_CSIS_INT_SRC_ERR_OVER(1), "FIFO Overflow Error 1" }, 255 { false, 2, MIPI_CSIS_INT_SRC_ERR_OVER(2), "FIFO Overflow Error 2" }, 256 { false, 3, MIPI_CSIS_INT_SRC_ERR_OVER(3), "FIFO Overflow Error 3" }, 257 { false, 0, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 258 { false, 0, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 259 { false, 0, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 260 { false, 0, MIPI_CSIS_INT_SRC_ERR_ID, "Unknown ID Error" }, 261 { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 262 { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 263 { true, 0, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(0), "Frame Size Error 0" }, 264 { true, 1, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(1), "Frame Size Error 1" }, 265 { true, 2, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(2), "Frame Size Error 2" }, 266 { true, 3, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(3), "Frame Size Error 3" }, 267 { true, 0, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(0), "Truncated Frame 0" }, 268 { true, 1, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(1), "Truncated Frame 1" }, 269 { true, 2, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(2), "Truncated Frame 2" }, 270 { true, 3, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(3), "Truncated Frame 3" }, 271 { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(0), "Early Frame End 0" }, 272 { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(1), "Early Frame End 1" }, 273 { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(2), "Early Frame End 2" }, 274 { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(3), "Early Frame End 3" }, 275 { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(0), "Early Frame Start 0" }, 276 { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(1), "Early Frame Start 1" }, 277 { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(2), "Early Frame Start 2" }, 278 { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(3), "Early Frame Start 3" }, 279 /* Non-image data receive events */ 280 { false, 0, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 281 { false, 0, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 282 { false, 0, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 283 { false, 0, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 284 /* Frame start/end */ 285 { false, 0, MIPI_CSIS_INT_SRC_FRAME_START(0), "Frame Start 0" }, 286 { false, 1, MIPI_CSIS_INT_SRC_FRAME_START(1), "Frame Start 1" }, 287 { false, 2, MIPI_CSIS_INT_SRC_FRAME_START(2), "Frame Start 2" }, 288 { false, 3, MIPI_CSIS_INT_SRC_FRAME_START(3), "Frame Start 3" }, 289 { false, 0, MIPI_CSIS_INT_SRC_FRAME_END(0), "Frame End 0" }, 290 { false, 1, MIPI_CSIS_INT_SRC_FRAME_END(1), "Frame End 1" }, 291 { false, 2, MIPI_CSIS_INT_SRC_FRAME_END(2), "Frame End 2" }, 292 { false, 3, MIPI_CSIS_INT_SRC_FRAME_END(3), "Frame End 3" }, 293 { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(0), "VSYNC Falling Edge 0" }, 294 { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(1), "VSYNC Falling Edge 1" }, 295 { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(2), "VSYNC Falling Edge 2" }, 296 { true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(3), "VSYNC Falling Edge 3" }, 297 { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(0), "VSYNC Rising Edge 0" }, 298 { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(1), "VSYNC Rising Edge 1" }, 299 { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(2), "VSYNC Rising Edge 2" }, 300 { true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(3), "VSYNC Rising Edge 3" }, 301 }; 302 303 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 304 #define MIPI_CSIS_NUM_ERROR_EVENTS 38 305 306 enum mipi_csis_clk { 307 MIPI_CSIS_CLK_PCLK, 308 MIPI_CSIS_CLK_WRAP, 309 MIPI_CSIS_CLK_PHY, 310 MIPI_CSIS_CLK_AXI, 311 }; 312 313 static const char * const mipi_csis_clk_id[] = { 314 "pclk", 315 "wrap", 316 "phy", 317 "axi", 318 }; 319 320 enum mipi_csis_version { 321 MIPI_CSIS_V3_3, 322 MIPI_CSIS_V3_6_3, 323 }; 324 325 struct mipi_csis_info { 326 enum mipi_csis_version version; 327 unsigned int num_clocks; 328 }; 329 330 struct mipi_csis_device { 331 struct device *dev; 332 void __iomem *regs; 333 struct clk_bulk_data *clks; 334 struct reset_control *mrst; 335 struct regulator *mipi_phy_regulator; 336 337 const struct mipi_csis_info *info; 338 unsigned int num_channels; 339 340 struct v4l2_subdev sd; 341 struct media_pad pads[CSIS_PADS_NUM]; 342 struct v4l2_async_notifier notifier; 343 344 struct { 345 struct v4l2_subdev *sd; 346 const struct media_pad *pad; 347 } source; 348 349 struct v4l2_mbus_config_mipi_csi2 bus; 350 u32 clk_frequency; 351 u32 hs_settle; 352 u32 clk_settle; 353 354 spinlock_t slock; /* Protect events */ 355 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 356 struct dentry *debugfs_root; 357 struct { 358 bool enable; 359 u32 hs_settle; 360 u32 clk_settle; 361 } debug; 362 }; 363 364 /* ----------------------------------------------------------------------------- 365 * Format helpers 366 */ 367 368 struct csis_pix_format { 369 u32 code; 370 u32 output; 371 u32 data_type; 372 u8 width; 373 }; 374 375 static const struct csis_pix_format mipi_csis_formats[] = { 376 /* YUV formats. */ 377 { 378 .code = MEDIA_BUS_FMT_UYVY8_1X16, 379 .output = MEDIA_BUS_FMT_UYVY8_1X16, 380 .data_type = MIPI_CSI2_DT_YUV422_8B, 381 .width = 16, 382 }, 383 /* RGB formats. */ 384 { 385 .code = MEDIA_BUS_FMT_RGB565_1X16, 386 .output = MEDIA_BUS_FMT_RGB565_1X16, 387 .data_type = MIPI_CSI2_DT_RGB565, 388 .width = 16, 389 }, { 390 .code = MEDIA_BUS_FMT_BGR888_1X24, 391 .output = MEDIA_BUS_FMT_RGB888_1X24, 392 .data_type = MIPI_CSI2_DT_RGB888, 393 .width = 24, 394 }, 395 /* RAW (Bayer and greyscale) formats. */ 396 { 397 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 398 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 399 .data_type = MIPI_CSI2_DT_RAW8, 400 .width = 8, 401 }, { 402 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 403 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 404 .data_type = MIPI_CSI2_DT_RAW8, 405 .width = 8, 406 }, { 407 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 408 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 409 .data_type = MIPI_CSI2_DT_RAW8, 410 .width = 8, 411 }, { 412 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 413 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 414 .data_type = MIPI_CSI2_DT_RAW8, 415 .width = 8, 416 }, { 417 .code = MEDIA_BUS_FMT_Y8_1X8, 418 .output = MEDIA_BUS_FMT_Y8_1X8, 419 .data_type = MIPI_CSI2_DT_RAW8, 420 .width = 8, 421 }, { 422 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 423 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 424 .data_type = MIPI_CSI2_DT_RAW10, 425 .width = 10, 426 }, { 427 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 428 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 429 .data_type = MIPI_CSI2_DT_RAW10, 430 .width = 10, 431 }, { 432 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 433 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 434 .data_type = MIPI_CSI2_DT_RAW10, 435 .width = 10, 436 }, { 437 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 438 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 439 .data_type = MIPI_CSI2_DT_RAW10, 440 .width = 10, 441 }, { 442 .code = MEDIA_BUS_FMT_Y10_1X10, 443 .output = MEDIA_BUS_FMT_Y10_1X10, 444 .data_type = MIPI_CSI2_DT_RAW10, 445 .width = 10, 446 }, { 447 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 448 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 449 .data_type = MIPI_CSI2_DT_RAW12, 450 .width = 12, 451 }, { 452 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 453 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 454 .data_type = MIPI_CSI2_DT_RAW12, 455 .width = 12, 456 }, { 457 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 458 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 459 .data_type = MIPI_CSI2_DT_RAW12, 460 .width = 12, 461 }, { 462 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 463 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 464 .data_type = MIPI_CSI2_DT_RAW12, 465 .width = 12, 466 }, { 467 .code = MEDIA_BUS_FMT_Y12_1X12, 468 .output = MEDIA_BUS_FMT_Y12_1X12, 469 .data_type = MIPI_CSI2_DT_RAW12, 470 .width = 12, 471 }, { 472 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 473 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 474 .data_type = MIPI_CSI2_DT_RAW14, 475 .width = 14, 476 }, { 477 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 478 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 479 .data_type = MIPI_CSI2_DT_RAW14, 480 .width = 14, 481 }, { 482 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 483 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 484 .data_type = MIPI_CSI2_DT_RAW14, 485 .width = 14, 486 }, { 487 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 488 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 489 .data_type = MIPI_CSI2_DT_RAW14, 490 .width = 14, 491 }, 492 /* JPEG */ 493 { 494 .code = MEDIA_BUS_FMT_JPEG_1X8, 495 .output = MEDIA_BUS_FMT_JPEG_1X8, 496 /* 497 * Map JPEG_1X8 to the RAW8 datatype. 498 * 499 * The CSI-2 specification suggests in Annex A "JPEG8 Data 500 * Format (informative)" to transmit JPEG data using one of the 501 * Data Types aimed to represent arbitrary data, such as the 502 * "User Defined Data Type 1" (0x30). 503 * 504 * However, when configured with a User Defined Data Type, the 505 * CSIS outputs data in quad pixel mode regardless of the mode 506 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 507 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 508 * or ISI) support quad pixel mode, so this will never work in 509 * practice. 510 * 511 * Some sensors (such as the OV5640) send JPEG data using the 512 * RAW8 data type. This is usable and works, so map the JPEG 513 * format to RAW8. If the CSIS ends up being integrated in an 514 * SoC that can support quad pixel mode, this will have to be 515 * revisited. 516 */ 517 .data_type = MIPI_CSI2_DT_RAW8, 518 .width = 8, 519 } 520 }; 521 522 static const struct csis_pix_format *find_csis_format(u32 code) 523 { 524 unsigned int i; 525 526 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 527 if (code == mipi_csis_formats[i].code) 528 return &mipi_csis_formats[i]; 529 return NULL; 530 } 531 532 /* ----------------------------------------------------------------------------- 533 * Hardware configuration 534 */ 535 536 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 537 { 538 return readl(csis->regs + reg); 539 } 540 541 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 542 u32 val) 543 { 544 writel(val, csis->regs + reg); 545 } 546 547 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 548 { 549 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 550 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 551 } 552 553 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 554 { 555 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 556 557 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 558 val | MIPI_CSIS_CMN_CTRL_SW_RESET); 559 usleep_range(10, 20); 560 } 561 562 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 563 { 564 u32 val, mask; 565 566 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 567 if (on) 568 val |= MIPI_CSIS_CMN_CTRL_CSI_EN; 569 else 570 val &= ~MIPI_CSIS_CMN_CTRL_CSI_EN; 571 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 572 573 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 574 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 575 if (on) { 576 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 577 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 578 } 579 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 580 } 581 582 static void __mipi_csis_set_format(struct mipi_csis_device *csis, 583 const struct v4l2_mbus_framefmt *format, 584 const struct csis_pix_format *csis_fmt) 585 { 586 u32 val; 587 588 /* Color format */ 589 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 590 val &= ~(MIPI_CSIS_ISPCFG_PARALLEL | MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK | 591 MIPI_CSIS_ISPCFG_DATAFORMAT_MASK); 592 593 /* 594 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 595 * (referred to in the documentation as single and dual pixel modes 596 * respectively, although the 8-bit mode transfers half a pixel per 597 * clock sample and the 16-bit mode one pixel). While both mode work 598 * when the CSIS is connected to a receiver that supports either option, 599 * single pixel mode requires clock rates twice as high. As all SoCs 600 * that integrate the CSIS can operate in 16-bit bit mode, and some do 601 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 602 * pixel mode unconditionally. 603 * 604 * TODO: Verify which other formats require DUAL (or QUAD) modes. 605 */ 606 if (csis_fmt->data_type == MIPI_CSI2_DT_YUV422_8B) 607 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 608 609 val |= MIPI_CSIS_ISPCFG_DATAFORMAT(csis_fmt->data_type); 610 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 611 612 /* Pixel resolution */ 613 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), 614 MIPI_CSIS_ISP_RESOL_VRESOL(format->height) | 615 MIPI_CSIS_ISP_RESOL_HRESOL(format->width)); 616 } 617 618 static int mipi_csis_calculate_params(struct mipi_csis_device *csis, 619 const struct csis_pix_format *csis_fmt) 620 { 621 s64 link_freq; 622 u32 lane_rate; 623 624 /* Calculate the line rate from the pixel rate. */ 625 link_freq = v4l2_get_link_freq(csis->source.pad, csis_fmt->width, 626 csis->bus.num_data_lanes * 2); 627 if (link_freq < 0) { 628 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 629 (int)link_freq); 630 return link_freq; 631 } 632 633 lane_rate = link_freq * 2; 634 635 if (lane_rate < 80000000 || lane_rate > 1500000000) { 636 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 637 return -EINVAL; 638 } 639 640 /* 641 * The HSSETTLE counter value is document in a table, but can also 642 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 643 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 644 * we figure out how to compute it correctly. 645 */ 646 csis->hs_settle = (lane_rate - 5000000) / 45000000; 647 csis->clk_settle = 0; 648 649 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 650 lane_rate, csis->clk_settle, csis->hs_settle); 651 652 if (csis->debug.hs_settle < 0xff) { 653 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 654 csis->debug.hs_settle); 655 csis->hs_settle = csis->debug.hs_settle; 656 } 657 658 if (csis->debug.clk_settle < 4) { 659 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 660 csis->debug.clk_settle); 661 csis->clk_settle = csis->debug.clk_settle; 662 } 663 664 return 0; 665 } 666 667 static void mipi_csis_set_params(struct mipi_csis_device *csis, 668 const struct v4l2_mbus_framefmt *format, 669 const struct csis_pix_format *csis_fmt) 670 { 671 int lanes = csis->bus.num_data_lanes; 672 u32 val; 673 674 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 675 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK; 676 val |= MIPI_CSIS_CMN_CTRL_LANE_NUMBER(lanes - 1); 677 if (csis->info->version == MIPI_CSIS_V3_3) 678 val |= MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT; 679 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 680 681 __mipi_csis_set_format(csis, format, csis_fmt); 682 683 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 684 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 685 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 686 687 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), 688 MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(0) | 689 MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(0) | 690 MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0)); 691 692 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 693 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC(0); 694 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(0, 15); 695 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK; 696 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 697 698 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 699 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 700 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 701 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 702 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 703 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 704 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 705 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 706 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 707 708 /* Update the shadow register. */ 709 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 710 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 711 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(0) | 712 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 713 } 714 715 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 716 { 717 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 718 } 719 720 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 721 { 722 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 723 } 724 725 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 726 { 727 unsigned int i; 728 int ret; 729 730 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 731 sizeof(*csis->clks), GFP_KERNEL); 732 733 if (!csis->clks) 734 return -ENOMEM; 735 736 for (i = 0; i < csis->info->num_clocks; i++) 737 csis->clks[i].id = mipi_csis_clk_id[i]; 738 739 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 740 csis->clks); 741 if (ret < 0) 742 return ret; 743 744 if (csis->clk_frequency) { 745 /* 746 * Set the clock rate. This is deprecated, for backward 747 * compatibility with old device trees. 748 */ 749 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 750 csis->clk_frequency); 751 if (ret < 0) 752 dev_err(csis->dev, "set rate=%d failed: %d\n", 753 csis->clk_frequency, ret); 754 } 755 756 return ret; 757 } 758 759 static void mipi_csis_start_stream(struct mipi_csis_device *csis, 760 const struct v4l2_mbus_framefmt *format, 761 const struct csis_pix_format *csis_fmt) 762 { 763 mipi_csis_sw_reset(csis); 764 mipi_csis_set_params(csis, format, csis_fmt); 765 mipi_csis_system_enable(csis, true); 766 mipi_csis_enable_interrupts(csis, true); 767 } 768 769 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 770 { 771 mipi_csis_enable_interrupts(csis, false); 772 mipi_csis_system_enable(csis, false); 773 } 774 775 static void mipi_csis_queue_event_sof(struct mipi_csis_device *csis) 776 { 777 struct v4l2_event event = { 778 .type = V4L2_EVENT_FRAME_SYNC, 779 }; 780 u32 frame; 781 782 frame = mipi_csis_read(csis, MIPI_CSIS_FRAME_COUNTER_CH(0)); 783 event.u.frame_sync.frame_sequence = frame; 784 v4l2_event_queue(csis->sd.devnode, &event); 785 } 786 787 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 788 { 789 struct mipi_csis_device *csis = dev_id; 790 unsigned long flags; 791 unsigned int i; 792 u32 status; 793 u32 dbg_status; 794 795 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 796 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 797 798 spin_lock_irqsave(&csis->slock, flags); 799 800 /* Update the event/error counters */ 801 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 802 for (i = 0; i < ARRAY_SIZE(csis->events); i++) { 803 struct mipi_csis_event *event = &csis->events[i]; 804 805 if (event->channel >= csis->num_channels) 806 continue; 807 808 if ((!event->debug && (status & event->mask)) || 809 (event->debug && (dbg_status & event->mask))) 810 event->counter++; 811 } 812 } 813 814 if (status & MIPI_CSIS_INT_SRC_FRAME_START(0)) 815 mipi_csis_queue_event_sof(csis); 816 817 spin_unlock_irqrestore(&csis->slock, flags); 818 819 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 820 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 821 822 return IRQ_HANDLED; 823 } 824 825 /* ----------------------------------------------------------------------------- 826 * PHY regulator and reset 827 */ 828 829 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 830 { 831 if (csis->info->version != MIPI_CSIS_V3_3) 832 return 0; 833 834 return regulator_enable(csis->mipi_phy_regulator); 835 } 836 837 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 838 { 839 if (csis->info->version != MIPI_CSIS_V3_3) 840 return 0; 841 842 return regulator_disable(csis->mipi_phy_regulator); 843 } 844 845 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 846 { 847 if (csis->info->version != MIPI_CSIS_V3_3) 848 return; 849 850 reset_control_assert(csis->mrst); 851 msleep(20); 852 reset_control_deassert(csis->mrst); 853 } 854 855 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 856 { 857 if (csis->info->version != MIPI_CSIS_V3_3) 858 return 0; 859 860 /* Get MIPI PHY reset and regulator. */ 861 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 862 if (IS_ERR(csis->mrst)) 863 return PTR_ERR(csis->mrst); 864 865 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 866 if (IS_ERR(csis->mipi_phy_regulator)) 867 return PTR_ERR(csis->mipi_phy_regulator); 868 869 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 870 1000000); 871 } 872 873 /* ----------------------------------------------------------------------------- 874 * Debug 875 */ 876 877 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 878 { 879 unsigned long flags; 880 unsigned int i; 881 882 spin_lock_irqsave(&csis->slock, flags); 883 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 884 csis->events[i].counter = 0; 885 spin_unlock_irqrestore(&csis->slock, flags); 886 } 887 888 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 889 { 890 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 891 : MIPI_CSIS_NUM_ERROR_EVENTS; 892 unsigned int counters[MIPI_CSIS_NUM_EVENTS]; 893 unsigned long flags; 894 unsigned int i; 895 896 spin_lock_irqsave(&csis->slock, flags); 897 for (i = 0; i < num_events; ++i) 898 counters[i] = csis->events[i].counter; 899 spin_unlock_irqrestore(&csis->slock, flags); 900 901 for (i = 0; i < num_events; ++i) { 902 const struct mipi_csis_event *event = &csis->events[i]; 903 904 if (event->channel >= csis->num_channels) 905 continue; 906 907 if (counters[i] > 0 || csis->debug.enable) 908 dev_info(csis->dev, "%s events: %d\n", 909 event->name, counters[i]); 910 } 911 } 912 913 struct mipi_csis_reg_info { 914 u32 addr; 915 unsigned int offset; 916 const char * const name; 917 }; 918 919 static void mipi_csis_dump_channel_reg(struct mipi_csis_device *csis, 920 const struct mipi_csis_reg_info *reg, 921 unsigned int channel) 922 { 923 dev_info(csis->dev, "%16s%u: 0x%08x\n", reg->name, channel, 924 mipi_csis_read(csis, reg->addr + channel * reg->offset)); 925 } 926 927 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 928 { 929 static const struct mipi_csis_reg_info common_registers[] = { 930 { MIPI_CSIS_CMN_CTRL, 0, "CMN_CTRL" }, 931 { MIPI_CSIS_CLK_CTRL, 0, "CLK_CTRL" }, 932 { MIPI_CSIS_INT_MSK, 0, "INT_MSK" }, 933 { MIPI_CSIS_DPHY_STATUS, 0, "DPHY_STATUS" }, 934 { MIPI_CSIS_DPHY_CMN_CTRL, 0, "DPHY_CMN_CTRL" }, 935 { MIPI_CSIS_DPHY_SCTRL_L, 0, "DPHY_SCTRL_L" }, 936 { MIPI_CSIS_DPHY_SCTRL_H, 0, "DPHY_SCTRL_H" }, 937 { MIPI_CSIS_DBG_CTRL, 0, "DBG_CTRL" }, 938 }; 939 static const struct mipi_csis_reg_info channel_registers[] = { 940 { MIPI_CSIS_ISP_CONFIG_CH(0), 0x10, "ISP_CONFIG_CH" }, 941 { MIPI_CSIS_ISP_RESOL_CH(0), 0x10, "ISP_RESOL_CH" }, 942 { MIPI_CSIS_SDW_CONFIG_CH(0), 0x10, "SDW_CONFIG_CH" }, 943 { MIPI_CSIS_SDW_RESOL_CH(0), 0x10, "SDW_RESOL_CH" }, 944 { MIPI_CSIS_FRAME_COUNTER_CH(0), 4, "FRAME_COUNTER_CH" }, 945 }; 946 947 if (!pm_runtime_get_if_in_use(csis->dev)) 948 return 0; 949 950 dev_info(csis->dev, "--- REGISTERS ---\n"); 951 952 for (unsigned int i = 0; i < ARRAY_SIZE(common_registers); i++) { 953 const struct mipi_csis_reg_info *reg = &common_registers[i]; 954 955 dev_info(csis->dev, "%17s: 0x%08x\n", reg->name, 956 mipi_csis_read(csis, reg->addr)); 957 } 958 959 for (unsigned int chan = 0; chan < csis->num_channels; chan++) { 960 for (unsigned int i = 0; i < ARRAY_SIZE(channel_registers); ++i) 961 mipi_csis_dump_channel_reg(csis, &channel_registers[i], 962 chan); 963 } 964 965 pm_runtime_put(csis->dev); 966 967 return 0; 968 } 969 970 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 971 { 972 struct mipi_csis_device *csis = m->private; 973 974 return mipi_csis_dump_regs(csis); 975 } 976 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 977 978 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 979 { 980 csis->debug.hs_settle = UINT_MAX; 981 csis->debug.clk_settle = UINT_MAX; 982 983 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 984 985 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 986 &csis->debug.enable); 987 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 988 &mipi_csis_dump_regs_fops); 989 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 990 &csis->debug.clk_settle); 991 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 992 &csis->debug.hs_settle); 993 } 994 995 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 996 { 997 debugfs_remove_recursive(csis->debugfs_root); 998 } 999 1000 /* ----------------------------------------------------------------------------- 1001 * V4L2 subdev operations 1002 */ 1003 1004 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 1005 { 1006 return container_of(sdev, struct mipi_csis_device, sd); 1007 } 1008 1009 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 1010 { 1011 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1012 const struct v4l2_mbus_framefmt *format; 1013 const struct csis_pix_format *csis_fmt; 1014 struct v4l2_subdev_state *state; 1015 int ret; 1016 1017 if (!enable) { 1018 v4l2_subdev_disable_streams(csis->source.sd, 1019 csis->source.pad->index, BIT(0)); 1020 1021 mipi_csis_stop_stream(csis); 1022 if (csis->debug.enable) 1023 mipi_csis_log_counters(csis, true); 1024 1025 pm_runtime_put(csis->dev); 1026 1027 return 0; 1028 } 1029 1030 state = v4l2_subdev_lock_and_get_active_state(sd); 1031 1032 format = v4l2_subdev_state_get_format(state, CSIS_PAD_SINK); 1033 csis_fmt = find_csis_format(format->code); 1034 1035 ret = mipi_csis_calculate_params(csis, csis_fmt); 1036 if (ret < 0) 1037 goto err_unlock; 1038 1039 mipi_csis_clear_counters(csis); 1040 1041 ret = pm_runtime_resume_and_get(csis->dev); 1042 if (ret < 0) 1043 goto err_unlock; 1044 1045 mipi_csis_start_stream(csis, format, csis_fmt); 1046 1047 ret = v4l2_subdev_enable_streams(csis->source.sd, 1048 csis->source.pad->index, BIT(0)); 1049 if (ret < 0) 1050 goto err_stop; 1051 1052 mipi_csis_log_counters(csis, true); 1053 1054 v4l2_subdev_unlock_state(state); 1055 1056 return 0; 1057 1058 err_stop: 1059 mipi_csis_stop_stream(csis); 1060 pm_runtime_put(csis->dev); 1061 err_unlock: 1062 v4l2_subdev_unlock_state(state); 1063 1064 return ret; 1065 } 1066 1067 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 1068 struct v4l2_subdev_state *state, 1069 struct v4l2_subdev_mbus_code_enum *code) 1070 { 1071 /* 1072 * The CSIS can't transcode in any way, the source format is identical 1073 * to the sink format. 1074 */ 1075 if (code->pad == CSIS_PAD_SOURCE) { 1076 struct v4l2_mbus_framefmt *fmt; 1077 1078 if (code->index > 0) 1079 return -EINVAL; 1080 1081 fmt = v4l2_subdev_state_get_format(state, code->pad); 1082 code->code = fmt->code; 1083 return 0; 1084 } 1085 1086 if (code->pad != CSIS_PAD_SINK) 1087 return -EINVAL; 1088 1089 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1090 return -EINVAL; 1091 1092 code->code = mipi_csis_formats[code->index].code; 1093 1094 return 0; 1095 } 1096 1097 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1098 struct v4l2_subdev_state *state, 1099 struct v4l2_subdev_format *sdformat) 1100 { 1101 const struct csis_pix_format *csis_fmt; 1102 struct v4l2_mbus_framefmt *fmt; 1103 unsigned int align; 1104 1105 /* 1106 * The CSIS can't transcode in any way, the source format can't be 1107 * modified. 1108 */ 1109 if (sdformat->pad == CSIS_PAD_SOURCE) 1110 return v4l2_subdev_get_fmt(sd, state, sdformat); 1111 1112 if (sdformat->pad != CSIS_PAD_SINK) 1113 return -EINVAL; 1114 1115 /* 1116 * Validate the media bus code and clamp and align the size. 1117 * 1118 * The total number of bits per line must be a multiple of 8. We thus 1119 * need to align the width for formats that are not multiples of 8 1120 * bits. 1121 */ 1122 csis_fmt = find_csis_format(sdformat->format.code); 1123 if (!csis_fmt) 1124 csis_fmt = &mipi_csis_formats[0]; 1125 1126 switch (csis_fmt->width % 8) { 1127 case 0: 1128 align = 0; 1129 break; 1130 case 4: 1131 align = 1; 1132 break; 1133 case 2: 1134 case 6: 1135 align = 2; 1136 break; 1137 default: 1138 /* 1, 3, 5, 7 */ 1139 align = 3; 1140 break; 1141 } 1142 1143 v4l_bound_align_image(&sdformat->format.width, 1, 1144 CSIS_MAX_PIX_WIDTH, align, 1145 &sdformat->format.height, 1, 1146 CSIS_MAX_PIX_HEIGHT, 0, 0); 1147 1148 fmt = v4l2_subdev_state_get_format(state, sdformat->pad); 1149 1150 fmt->code = csis_fmt->code; 1151 fmt->width = sdformat->format.width; 1152 fmt->height = sdformat->format.height; 1153 fmt->field = V4L2_FIELD_NONE; 1154 fmt->colorspace = sdformat->format.colorspace; 1155 fmt->quantization = sdformat->format.quantization; 1156 fmt->xfer_func = sdformat->format.xfer_func; 1157 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1158 1159 sdformat->format = *fmt; 1160 1161 /* Propagate the format from sink to source. */ 1162 fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE); 1163 *fmt = sdformat->format; 1164 1165 /* The format on the source pad might change due to unpacking. */ 1166 fmt->code = csis_fmt->output; 1167 1168 return 0; 1169 } 1170 1171 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 1172 struct v4l2_mbus_frame_desc *fd) 1173 { 1174 struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0]; 1175 const struct csis_pix_format *csis_fmt; 1176 const struct v4l2_mbus_framefmt *fmt; 1177 struct v4l2_subdev_state *state; 1178 1179 if (pad != CSIS_PAD_SOURCE) 1180 return -EINVAL; 1181 1182 state = v4l2_subdev_lock_and_get_active_state(sd); 1183 fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE); 1184 csis_fmt = find_csis_format(fmt->code); 1185 v4l2_subdev_unlock_state(state); 1186 1187 if (!csis_fmt) 1188 return -EPIPE; 1189 1190 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL; 1191 fd->num_entries = 1; 1192 1193 entry->flags = 0; 1194 entry->pixelcode = csis_fmt->code; 1195 entry->bus.csi2.vc = 0; 1196 entry->bus.csi2.dt = csis_fmt->data_type; 1197 1198 return 0; 1199 } 1200 1201 static int mipi_csis_init_state(struct v4l2_subdev *sd, 1202 struct v4l2_subdev_state *state) 1203 { 1204 struct v4l2_subdev_format fmt = { 1205 .pad = CSIS_PAD_SINK, 1206 }; 1207 1208 fmt.format.code = mipi_csis_formats[0].code; 1209 fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH; 1210 fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT; 1211 1212 fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1213 fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace); 1214 fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace); 1215 fmt.format.quantization = 1216 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace, 1217 fmt.format.ycbcr_enc); 1218 1219 return mipi_csis_set_fmt(sd, state, &fmt); 1220 } 1221 1222 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1223 { 1224 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1225 1226 mipi_csis_log_counters(csis, true); 1227 if (csis->debug.enable) 1228 mipi_csis_dump_regs(csis); 1229 1230 return 0; 1231 } 1232 1233 static int mipi_csis_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1234 struct v4l2_event_subscription *sub) 1235 { 1236 if (sub->type != V4L2_EVENT_FRAME_SYNC) 1237 return -EINVAL; 1238 1239 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */ 1240 if (sub->id != 0) 1241 return -EINVAL; 1242 1243 return v4l2_event_subscribe(fh, sub, 0, NULL); 1244 } 1245 1246 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1247 .log_status = mipi_csis_log_status, 1248 .subscribe_event = mipi_csis_subscribe_event, 1249 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1250 }; 1251 1252 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1253 .s_stream = mipi_csis_s_stream, 1254 }; 1255 1256 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1257 .enum_mbus_code = mipi_csis_enum_mbus_code, 1258 .get_fmt = v4l2_subdev_get_fmt, 1259 .set_fmt = mipi_csis_set_fmt, 1260 .get_frame_desc = mipi_csis_get_frame_desc, 1261 }; 1262 1263 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1264 .core = &mipi_csis_core_ops, 1265 .video = &mipi_csis_video_ops, 1266 .pad = &mipi_csis_pad_ops, 1267 }; 1268 1269 static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = { 1270 .init_state = mipi_csis_init_state, 1271 }; 1272 1273 /* ----------------------------------------------------------------------------- 1274 * Media entity operations 1275 */ 1276 1277 static int mipi_csis_link_setup(struct media_entity *entity, 1278 const struct media_pad *local_pad, 1279 const struct media_pad *remote_pad, u32 flags) 1280 { 1281 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1282 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1283 struct v4l2_subdev *remote_sd; 1284 1285 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1286 local_pad->entity->name); 1287 1288 /* We only care about the link to the source. */ 1289 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1290 return 0; 1291 1292 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1293 1294 if (flags & MEDIA_LNK_FL_ENABLED) { 1295 if (csis->source.sd) 1296 return -EBUSY; 1297 1298 csis->source.sd = remote_sd; 1299 csis->source.pad = remote_pad; 1300 } else { 1301 csis->source.sd = NULL; 1302 csis->source.pad = NULL; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static const struct media_entity_operations mipi_csis_entity_ops = { 1309 .link_setup = mipi_csis_link_setup, 1310 .link_validate = v4l2_subdev_link_validate, 1311 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1312 }; 1313 1314 /* ----------------------------------------------------------------------------- 1315 * Async subdev notifier 1316 */ 1317 1318 static struct mipi_csis_device * 1319 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1320 { 1321 return container_of(n, struct mipi_csis_device, notifier); 1322 } 1323 1324 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1325 struct v4l2_subdev *sd, 1326 struct v4l2_async_connection *asd) 1327 { 1328 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1329 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1330 1331 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1332 } 1333 1334 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1335 .bound = mipi_csis_notify_bound, 1336 }; 1337 1338 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1339 { 1340 struct v4l2_fwnode_endpoint vep = { 1341 .bus_type = V4L2_MBUS_CSI2_DPHY, 1342 }; 1343 struct v4l2_async_connection *asd; 1344 struct fwnode_handle *ep; 1345 unsigned int i; 1346 int ret; 1347 1348 v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd); 1349 1350 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1351 FWNODE_GRAPH_ENDPOINT_NEXT); 1352 if (!ep) 1353 return -ENOTCONN; 1354 1355 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1356 if (ret) 1357 goto err_parse; 1358 1359 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1360 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1361 dev_err(csis->dev, 1362 "data lanes reordering is not supported"); 1363 ret = -EINVAL; 1364 goto err_parse; 1365 } 1366 } 1367 1368 csis->bus = vep.bus.mipi_csi2; 1369 1370 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1371 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1372 1373 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1374 struct v4l2_async_connection); 1375 if (IS_ERR(asd)) { 1376 ret = PTR_ERR(asd); 1377 goto err_parse; 1378 } 1379 1380 fwnode_handle_put(ep); 1381 1382 csis->notifier.ops = &mipi_csis_notify_ops; 1383 1384 ret = v4l2_async_nf_register(&csis->notifier); 1385 if (ret) 1386 return ret; 1387 1388 return v4l2_async_register_subdev(&csis->sd); 1389 1390 err_parse: 1391 fwnode_handle_put(ep); 1392 1393 return ret; 1394 } 1395 1396 /* ----------------------------------------------------------------------------- 1397 * Suspend/resume 1398 */ 1399 1400 static int mipi_csis_runtime_suspend(struct device *dev) 1401 { 1402 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1403 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1404 int ret; 1405 1406 ret = mipi_csis_phy_disable(csis); 1407 if (ret) 1408 return -EAGAIN; 1409 1410 mipi_csis_clk_disable(csis); 1411 1412 return 0; 1413 } 1414 1415 static int mipi_csis_runtime_resume(struct device *dev) 1416 { 1417 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1418 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1419 int ret; 1420 1421 ret = mipi_csis_phy_enable(csis); 1422 if (ret) 1423 return -EAGAIN; 1424 1425 ret = mipi_csis_clk_enable(csis); 1426 if (ret) { 1427 mipi_csis_phy_disable(csis); 1428 return ret; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static const struct dev_pm_ops mipi_csis_pm_ops = { 1435 RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1436 NULL) 1437 }; 1438 1439 /* ----------------------------------------------------------------------------- 1440 * Probe/remove & platform driver 1441 */ 1442 1443 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1444 { 1445 struct v4l2_subdev *sd = &csis->sd; 1446 int ret; 1447 1448 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1449 sd->internal_ops = &mipi_csis_internal_ops; 1450 sd->owner = THIS_MODULE; 1451 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1452 dev_name(csis->dev)); 1453 1454 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1455 sd->ctrl_handler = NULL; 1456 1457 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1458 sd->entity.ops = &mipi_csis_entity_ops; 1459 1460 sd->dev = csis->dev; 1461 1462 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1463 | MEDIA_PAD_FL_MUST_CONNECT; 1464 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1465 | MEDIA_PAD_FL_MUST_CONNECT; 1466 ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads); 1467 if (ret) 1468 return ret; 1469 1470 ret = v4l2_subdev_init_finalize(sd); 1471 if (ret) { 1472 media_entity_cleanup(&sd->entity); 1473 return ret; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1480 { 1481 struct device_node *node = csis->dev->of_node; 1482 1483 of_property_read_u32(node, "clock-frequency", &csis->clk_frequency); 1484 1485 csis->num_channels = 1; 1486 of_property_read_u32(node, "fsl,num-channels", &csis->num_channels); 1487 if (csis->num_channels < 1 || csis->num_channels > MIPI_CSIS_MAX_CHANNELS) 1488 return dev_err_probe(csis->dev, -EINVAL, 1489 "Invalid fsl,num-channels value\n"); 1490 1491 return 0; 1492 } 1493 1494 static int mipi_csis_probe(struct platform_device *pdev) 1495 { 1496 struct device *dev = &pdev->dev; 1497 struct mipi_csis_device *csis; 1498 int irq; 1499 int ret; 1500 1501 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1502 if (!csis) 1503 return -ENOMEM; 1504 1505 spin_lock_init(&csis->slock); 1506 1507 csis->dev = dev; 1508 csis->info = of_device_get_match_data(dev); 1509 1510 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1511 1512 /* Parse DT properties. */ 1513 ret = mipi_csis_parse_dt(csis); 1514 if (ret < 0) 1515 return ret; 1516 1517 /* Acquire resources. */ 1518 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1519 if (IS_ERR(csis->regs)) 1520 return PTR_ERR(csis->regs); 1521 1522 irq = platform_get_irq(pdev, 0); 1523 if (irq < 0) 1524 return irq; 1525 1526 ret = mipi_csis_phy_init(csis); 1527 if (ret < 0) 1528 return ret; 1529 1530 ret = mipi_csis_clk_get(csis); 1531 if (ret < 0) 1532 return ret; 1533 1534 /* Reset PHY and enable the clocks. */ 1535 mipi_csis_phy_reset(csis); 1536 1537 /* Now that the hardware is initialized, request the interrupt. */ 1538 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1539 dev_name(dev), csis); 1540 if (ret) { 1541 dev_err(dev, "Interrupt request failed\n"); 1542 return ret; 1543 } 1544 1545 /* Initialize and register the subdev. */ 1546 ret = mipi_csis_subdev_init(csis); 1547 if (ret < 0) 1548 return ret; 1549 1550 platform_set_drvdata(pdev, &csis->sd); 1551 1552 ret = mipi_csis_async_register(csis); 1553 if (ret < 0) { 1554 dev_err(dev, "async register failed: %d\n", ret); 1555 goto err_cleanup; 1556 } 1557 1558 /* Initialize debugfs. */ 1559 mipi_csis_debugfs_init(csis); 1560 1561 /* Enable runtime PM. */ 1562 pm_runtime_enable(dev); 1563 if (!pm_runtime_enabled(dev)) { 1564 ret = mipi_csis_runtime_resume(dev); 1565 if (ret < 0) 1566 goto err_unregister_all; 1567 } 1568 1569 dev_info(dev, "lanes: %d, freq: %u\n", 1570 csis->bus.num_data_lanes, csis->clk_frequency); 1571 1572 return 0; 1573 1574 err_unregister_all: 1575 mipi_csis_debugfs_exit(csis); 1576 err_cleanup: 1577 v4l2_subdev_cleanup(&csis->sd); 1578 media_entity_cleanup(&csis->sd.entity); 1579 v4l2_async_nf_unregister(&csis->notifier); 1580 v4l2_async_nf_cleanup(&csis->notifier); 1581 v4l2_async_unregister_subdev(&csis->sd); 1582 1583 return ret; 1584 } 1585 1586 static void mipi_csis_remove(struct platform_device *pdev) 1587 { 1588 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1589 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1590 1591 mipi_csis_debugfs_exit(csis); 1592 v4l2_async_nf_unregister(&csis->notifier); 1593 v4l2_async_nf_cleanup(&csis->notifier); 1594 v4l2_async_unregister_subdev(&csis->sd); 1595 1596 if (!pm_runtime_enabled(&pdev->dev)) 1597 mipi_csis_runtime_suspend(&pdev->dev); 1598 1599 pm_runtime_disable(&pdev->dev); 1600 v4l2_subdev_cleanup(&csis->sd); 1601 media_entity_cleanup(&csis->sd.entity); 1602 pm_runtime_set_suspended(&pdev->dev); 1603 } 1604 1605 static const struct of_device_id mipi_csis_of_match[] = { 1606 { 1607 .compatible = "fsl,imx7-mipi-csi2", 1608 .data = &(const struct mipi_csis_info){ 1609 .version = MIPI_CSIS_V3_3, 1610 .num_clocks = 3, 1611 }, 1612 }, { 1613 .compatible = "fsl,imx8mm-mipi-csi2", 1614 .data = &(const struct mipi_csis_info){ 1615 .version = MIPI_CSIS_V3_6_3, 1616 .num_clocks = 4, 1617 }, 1618 }, 1619 { /* sentinel */ }, 1620 }; 1621 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1622 1623 static struct platform_driver mipi_csis_driver = { 1624 .probe = mipi_csis_probe, 1625 .remove = mipi_csis_remove, 1626 .driver = { 1627 .of_match_table = mipi_csis_of_match, 1628 .name = CSIS_DRIVER_NAME, 1629 .pm = pm_ptr(&mipi_csis_pm_ops), 1630 }, 1631 }; 1632 1633 module_platform_driver(mipi_csis_driver); 1634 1635 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1636 MODULE_LICENSE("GPL v2"); 1637 MODULE_ALIAS("platform:imx-mipi-csi2"); 1638