1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/spinlock.h> 30 31 #include <media/v4l2-common.h> 32 #include <media/v4l2-device.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-mc.h> 36 #include <media/v4l2-subdev.h> 37 38 #define CSIS_DRIVER_NAME "imx-mipi-csis" 39 40 #define CSIS_PAD_SINK 0 41 #define CSIS_PAD_SOURCE 1 42 #define CSIS_PADS_NUM 2 43 44 #define MIPI_CSIS_DEF_PIX_WIDTH 640 45 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 46 47 /* Register map definition */ 48 49 /* CSIS version */ 50 #define MIPI_CSIS_VERSION 0x00 51 #define MIPI_CSIS_VERSION_IMX7D 0x03030505 52 #define MIPI_CSIS_VERSION_IMX8MP 0x03060301 53 54 /* CSIS common control */ 55 #define MIPI_CSIS_CMN_CTRL 0x04 56 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) 57 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) 58 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 59 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) 60 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) 61 62 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 63 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) 64 65 /* CSIS clock control */ 66 #define MIPI_CSIS_CLK_CTRL 0x08 67 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) 68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) 69 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) 70 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) 71 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) 72 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) 73 74 /* CSIS Interrupt mask */ 75 #define MIPI_CSIS_INT_MSK 0x10 76 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 77 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 78 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 79 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 80 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 81 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 82 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 83 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 84 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 85 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 86 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 87 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 88 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 89 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) 90 91 /* CSIS Interrupt source */ 92 #define MIPI_CSIS_INT_SRC 0x14 93 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 94 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 95 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 96 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 97 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 98 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 99 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 100 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) 101 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) 102 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) 103 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) 104 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) 105 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) 106 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 107 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 108 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 109 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) 110 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 111 112 /* D-PHY status control */ 113 #define MIPI_CSIS_DPHY_STATUS 0x20 114 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 115 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 116 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 117 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 118 119 /* D-PHY common control */ 120 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 121 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 122 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 125 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) 126 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) 127 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 128 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 129 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 130 131 /* D-PHY Master and Slave Control register Low */ 132 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 133 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 134 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 135 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 136 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 137 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 138 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 139 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 140 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 141 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 143 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 144 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 145 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 150 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 153 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 154 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 156 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 157 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 158 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 159 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 160 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 161 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 162 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 163 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 164 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 165 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 166 167 /* D-PHY Master and Slave Control register High */ 168 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 169 /* D-PHY Slave Control register Low */ 170 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 171 /* D-PHY Slave Control register High */ 172 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 173 174 /* ISP Configuration register */ 175 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 176 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) 177 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 178 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 179 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 180 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 181 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) 182 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) 183 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) 184 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) 185 186 /* ISP Image Resolution register */ 187 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 188 #define CSIS_MAX_PIX_WIDTH 0xffff 189 #define CSIS_MAX_PIX_HEIGHT 0xffff 190 191 /* ISP SYNC register */ 192 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 193 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 194 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 195 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 196 197 /* ISP shadow registers */ 198 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 199 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 200 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 201 202 /* Debug control register */ 203 #define MIPI_CSIS_DBG_CTRL 0xc0 204 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 205 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 206 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 207 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) 208 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) 209 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) 210 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) 211 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) 212 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) 213 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 214 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 215 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 216 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) 217 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) 218 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) 219 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) 220 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) 221 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) 222 223 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 224 225 /* Non-image packet data buffers */ 226 #define MIPI_CSIS_PKTDATA_ODD 0x2000 227 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 228 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 229 230 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL 231 232 /* MIPI CSI-2 Data Types */ 233 #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18 234 #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19 235 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a 236 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c 237 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d 238 #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e 239 #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f 240 #define MIPI_CSI2_DATA_TYPE_RGB565 0x22 241 #define MIPI_CSI2_DATA_TYPE_RGB666 0x23 242 #define MIPI_CSI2_DATA_TYPE_RGB888 0x24 243 #define MIPI_CSI2_DATA_TYPE_RAW6 0x28 244 #define MIPI_CSI2_DATA_TYPE_RAW7 0x29 245 #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a 246 #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b 247 #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c 248 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d 249 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) 250 251 struct mipi_csis_event { 252 bool debug; 253 u32 mask; 254 const char * const name; 255 unsigned int counter; 256 }; 257 258 static const struct mipi_csis_event mipi_csis_events[] = { 259 /* Errors */ 260 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, 261 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, 262 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, 263 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, 264 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 265 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 266 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 267 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, 268 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 269 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 270 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, 271 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, 272 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, 273 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, 274 /* Non-image data receive events */ 275 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 276 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 277 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 278 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 279 /* Frame start/end */ 280 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, 281 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, 282 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, 283 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, 284 }; 285 286 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 287 288 enum mipi_csis_clk { 289 MIPI_CSIS_CLK_PCLK, 290 MIPI_CSIS_CLK_WRAP, 291 MIPI_CSIS_CLK_PHY, 292 MIPI_CSIS_CLK_AXI, 293 }; 294 295 static const char * const mipi_csis_clk_id[] = { 296 "pclk", 297 "wrap", 298 "phy", 299 "axi", 300 }; 301 302 enum mipi_csis_version { 303 MIPI_CSIS_V3_3, 304 MIPI_CSIS_V3_6_3, 305 }; 306 307 struct mipi_csis_info { 308 enum mipi_csis_version version; 309 unsigned int num_clocks; 310 }; 311 312 struct mipi_csis_device { 313 struct device *dev; 314 void __iomem *regs; 315 struct clk_bulk_data *clks; 316 struct reset_control *mrst; 317 struct regulator *mipi_phy_regulator; 318 const struct mipi_csis_info *info; 319 320 struct v4l2_subdev sd; 321 struct media_pad pads[CSIS_PADS_NUM]; 322 struct v4l2_async_notifier notifier; 323 struct v4l2_subdev *src_sd; 324 325 struct v4l2_mbus_config_mipi_csi2 bus; 326 u32 clk_frequency; 327 u32 hs_settle; 328 u32 clk_settle; 329 330 spinlock_t slock; /* Protect events */ 331 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 332 struct dentry *debugfs_root; 333 struct { 334 bool enable; 335 u32 hs_settle; 336 u32 clk_settle; 337 } debug; 338 }; 339 340 /* ----------------------------------------------------------------------------- 341 * Format helpers 342 */ 343 344 struct csis_pix_format { 345 u32 code; 346 u32 output; 347 u32 data_type; 348 u8 width; 349 }; 350 351 static const struct csis_pix_format mipi_csis_formats[] = { 352 /* YUV formats. */ 353 { 354 .code = MEDIA_BUS_FMT_UYVY8_1X16, 355 .output = MEDIA_BUS_FMT_UYVY8_1X16, 356 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8, 357 .width = 16, 358 }, 359 /* RGB formats. */ 360 { 361 .code = MEDIA_BUS_FMT_RGB565_1X16, 362 .output = MEDIA_BUS_FMT_RGB565_1X16, 363 .data_type = MIPI_CSI2_DATA_TYPE_RGB565, 364 .width = 16, 365 }, { 366 .code = MEDIA_BUS_FMT_BGR888_1X24, 367 .output = MEDIA_BUS_FMT_RGB888_1X24, 368 .data_type = MIPI_CSI2_DATA_TYPE_RGB888, 369 .width = 24, 370 }, 371 /* RAW (Bayer and greyscale) formats. */ 372 { 373 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 374 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 375 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 376 .width = 8, 377 }, { 378 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 379 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 380 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 381 .width = 8, 382 }, { 383 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 384 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 385 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 386 .width = 8, 387 }, { 388 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 389 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 390 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 391 .width = 8, 392 }, { 393 .code = MEDIA_BUS_FMT_Y8_1X8, 394 .output = MEDIA_BUS_FMT_Y8_1X8, 395 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 396 .width = 8, 397 }, { 398 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 399 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 400 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 401 .width = 10, 402 }, { 403 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 404 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 405 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 406 .width = 10, 407 }, { 408 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 409 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 410 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 411 .width = 10, 412 }, { 413 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 414 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 415 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 416 .width = 10, 417 }, { 418 .code = MEDIA_BUS_FMT_Y10_1X10, 419 .output = MEDIA_BUS_FMT_Y10_1X10, 420 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 421 .width = 10, 422 }, { 423 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 424 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 425 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 426 .width = 12, 427 }, { 428 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 429 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 430 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 431 .width = 12, 432 }, { 433 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 434 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 435 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 436 .width = 12, 437 }, { 438 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 439 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 440 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 441 .width = 12, 442 }, { 443 .code = MEDIA_BUS_FMT_Y12_1X12, 444 .output = MEDIA_BUS_FMT_Y12_1X12, 445 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 446 .width = 12, 447 }, { 448 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 449 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 450 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 451 .width = 14, 452 }, { 453 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 454 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 455 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 456 .width = 14, 457 }, { 458 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 459 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 460 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 461 .width = 14, 462 }, { 463 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 464 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 465 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 466 .width = 14, 467 }, 468 /* JPEG */ 469 { 470 .code = MEDIA_BUS_FMT_JPEG_1X8, 471 .output = MEDIA_BUS_FMT_JPEG_1X8, 472 /* 473 * Map JPEG_1X8 to the RAW8 datatype. 474 * 475 * The CSI-2 specification suggests in Annex A "JPEG8 Data 476 * Format (informative)" to transmit JPEG data using one of the 477 * Data Types aimed to represent arbitrary data, such as the 478 * "User Defined Data Type 1" (0x30). 479 * 480 * However, when configured with a User Defined Data Type, the 481 * CSIS outputs data in quad pixel mode regardless of the mode 482 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 483 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 484 * or ISI) support quad pixel mode, so this will never work in 485 * practice. 486 * 487 * Some sensors (such as the OV5640) send JPEG data using the 488 * RAW8 data type. This is usable and works, so map the JPEG 489 * format to RAW8. If the CSIS ends up being integrated in an 490 * SoC that can support quad pixel mode, this will have to be 491 * revisited. 492 */ 493 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 494 .width = 8, 495 } 496 }; 497 498 static const struct csis_pix_format *find_csis_format(u32 code) 499 { 500 unsigned int i; 501 502 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 503 if (code == mipi_csis_formats[i].code) 504 return &mipi_csis_formats[i]; 505 return NULL; 506 } 507 508 /* ----------------------------------------------------------------------------- 509 * Hardware configuration 510 */ 511 512 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 513 { 514 return readl(csis->regs + reg); 515 } 516 517 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 518 u32 val) 519 { 520 writel(val, csis->regs + reg); 521 } 522 523 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 524 { 525 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 526 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 527 } 528 529 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 530 { 531 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 532 533 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 534 val | MIPI_CSIS_CMN_CTRL_RESET); 535 usleep_range(10, 20); 536 } 537 538 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 539 { 540 u32 val, mask; 541 542 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 543 if (on) 544 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 545 else 546 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 547 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 548 549 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 550 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 551 if (on) { 552 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 553 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 554 } 555 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 556 } 557 558 static void __mipi_csis_set_format(struct mipi_csis_device *csis, 559 const struct v4l2_mbus_framefmt *format, 560 const struct csis_pix_format *csis_fmt) 561 { 562 u32 val; 563 564 /* Color format */ 565 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 566 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 567 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 568 569 /* 570 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 571 * (referred to in the documentation as single and dual pixel modes 572 * respectively, although the 8-bit mode transfers half a pixel per 573 * clock sample and the 16-bit mode one pixel). While both mode work 574 * when the CSIS is connected to a receiver that supports either option, 575 * single pixel mode requires clock rates twice as high. As all SoCs 576 * that integrate the CSIS can operate in 16-bit bit mode, and some do 577 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 578 * pixel mode unconditionally. 579 * 580 * TODO: Verify which other formats require DUAL (or QUAD) modes. 581 */ 582 if (csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 583 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 584 585 val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type); 586 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 587 588 /* Pixel resolution */ 589 val = format->width | (format->height << 16); 590 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 591 } 592 593 static int mipi_csis_calculate_params(struct mipi_csis_device *csis, 594 const struct csis_pix_format *csis_fmt) 595 { 596 s64 link_freq; 597 u32 lane_rate; 598 599 /* Calculate the line rate from the pixel rate. */ 600 link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler, 601 csis_fmt->width, 602 csis->bus.num_data_lanes * 2); 603 if (link_freq < 0) { 604 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 605 (int)link_freq); 606 return link_freq; 607 } 608 609 lane_rate = link_freq * 2; 610 611 if (lane_rate < 80000000 || lane_rate > 1500000000) { 612 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 613 return -EINVAL; 614 } 615 616 /* 617 * The HSSETTLE counter value is document in a table, but can also 618 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 619 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 620 * we figure out how to compute it correctly. 621 */ 622 csis->hs_settle = (lane_rate - 5000000) / 45000000; 623 csis->clk_settle = 0; 624 625 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 626 lane_rate, csis->clk_settle, csis->hs_settle); 627 628 if (csis->debug.hs_settle < 0xff) { 629 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 630 csis->debug.hs_settle); 631 csis->hs_settle = csis->debug.hs_settle; 632 } 633 634 if (csis->debug.clk_settle < 4) { 635 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 636 csis->debug.clk_settle); 637 csis->clk_settle = csis->debug.clk_settle; 638 } 639 640 return 0; 641 } 642 643 static void mipi_csis_set_params(struct mipi_csis_device *csis, 644 const struct v4l2_mbus_framefmt *format, 645 const struct csis_pix_format *csis_fmt) 646 { 647 int lanes = csis->bus.num_data_lanes; 648 u32 val; 649 650 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 651 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 652 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 653 if (csis->info->version == MIPI_CSIS_V3_3) 654 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 655 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 656 657 __mipi_csis_set_format(csis, format, csis_fmt); 658 659 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 660 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 661 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 662 663 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 664 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 665 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 666 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 667 668 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 669 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 670 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 671 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 672 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 673 674 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 675 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 676 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 677 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 678 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 679 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 680 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 681 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 682 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 683 684 /* Update the shadow register. */ 685 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 686 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 687 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 688 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 689 } 690 691 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 692 { 693 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 694 } 695 696 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 697 { 698 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 699 } 700 701 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 702 { 703 unsigned int i; 704 int ret; 705 706 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 707 sizeof(*csis->clks), GFP_KERNEL); 708 709 if (!csis->clks) 710 return -ENOMEM; 711 712 for (i = 0; i < csis->info->num_clocks; i++) 713 csis->clks[i].id = mipi_csis_clk_id[i]; 714 715 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 716 csis->clks); 717 if (ret < 0) 718 return ret; 719 720 /* Set clock rate */ 721 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 722 csis->clk_frequency); 723 if (ret < 0) 724 dev_err(csis->dev, "set rate=%d failed: %d\n", 725 csis->clk_frequency, ret); 726 727 return ret; 728 } 729 730 static void mipi_csis_start_stream(struct mipi_csis_device *csis, 731 const struct v4l2_mbus_framefmt *format, 732 const struct csis_pix_format *csis_fmt) 733 { 734 mipi_csis_sw_reset(csis); 735 mipi_csis_set_params(csis, format, csis_fmt); 736 mipi_csis_system_enable(csis, true); 737 mipi_csis_enable_interrupts(csis, true); 738 } 739 740 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 741 { 742 mipi_csis_enable_interrupts(csis, false); 743 mipi_csis_system_enable(csis, false); 744 } 745 746 static void mipi_csis_queue_event_sof(struct mipi_csis_device *csis) 747 { 748 struct v4l2_event event = { 749 .type = V4L2_EVENT_FRAME_SYNC, 750 }; 751 u32 frame; 752 753 frame = mipi_csis_read(csis, MIPI_CSIS_FRAME_COUNTER_CH(0)); 754 event.u.frame_sync.frame_sequence = frame; 755 v4l2_event_queue(csis->sd.devnode, &event); 756 } 757 758 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 759 { 760 struct mipi_csis_device *csis = dev_id; 761 unsigned long flags; 762 unsigned int i; 763 u32 status; 764 u32 dbg_status; 765 766 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 767 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 768 769 spin_lock_irqsave(&csis->slock, flags); 770 771 /* Update the event/error counters */ 772 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 773 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 774 struct mipi_csis_event *event = &csis->events[i]; 775 776 if ((!event->debug && (status & event->mask)) || 777 (event->debug && (dbg_status & event->mask))) 778 event->counter++; 779 } 780 } 781 782 if (status & MIPI_CSIS_INT_SRC_FRAME_START) 783 mipi_csis_queue_event_sof(csis); 784 785 spin_unlock_irqrestore(&csis->slock, flags); 786 787 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 788 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 789 790 return IRQ_HANDLED; 791 } 792 793 /* ----------------------------------------------------------------------------- 794 * PHY regulator and reset 795 */ 796 797 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 798 { 799 if (csis->info->version != MIPI_CSIS_V3_3) 800 return 0; 801 802 return regulator_enable(csis->mipi_phy_regulator); 803 } 804 805 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 806 { 807 if (csis->info->version != MIPI_CSIS_V3_3) 808 return 0; 809 810 return regulator_disable(csis->mipi_phy_regulator); 811 } 812 813 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 814 { 815 if (csis->info->version != MIPI_CSIS_V3_3) 816 return; 817 818 reset_control_assert(csis->mrst); 819 msleep(20); 820 reset_control_deassert(csis->mrst); 821 } 822 823 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 824 { 825 if (csis->info->version != MIPI_CSIS_V3_3) 826 return 0; 827 828 /* Get MIPI PHY reset and regulator. */ 829 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 830 if (IS_ERR(csis->mrst)) 831 return PTR_ERR(csis->mrst); 832 833 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 834 if (IS_ERR(csis->mipi_phy_regulator)) 835 return PTR_ERR(csis->mipi_phy_regulator); 836 837 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 838 1000000); 839 } 840 841 /* ----------------------------------------------------------------------------- 842 * Debug 843 */ 844 845 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 846 { 847 unsigned long flags; 848 unsigned int i; 849 850 spin_lock_irqsave(&csis->slock, flags); 851 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 852 csis->events[i].counter = 0; 853 spin_unlock_irqrestore(&csis->slock, flags); 854 } 855 856 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 857 { 858 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 859 : MIPI_CSIS_NUM_EVENTS - 8; 860 unsigned long flags; 861 unsigned int i; 862 863 spin_lock_irqsave(&csis->slock, flags); 864 865 for (i = 0; i < num_events; ++i) { 866 if (csis->events[i].counter > 0 || csis->debug.enable) 867 dev_info(csis->dev, "%s events: %d\n", 868 csis->events[i].name, 869 csis->events[i].counter); 870 } 871 spin_unlock_irqrestore(&csis->slock, flags); 872 } 873 874 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 875 { 876 static const struct { 877 u32 offset; 878 const char * const name; 879 } registers[] = { 880 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, 881 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, 882 { MIPI_CSIS_INT_MSK, "INT_MSK" }, 883 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, 884 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, 885 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, 886 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, 887 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, 888 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, 889 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, 890 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, 891 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, 892 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, 893 }; 894 895 unsigned int i; 896 u32 cfg; 897 898 if (!pm_runtime_get_if_in_use(csis->dev)) 899 return 0; 900 901 dev_info(csis->dev, "--- REGISTERS ---\n"); 902 903 for (i = 0; i < ARRAY_SIZE(registers); i++) { 904 cfg = mipi_csis_read(csis, registers[i].offset); 905 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 906 } 907 908 pm_runtime_put(csis->dev); 909 910 return 0; 911 } 912 913 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 914 { 915 struct mipi_csis_device *csis = m->private; 916 917 return mipi_csis_dump_regs(csis); 918 } 919 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 920 921 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 922 { 923 csis->debug.hs_settle = UINT_MAX; 924 csis->debug.clk_settle = UINT_MAX; 925 926 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 927 928 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 929 &csis->debug.enable); 930 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 931 &mipi_csis_dump_regs_fops); 932 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 933 &csis->debug.clk_settle); 934 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 935 &csis->debug.hs_settle); 936 } 937 938 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 939 { 940 debugfs_remove_recursive(csis->debugfs_root); 941 } 942 943 /* ----------------------------------------------------------------------------- 944 * V4L2 subdev operations 945 */ 946 947 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 948 { 949 return container_of(sdev, struct mipi_csis_device, sd); 950 } 951 952 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 953 { 954 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 955 const struct v4l2_mbus_framefmt *format; 956 const struct csis_pix_format *csis_fmt; 957 struct v4l2_subdev_state *state; 958 int ret; 959 960 if (!enable) { 961 v4l2_subdev_call(csis->src_sd, video, s_stream, 0); 962 963 mipi_csis_stop_stream(csis); 964 if (csis->debug.enable) 965 mipi_csis_log_counters(csis, true); 966 967 pm_runtime_put(csis->dev); 968 969 return 0; 970 } 971 972 state = v4l2_subdev_lock_and_get_active_state(sd); 973 974 format = v4l2_subdev_state_get_format(state, CSIS_PAD_SINK); 975 csis_fmt = find_csis_format(format->code); 976 977 ret = mipi_csis_calculate_params(csis, csis_fmt); 978 if (ret < 0) 979 goto err_unlock; 980 981 mipi_csis_clear_counters(csis); 982 983 ret = pm_runtime_resume_and_get(csis->dev); 984 if (ret < 0) 985 goto err_unlock; 986 987 mipi_csis_start_stream(csis, format, csis_fmt); 988 989 ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1); 990 if (ret < 0) 991 goto err_stop; 992 993 mipi_csis_log_counters(csis, true); 994 995 v4l2_subdev_unlock_state(state); 996 997 return 0; 998 999 err_stop: 1000 mipi_csis_stop_stream(csis); 1001 pm_runtime_put(csis->dev); 1002 err_unlock: 1003 v4l2_subdev_unlock_state(state); 1004 1005 return ret; 1006 } 1007 1008 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 1009 struct v4l2_subdev_state *sd_state, 1010 struct v4l2_subdev_mbus_code_enum *code) 1011 { 1012 /* 1013 * The CSIS can't transcode in any way, the source format is identical 1014 * to the sink format. 1015 */ 1016 if (code->pad == CSIS_PAD_SOURCE) { 1017 struct v4l2_mbus_framefmt *fmt; 1018 1019 if (code->index > 0) 1020 return -EINVAL; 1021 1022 fmt = v4l2_subdev_state_get_format(sd_state, code->pad); 1023 code->code = fmt->code; 1024 return 0; 1025 } 1026 1027 if (code->pad != CSIS_PAD_SINK) 1028 return -EINVAL; 1029 1030 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1031 return -EINVAL; 1032 1033 code->code = mipi_csis_formats[code->index].code; 1034 1035 return 0; 1036 } 1037 1038 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1039 struct v4l2_subdev_state *sd_state, 1040 struct v4l2_subdev_format *sdformat) 1041 { 1042 struct csis_pix_format const *csis_fmt; 1043 struct v4l2_mbus_framefmt *fmt; 1044 unsigned int align; 1045 1046 /* 1047 * The CSIS can't transcode in any way, the source format can't be 1048 * modified. 1049 */ 1050 if (sdformat->pad == CSIS_PAD_SOURCE) 1051 return v4l2_subdev_get_fmt(sd, sd_state, sdformat); 1052 1053 if (sdformat->pad != CSIS_PAD_SINK) 1054 return -EINVAL; 1055 1056 /* 1057 * Validate the media bus code and clamp and align the size. 1058 * 1059 * The total number of bits per line must be a multiple of 8. We thus 1060 * need to align the width for formats that are not multiples of 8 1061 * bits. 1062 */ 1063 csis_fmt = find_csis_format(sdformat->format.code); 1064 if (!csis_fmt) 1065 csis_fmt = &mipi_csis_formats[0]; 1066 1067 switch (csis_fmt->width % 8) { 1068 case 0: 1069 align = 0; 1070 break; 1071 case 4: 1072 align = 1; 1073 break; 1074 case 2: 1075 case 6: 1076 align = 2; 1077 break; 1078 default: 1079 /* 1, 3, 5, 7 */ 1080 align = 3; 1081 break; 1082 } 1083 1084 v4l_bound_align_image(&sdformat->format.width, 1, 1085 CSIS_MAX_PIX_WIDTH, align, 1086 &sdformat->format.height, 1, 1087 CSIS_MAX_PIX_HEIGHT, 0, 0); 1088 1089 fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad); 1090 1091 fmt->code = csis_fmt->code; 1092 fmt->width = sdformat->format.width; 1093 fmt->height = sdformat->format.height; 1094 fmt->field = V4L2_FIELD_NONE; 1095 fmt->colorspace = sdformat->format.colorspace; 1096 fmt->quantization = sdformat->format.quantization; 1097 fmt->xfer_func = sdformat->format.xfer_func; 1098 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1099 1100 sdformat->format = *fmt; 1101 1102 /* Propagate the format from sink to source. */ 1103 fmt = v4l2_subdev_state_get_format(sd_state, CSIS_PAD_SOURCE); 1104 *fmt = sdformat->format; 1105 1106 /* The format on the source pad might change due to unpacking. */ 1107 fmt->code = csis_fmt->output; 1108 1109 return 0; 1110 } 1111 1112 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 1113 struct v4l2_mbus_frame_desc *fd) 1114 { 1115 struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0]; 1116 const struct csis_pix_format *csis_fmt; 1117 const struct v4l2_mbus_framefmt *fmt; 1118 struct v4l2_subdev_state *state; 1119 1120 if (pad != CSIS_PAD_SOURCE) 1121 return -EINVAL; 1122 1123 state = v4l2_subdev_lock_and_get_active_state(sd); 1124 fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE); 1125 csis_fmt = find_csis_format(fmt->code); 1126 v4l2_subdev_unlock_state(state); 1127 1128 if (!csis_fmt) 1129 return -EPIPE; 1130 1131 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL; 1132 fd->num_entries = 1; 1133 1134 entry->flags = 0; 1135 entry->pixelcode = csis_fmt->code; 1136 entry->bus.csi2.vc = 0; 1137 entry->bus.csi2.dt = csis_fmt->data_type; 1138 1139 return 0; 1140 } 1141 1142 static int mipi_csis_init_state(struct v4l2_subdev *sd, 1143 struct v4l2_subdev_state *sd_state) 1144 { 1145 struct v4l2_subdev_format fmt = { 1146 .pad = CSIS_PAD_SINK, 1147 }; 1148 1149 fmt.format.code = mipi_csis_formats[0].code; 1150 fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH; 1151 fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT; 1152 1153 fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1154 fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace); 1155 fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace); 1156 fmt.format.quantization = 1157 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace, 1158 fmt.format.ycbcr_enc); 1159 1160 return mipi_csis_set_fmt(sd, sd_state, &fmt); 1161 } 1162 1163 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1164 { 1165 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1166 1167 mipi_csis_log_counters(csis, true); 1168 if (csis->debug.enable) 1169 mipi_csis_dump_regs(csis); 1170 1171 return 0; 1172 } 1173 1174 static int mipi_csis_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1175 struct v4l2_event_subscription *sub) 1176 { 1177 if (sub->type != V4L2_EVENT_FRAME_SYNC) 1178 return -EINVAL; 1179 1180 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */ 1181 if (sub->id != 0) 1182 return -EINVAL; 1183 1184 return v4l2_event_subscribe(fh, sub, 0, NULL); 1185 } 1186 1187 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1188 .log_status = mipi_csis_log_status, 1189 .subscribe_event = mipi_csis_subscribe_event, 1190 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1191 }; 1192 1193 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1194 .s_stream = mipi_csis_s_stream, 1195 }; 1196 1197 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1198 .enum_mbus_code = mipi_csis_enum_mbus_code, 1199 .get_fmt = v4l2_subdev_get_fmt, 1200 .set_fmt = mipi_csis_set_fmt, 1201 .get_frame_desc = mipi_csis_get_frame_desc, 1202 }; 1203 1204 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1205 .core = &mipi_csis_core_ops, 1206 .video = &mipi_csis_video_ops, 1207 .pad = &mipi_csis_pad_ops, 1208 }; 1209 1210 static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = { 1211 .init_state = mipi_csis_init_state, 1212 }; 1213 1214 /* ----------------------------------------------------------------------------- 1215 * Media entity operations 1216 */ 1217 1218 static int mipi_csis_link_setup(struct media_entity *entity, 1219 const struct media_pad *local_pad, 1220 const struct media_pad *remote_pad, u32 flags) 1221 { 1222 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1223 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1224 struct v4l2_subdev *remote_sd; 1225 1226 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1227 local_pad->entity->name); 1228 1229 /* We only care about the link to the source. */ 1230 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1231 return 0; 1232 1233 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1234 1235 if (flags & MEDIA_LNK_FL_ENABLED) { 1236 if (csis->src_sd) 1237 return -EBUSY; 1238 1239 csis->src_sd = remote_sd; 1240 } else { 1241 csis->src_sd = NULL; 1242 } 1243 1244 return 0; 1245 } 1246 1247 static const struct media_entity_operations mipi_csis_entity_ops = { 1248 .link_setup = mipi_csis_link_setup, 1249 .link_validate = v4l2_subdev_link_validate, 1250 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1251 }; 1252 1253 /* ----------------------------------------------------------------------------- 1254 * Async subdev notifier 1255 */ 1256 1257 static struct mipi_csis_device * 1258 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1259 { 1260 return container_of(n, struct mipi_csis_device, notifier); 1261 } 1262 1263 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1264 struct v4l2_subdev *sd, 1265 struct v4l2_async_connection *asd) 1266 { 1267 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1268 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1269 1270 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1271 } 1272 1273 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1274 .bound = mipi_csis_notify_bound, 1275 }; 1276 1277 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1278 { 1279 struct v4l2_fwnode_endpoint vep = { 1280 .bus_type = V4L2_MBUS_CSI2_DPHY, 1281 }; 1282 struct v4l2_async_connection *asd; 1283 struct fwnode_handle *ep; 1284 unsigned int i; 1285 int ret; 1286 1287 v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd); 1288 1289 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1290 FWNODE_GRAPH_ENDPOINT_NEXT); 1291 if (!ep) 1292 return -ENOTCONN; 1293 1294 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1295 if (ret) 1296 goto err_parse; 1297 1298 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1299 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1300 dev_err(csis->dev, 1301 "data lanes reordering is not supported"); 1302 ret = -EINVAL; 1303 goto err_parse; 1304 } 1305 } 1306 1307 csis->bus = vep.bus.mipi_csi2; 1308 1309 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1310 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1311 1312 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1313 struct v4l2_async_connection); 1314 if (IS_ERR(asd)) { 1315 ret = PTR_ERR(asd); 1316 goto err_parse; 1317 } 1318 1319 fwnode_handle_put(ep); 1320 1321 csis->notifier.ops = &mipi_csis_notify_ops; 1322 1323 ret = v4l2_async_nf_register(&csis->notifier); 1324 if (ret) 1325 return ret; 1326 1327 return v4l2_async_register_subdev(&csis->sd); 1328 1329 err_parse: 1330 fwnode_handle_put(ep); 1331 1332 return ret; 1333 } 1334 1335 /* ----------------------------------------------------------------------------- 1336 * Suspend/resume 1337 */ 1338 1339 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) 1340 { 1341 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1342 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1343 int ret; 1344 1345 ret = mipi_csis_phy_disable(csis); 1346 if (ret) 1347 return -EAGAIN; 1348 1349 mipi_csis_clk_disable(csis); 1350 1351 return 0; 1352 } 1353 1354 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) 1355 { 1356 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1357 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1358 int ret; 1359 1360 ret = mipi_csis_phy_enable(csis); 1361 if (ret) 1362 return -EAGAIN; 1363 1364 ret = mipi_csis_clk_enable(csis); 1365 if (ret) { 1366 mipi_csis_phy_disable(csis); 1367 return ret; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static const struct dev_pm_ops mipi_csis_pm_ops = { 1374 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1375 NULL) 1376 }; 1377 1378 /* ----------------------------------------------------------------------------- 1379 * Probe/remove & platform driver 1380 */ 1381 1382 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1383 { 1384 struct v4l2_subdev *sd = &csis->sd; 1385 int ret; 1386 1387 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1388 sd->internal_ops = &mipi_csis_internal_ops; 1389 sd->owner = THIS_MODULE; 1390 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1391 dev_name(csis->dev)); 1392 1393 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1394 sd->ctrl_handler = NULL; 1395 1396 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1397 sd->entity.ops = &mipi_csis_entity_ops; 1398 1399 sd->dev = csis->dev; 1400 1401 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1402 | MEDIA_PAD_FL_MUST_CONNECT; 1403 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1404 | MEDIA_PAD_FL_MUST_CONNECT; 1405 ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads); 1406 if (ret) 1407 return ret; 1408 1409 ret = v4l2_subdev_init_finalize(sd); 1410 if (ret) { 1411 media_entity_cleanup(&sd->entity); 1412 return ret; 1413 } 1414 1415 return 0; 1416 } 1417 1418 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1419 { 1420 struct device_node *node = csis->dev->of_node; 1421 1422 if (of_property_read_u32(node, "clock-frequency", 1423 &csis->clk_frequency)) 1424 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1425 1426 return 0; 1427 } 1428 1429 static int mipi_csis_probe(struct platform_device *pdev) 1430 { 1431 struct device *dev = &pdev->dev; 1432 struct mipi_csis_device *csis; 1433 int irq; 1434 int ret; 1435 1436 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1437 if (!csis) 1438 return -ENOMEM; 1439 1440 spin_lock_init(&csis->slock); 1441 1442 csis->dev = dev; 1443 csis->info = of_device_get_match_data(dev); 1444 1445 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1446 1447 /* Parse DT properties. */ 1448 ret = mipi_csis_parse_dt(csis); 1449 if (ret < 0) { 1450 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1451 return ret; 1452 } 1453 1454 /* Acquire resources. */ 1455 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1456 if (IS_ERR(csis->regs)) 1457 return PTR_ERR(csis->regs); 1458 1459 irq = platform_get_irq(pdev, 0); 1460 if (irq < 0) 1461 return irq; 1462 1463 ret = mipi_csis_phy_init(csis); 1464 if (ret < 0) 1465 return ret; 1466 1467 ret = mipi_csis_clk_get(csis); 1468 if (ret < 0) 1469 return ret; 1470 1471 /* Reset PHY and enable the clocks. */ 1472 mipi_csis_phy_reset(csis); 1473 1474 /* Now that the hardware is initialized, request the interrupt. */ 1475 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1476 dev_name(dev), csis); 1477 if (ret) { 1478 dev_err(dev, "Interrupt request failed\n"); 1479 return ret; 1480 } 1481 1482 /* Initialize and register the subdev. */ 1483 ret = mipi_csis_subdev_init(csis); 1484 if (ret < 0) 1485 return ret; 1486 1487 platform_set_drvdata(pdev, &csis->sd); 1488 1489 ret = mipi_csis_async_register(csis); 1490 if (ret < 0) { 1491 dev_err(dev, "async register failed: %d\n", ret); 1492 goto err_cleanup; 1493 } 1494 1495 /* Initialize debugfs. */ 1496 mipi_csis_debugfs_init(csis); 1497 1498 /* Enable runtime PM. */ 1499 pm_runtime_enable(dev); 1500 if (!pm_runtime_enabled(dev)) { 1501 ret = mipi_csis_runtime_resume(dev); 1502 if (ret < 0) 1503 goto err_unregister_all; 1504 } 1505 1506 dev_info(dev, "lanes: %d, freq: %u\n", 1507 csis->bus.num_data_lanes, csis->clk_frequency); 1508 1509 return 0; 1510 1511 err_unregister_all: 1512 mipi_csis_debugfs_exit(csis); 1513 err_cleanup: 1514 v4l2_subdev_cleanup(&csis->sd); 1515 media_entity_cleanup(&csis->sd.entity); 1516 v4l2_async_nf_unregister(&csis->notifier); 1517 v4l2_async_nf_cleanup(&csis->notifier); 1518 v4l2_async_unregister_subdev(&csis->sd); 1519 1520 return ret; 1521 } 1522 1523 static void mipi_csis_remove(struct platform_device *pdev) 1524 { 1525 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1526 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1527 1528 mipi_csis_debugfs_exit(csis); 1529 v4l2_async_nf_unregister(&csis->notifier); 1530 v4l2_async_nf_cleanup(&csis->notifier); 1531 v4l2_async_unregister_subdev(&csis->sd); 1532 1533 if (!pm_runtime_enabled(&pdev->dev)) 1534 mipi_csis_runtime_suspend(&pdev->dev); 1535 1536 pm_runtime_disable(&pdev->dev); 1537 v4l2_subdev_cleanup(&csis->sd); 1538 media_entity_cleanup(&csis->sd.entity); 1539 pm_runtime_set_suspended(&pdev->dev); 1540 } 1541 1542 static const struct of_device_id mipi_csis_of_match[] = { 1543 { 1544 .compatible = "fsl,imx7-mipi-csi2", 1545 .data = &(const struct mipi_csis_info){ 1546 .version = MIPI_CSIS_V3_3, 1547 .num_clocks = 3, 1548 }, 1549 }, { 1550 .compatible = "fsl,imx8mm-mipi-csi2", 1551 .data = &(const struct mipi_csis_info){ 1552 .version = MIPI_CSIS_V3_6_3, 1553 .num_clocks = 4, 1554 }, 1555 }, 1556 { /* sentinel */ }, 1557 }; 1558 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1559 1560 static struct platform_driver mipi_csis_driver = { 1561 .probe = mipi_csis_probe, 1562 .remove_new = mipi_csis_remove, 1563 .driver = { 1564 .of_match_table = mipi_csis_of_match, 1565 .name = CSIS_DRIVER_NAME, 1566 .pm = &mipi_csis_pm_ops, 1567 }, 1568 }; 1569 1570 module_platform_driver(mipi_csis_driver); 1571 1572 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1573 MODULE_LICENSE("GPL v2"); 1574 MODULE_ALIAS("platform:imx-mipi-csi2"); 1575