1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * DW100 Hardware dewarper 4 * 5 * Copyright 2022 NXP 6 * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com) 7 * 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-event.h> 23 #include <media/v4l2-ioctl.h> 24 #include <media/v4l2-mem2mem.h> 25 #include <media/videobuf2-dma-contig.h> 26 27 #include <uapi/linux/dw100.h> 28 29 #include "dw100_regs.h" 30 31 #define DRV_NAME "dw100" 32 33 #define DW100_MIN_W 176u 34 #define DW100_MIN_H 144u 35 #define DW100_MAX_W 4096u 36 #define DW100_MAX_H 3072u 37 #define DW100_ALIGN_W 3 38 #define DW100_ALIGN_H 3 39 40 #define DW100_BLOCK_SIZE 16 41 42 #define DW100_DEF_W 640u 43 #define DW100_DEF_H 480u 44 #define DW100_DEF_LUT_W (DIV_ROUND_UP(DW100_DEF_W, DW100_BLOCK_SIZE) + 1) 45 #define DW100_DEF_LUT_H (DIV_ROUND_UP(DW100_DEF_H, DW100_BLOCK_SIZE) + 1) 46 47 /* 48 * 16 controls have been reserved for this driver for future extension, but 49 * let's limit the related driver allocation to the effective number of controls 50 * in use. 51 */ 52 #define DW100_MAX_CTRLS 1 53 #define DW100_CTRL_DEWARPING_MAP 0 54 55 enum { 56 DW100_QUEUE_SRC = 0, 57 DW100_QUEUE_DST = 1, 58 }; 59 60 enum { 61 DW100_FMT_CAPTURE = BIT(0), 62 DW100_FMT_OUTPUT = BIT(1), 63 }; 64 65 struct dw100_device { 66 struct platform_device *pdev; 67 struct v4l2_m2m_dev *m2m_dev; 68 struct v4l2_device v4l2_dev; 69 struct video_device vfd; 70 struct media_device mdev; 71 /* Video device lock */ 72 struct mutex vfd_mutex; 73 void __iomem *mmio; 74 struct clk_bulk_data *clks; 75 int num_clks; 76 struct dentry *debugfs_root; 77 }; 78 79 struct dw100_q_data { 80 struct v4l2_pix_format_mplane pix_fmt; 81 unsigned int sequence; 82 const struct dw100_fmt *fmt; 83 struct v4l2_rect crop; 84 }; 85 86 struct dw100_ctx { 87 struct v4l2_fh fh; 88 struct dw100_device *dw_dev; 89 struct v4l2_ctrl_handler hdl; 90 struct v4l2_ctrl *ctrls[DW100_MAX_CTRLS]; 91 /* per context m2m queue lock */ 92 struct mutex vq_mutex; 93 94 /* Look Up Table for pixel remapping */ 95 unsigned int *map; 96 dma_addr_t map_dma; 97 size_t map_size; 98 unsigned int map_width; 99 unsigned int map_height; 100 bool user_map_is_set; 101 102 /* Source and destination queue data */ 103 struct dw100_q_data q_data[2]; 104 }; 105 106 static const struct v4l2_frmsize_stepwise dw100_frmsize_stepwise = { 107 .min_width = DW100_MIN_W, 108 .min_height = DW100_MIN_H, 109 .max_width = DW100_MAX_W, 110 .max_height = DW100_MAX_H, 111 .step_width = 1UL << DW100_ALIGN_W, 112 .step_height = 1UL << DW100_ALIGN_H, 113 }; 114 115 static const struct dw100_fmt { 116 u32 fourcc; 117 u32 types; 118 u32 reg_format; 119 bool reg_swap_uv; 120 } formats[] = { 121 { 122 .fourcc = V4L2_PIX_FMT_NV16, 123 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 124 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 125 .reg_swap_uv = false, 126 }, { 127 .fourcc = V4L2_PIX_FMT_NV16M, 128 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 129 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 130 .reg_swap_uv = false, 131 }, { 132 .fourcc = V4L2_PIX_FMT_NV61, 133 .types = DW100_FMT_CAPTURE, 134 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 135 .reg_swap_uv = true, 136 }, { 137 .fourcc = V4L2_PIX_FMT_NV61M, 138 .types = DW100_FMT_CAPTURE, 139 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 140 .reg_swap_uv = true, 141 }, { 142 .fourcc = V4L2_PIX_FMT_YUYV, 143 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 144 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, 145 .reg_swap_uv = false, 146 }, { 147 .fourcc = V4L2_PIX_FMT_UYVY, 148 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 149 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, 150 .reg_swap_uv = true, 151 }, { 152 .fourcc = V4L2_PIX_FMT_NV12, 153 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 154 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 155 .reg_swap_uv = false, 156 }, { 157 .fourcc = V4L2_PIX_FMT_NV12M, 158 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 159 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 160 .reg_swap_uv = false, 161 }, { 162 .fourcc = V4L2_PIX_FMT_NV21, 163 .types = DW100_FMT_CAPTURE, 164 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 165 .reg_swap_uv = true, 166 }, { 167 .fourcc = V4L2_PIX_FMT_NV21M, 168 .types = DW100_FMT_CAPTURE, 169 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 170 .reg_swap_uv = true, 171 }, 172 }; 173 174 static inline int to_dw100_fmt_type(enum v4l2_buf_type type) 175 { 176 if (V4L2_TYPE_IS_OUTPUT(type)) 177 return DW100_FMT_OUTPUT; 178 else 179 return DW100_FMT_CAPTURE; 180 } 181 182 static const struct dw100_fmt *dw100_find_pixel_format(u32 pixel_format, 183 int fmt_type) 184 { 185 unsigned int i; 186 187 for (i = 0; i < ARRAY_SIZE(formats); i++) { 188 const struct dw100_fmt *fmt = &formats[i]; 189 190 if (fmt->fourcc == pixel_format && fmt->types & fmt_type) 191 return fmt; 192 } 193 194 return NULL; 195 } 196 197 static const struct dw100_fmt *dw100_find_format(struct v4l2_format *f) 198 { 199 return dw100_find_pixel_format(f->fmt.pix_mp.pixelformat, 200 to_dw100_fmt_type(f->type)); 201 } 202 203 static inline u32 dw100_read(struct dw100_device *dw_dev, u32 reg) 204 { 205 return readl(dw_dev->mmio + reg); 206 } 207 208 static inline void dw100_write(struct dw100_device *dw_dev, u32 reg, u32 val) 209 { 210 writel(val, dw_dev->mmio + reg); 211 } 212 213 static inline int dw100_dump_regs(struct seq_file *m) 214 { 215 struct dw100_device *dw_dev = m->private; 216 #define __DECLARE_REG(x) { #x, x } 217 unsigned int i; 218 static const struct reg_desc { 219 const char * const name; 220 unsigned int addr; 221 } dw100_regs[] = { 222 __DECLARE_REG(DW100_DEWARP_ID), 223 __DECLARE_REG(DW100_DEWARP_CTRL), 224 __DECLARE_REG(DW100_MAP_LUT_ADDR), 225 __DECLARE_REG(DW100_MAP_LUT_SIZE), 226 __DECLARE_REG(DW100_MAP_LUT_ADDR2), 227 __DECLARE_REG(DW100_MAP_LUT_SIZE2), 228 __DECLARE_REG(DW100_SRC_IMG_Y_BASE), 229 __DECLARE_REG(DW100_SRC_IMG_UV_BASE), 230 __DECLARE_REG(DW100_SRC_IMG_SIZE), 231 __DECLARE_REG(DW100_SRC_IMG_STRIDE), 232 __DECLARE_REG(DW100_DST_IMG_Y_BASE), 233 __DECLARE_REG(DW100_DST_IMG_UV_BASE), 234 __DECLARE_REG(DW100_DST_IMG_SIZE), 235 __DECLARE_REG(DW100_DST_IMG_STRIDE), 236 __DECLARE_REG(DW100_DST_IMG_Y_SIZE1), 237 __DECLARE_REG(DW100_DST_IMG_UV_SIZE1), 238 __DECLARE_REG(DW100_SRC_IMG_Y_BASE2), 239 __DECLARE_REG(DW100_SRC_IMG_UV_BASE2), 240 __DECLARE_REG(DW100_SRC_IMG_SIZE2), 241 __DECLARE_REG(DW100_SRC_IMG_STRIDE2), 242 __DECLARE_REG(DW100_DST_IMG_Y_BASE2), 243 __DECLARE_REG(DW100_DST_IMG_UV_BASE2), 244 __DECLARE_REG(DW100_DST_IMG_SIZE2), 245 __DECLARE_REG(DW100_DST_IMG_STRIDE2), 246 __DECLARE_REG(DW100_DST_IMG_Y_SIZE2), 247 __DECLARE_REG(DW100_DST_IMG_UV_SIZE2), 248 __DECLARE_REG(DW100_SWAP_CONTROL), 249 __DECLARE_REG(DW100_VERTICAL_SPLIT_LINE), 250 __DECLARE_REG(DW100_HORIZON_SPLIT_LINE), 251 __DECLARE_REG(DW100_SCALE_FACTOR), 252 __DECLARE_REG(DW100_ROI_START), 253 __DECLARE_REG(DW100_BOUNDARY_PIXEL), 254 __DECLARE_REG(DW100_INTERRUPT_STATUS), 255 __DECLARE_REG(DW100_BUS_CTRL), 256 __DECLARE_REG(DW100_BUS_CTRL1), 257 __DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE), 258 }; 259 260 for (i = 0; i < ARRAY_SIZE(dw100_regs); i++) 261 seq_printf(m, "%s: %#x\n", dw100_regs[i].name, 262 dw100_read(dw_dev, dw100_regs[i].addr)); 263 264 return 0; 265 } 266 267 static inline struct dw100_ctx *dw100_file2ctx(struct file *file) 268 { 269 return container_of(file_to_v4l2_fh(file), struct dw100_ctx, fh); 270 } 271 272 static struct dw100_q_data *dw100_get_q_data(struct dw100_ctx *ctx, 273 enum v4l2_buf_type type) 274 { 275 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 276 return &ctx->q_data[DW100_QUEUE_SRC]; 277 else 278 return &ctx->q_data[DW100_QUEUE_DST]; 279 } 280 281 static u32 dw100_get_n_vertices_from_length(u32 length) 282 { 283 return DIV_ROUND_UP(length, DW100_BLOCK_SIZE) + 1; 284 } 285 286 static u16 dw100_map_convert_to_uq12_4(u32 a) 287 { 288 return (u16)((a & 0xfff) << 4); 289 } 290 291 static u32 dw100_map_format_coordinates(u16 xq, u16 yq) 292 { 293 return (u32)((yq << 16) | xq); 294 } 295 296 static u32 *dw100_get_user_map(struct dw100_ctx *ctx) 297 { 298 struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP]; 299 300 return ctrl->p_cur.p_u32; 301 } 302 303 /* 304 * Create the dewarp map used by the hardware from the V4L2 control values which 305 * have been initialized with an identity map or set by the application. 306 */ 307 static int dw100_create_mapping(struct dw100_ctx *ctx) 308 { 309 u32 *user_map; 310 311 if (ctx->map) 312 dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, 313 ctx->map, ctx->map_dma); 314 315 ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, 316 &ctx->map_dma, GFP_KERNEL); 317 318 if (!ctx->map) 319 return -ENOMEM; 320 321 user_map = dw100_get_user_map(ctx); 322 memcpy(ctx->map, user_map, ctx->map_size); 323 324 dev_dbg(&ctx->dw_dev->pdev->dev, 325 "%ux%u %s mapping created (d:%pad-c:%p) for stream %ux%u->%ux%u\n", 326 ctx->map_width, ctx->map_height, 327 ctx->user_map_is_set ? "user" : "identity", 328 &ctx->map_dma, ctx->map, 329 ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width, 330 ctx->q_data[DW100_QUEUE_DST].pix_fmt.height, 331 ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width, 332 ctx->q_data[DW100_QUEUE_DST].pix_fmt.height); 333 334 return 0; 335 } 336 337 static void dw100_destroy_mapping(struct dw100_ctx *ctx) 338 { 339 if (ctx->map) { 340 dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, 341 ctx->map, ctx->map_dma); 342 ctx->map = NULL; 343 } 344 } 345 346 static int dw100_s_ctrl(struct v4l2_ctrl *ctrl) 347 { 348 struct dw100_ctx *ctx = 349 container_of(ctrl->handler, struct dw100_ctx, hdl); 350 351 switch (ctrl->id) { 352 case V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP: 353 ctx->user_map_is_set = true; 354 break; 355 } 356 357 return 0; 358 } 359 360 static const struct v4l2_ctrl_ops dw100_ctrl_ops = { 361 .s_ctrl = dw100_s_ctrl, 362 }; 363 364 /* 365 * Initialize the dewarping map with an identity mapping. 366 * 367 * A 16 pixels cell size grid is mapped on the destination image. 368 * The last cells width/height might be lesser than 16 if the destination image 369 * width/height is not divisible by 16. This dewarping grid map specifies the 370 * source image pixel location (x, y) on each grid intersection point. 371 * Bilinear interpolation is used to compute inner cell points locations. 372 * 373 * The coordinates are saved in UQ12.4 fixed point format. 374 */ 375 static void dw100_ctrl_dewarping_map_init(const struct v4l2_ctrl *ctrl, 376 u32 from_idx, 377 union v4l2_ctrl_ptr ptr) 378 { 379 struct dw100_ctx *ctx = 380 container_of(ctrl->handler, struct dw100_ctx, hdl); 381 382 u32 sw, sh, mw, mh, idx; 383 u16 qx, qy, qdx, qdy, qsh, qsw; 384 u32 *map = ctrl->p_cur.p_u32; 385 386 sw = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width; 387 sh = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.height; 388 389 mw = ctrl->dims[0]; 390 mh = ctrl->dims[1]; 391 392 qsw = dw100_map_convert_to_uq12_4(sw); 393 qsh = dw100_map_convert_to_uq12_4(sh); 394 qdx = qsw / (mw - 1); 395 qdy = qsh / (mh - 1); 396 397 ctx->map_width = mw; 398 ctx->map_height = mh; 399 ctx->map_size = mh * mw * sizeof(u32); 400 401 for (idx = from_idx; idx < ctrl->elems; idx++) { 402 qy = min_t(u32, (idx / mw) * qdy, qsh); 403 qx = min_t(u32, (idx % mw) * qdx, qsw); 404 map[idx] = dw100_map_format_coordinates(qx, qy); 405 } 406 407 ctx->user_map_is_set = false; 408 } 409 410 static const struct v4l2_ctrl_type_ops dw100_ctrl_type_ops = { 411 .init = dw100_ctrl_dewarping_map_init, 412 .validate = v4l2_ctrl_type_op_validate, 413 .log = v4l2_ctrl_type_op_log, 414 .equal = v4l2_ctrl_type_op_equal, 415 }; 416 417 static const struct v4l2_ctrl_config controls[] = { 418 [DW100_CTRL_DEWARPING_MAP] = { 419 .ops = &dw100_ctrl_ops, 420 .type_ops = &dw100_ctrl_type_ops, 421 .id = V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP, 422 .name = "Dewarping Vertex Map", 423 .type = V4L2_CTRL_TYPE_U32, 424 .min = 0x00000000, 425 .max = 0xffffffff, 426 .step = 1, 427 .def = 0, 428 .dims = { DW100_DEF_LUT_W, DW100_DEF_LUT_H }, 429 }, 430 }; 431 432 static int dw100_queue_setup(struct vb2_queue *vq, 433 unsigned int *nbuffers, unsigned int *nplanes, 434 unsigned int sizes[], struct device *alloc_devs[]) 435 { 436 struct dw100_ctx *ctx = vb2_get_drv_priv(vq); 437 const struct v4l2_pix_format_mplane *format; 438 unsigned int i; 439 440 format = &dw100_get_q_data(ctx, vq->type)->pix_fmt; 441 442 if (*nplanes) { 443 if (*nplanes != format->num_planes) 444 return -EINVAL; 445 446 for (i = 0; i < *nplanes; ++i) { 447 if (sizes[i] < format->plane_fmt[i].sizeimage) 448 return -EINVAL; 449 } 450 451 return 0; 452 } 453 454 *nplanes = format->num_planes; 455 456 for (i = 0; i < format->num_planes; ++i) 457 sizes[i] = format->plane_fmt[i].sizeimage; 458 459 return 0; 460 } 461 462 static int dw100_buf_prepare(struct vb2_buffer *vb) 463 { 464 unsigned int i; 465 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 466 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 467 struct dw100_device *dw_dev = ctx->dw_dev; 468 const struct v4l2_pix_format_mplane *pix_fmt = 469 &dw100_get_q_data(ctx, vb->vb2_queue->type)->pix_fmt; 470 471 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { 472 if (vbuf->field != V4L2_FIELD_NONE) { 473 dev_dbg(&dw_dev->pdev->dev, "%x field isn't supported\n", 474 vbuf->field); 475 return -EINVAL; 476 } 477 } 478 479 for (i = 0; i < pix_fmt->num_planes; i++) { 480 unsigned long size = pix_fmt->plane_fmt[i].sizeimage; 481 482 if (vb2_plane_size(vb, i) < size) { 483 dev_dbg(&dw_dev->pdev->dev, 484 "User buffer too small (%lu < %lu)\n", 485 vb2_plane_size(vb, i), size); 486 return -EINVAL; 487 } 488 489 vb2_set_plane_payload(vb, i, size); 490 } 491 492 return 0; 493 } 494 495 static void dw100_buf_queue(struct vb2_buffer *vb) 496 { 497 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 498 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 499 500 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 501 } 502 503 static void dw100_return_all_buffers(struct vb2_queue *q, 504 enum vb2_buffer_state state) 505 { 506 struct dw100_ctx *ctx = vb2_get_drv_priv(q); 507 struct vb2_v4l2_buffer *vbuf; 508 509 for (;;) { 510 if (V4L2_TYPE_IS_OUTPUT(q->type)) 511 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 512 else 513 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 514 if (!vbuf) 515 return; 516 v4l2_m2m_buf_done(vbuf, state); 517 } 518 } 519 520 static int dw100_start_streaming(struct vb2_queue *q, unsigned int count) 521 { 522 struct dw100_ctx *ctx = vb2_get_drv_priv(q); 523 struct dw100_q_data *q_data = dw100_get_q_data(ctx, q->type); 524 int ret; 525 526 q_data->sequence = 0; 527 528 ret = dw100_create_mapping(ctx); 529 if (ret) 530 goto err; 531 532 ret = pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev); 533 if (ret) { 534 dw100_destroy_mapping(ctx); 535 goto err; 536 } 537 538 return 0; 539 err: 540 dw100_return_all_buffers(q, VB2_BUF_STATE_QUEUED); 541 return ret; 542 } 543 544 static void dw100_stop_streaming(struct vb2_queue *q) 545 { 546 struct dw100_ctx *ctx = vb2_get_drv_priv(q); 547 548 dw100_return_all_buffers(q, VB2_BUF_STATE_ERROR); 549 550 pm_runtime_put_sync(&ctx->dw_dev->pdev->dev); 551 552 dw100_destroy_mapping(ctx); 553 } 554 555 static const struct vb2_ops dw100_qops = { 556 .queue_setup = dw100_queue_setup, 557 .buf_prepare = dw100_buf_prepare, 558 .buf_queue = dw100_buf_queue, 559 .start_streaming = dw100_start_streaming, 560 .stop_streaming = dw100_stop_streaming, 561 }; 562 563 static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq, 564 struct vb2_queue *dst_vq) 565 { 566 struct dw100_ctx *ctx = priv; 567 int ret; 568 569 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 570 src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 571 src_vq->drv_priv = ctx; 572 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 573 src_vq->ops = &dw100_qops; 574 src_vq->mem_ops = &vb2_dma_contig_memops; 575 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 576 src_vq->lock = &ctx->vq_mutex; 577 src_vq->dev = ctx->dw_dev->v4l2_dev.dev; 578 579 ret = vb2_queue_init(src_vq); 580 if (ret) 581 return ret; 582 583 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 584 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 585 dst_vq->drv_priv = ctx; 586 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 587 dst_vq->ops = &dw100_qops; 588 dst_vq->mem_ops = &vb2_dma_contig_memops; 589 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 590 dst_vq->lock = &ctx->vq_mutex; 591 dst_vq->dev = ctx->dw_dev->v4l2_dev.dev; 592 593 return vb2_queue_init(dst_vq); 594 } 595 596 static int dw100_open(struct file *file) 597 { 598 struct dw100_device *dw_dev = video_drvdata(file); 599 struct dw100_ctx *ctx; 600 struct v4l2_ctrl_handler *hdl; 601 struct v4l2_pix_format_mplane *pix_fmt; 602 int ret, i; 603 604 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 605 if (!ctx) 606 return -ENOMEM; 607 608 mutex_init(&ctx->vq_mutex); 609 v4l2_fh_init(&ctx->fh, video_devdata(file)); 610 ctx->dw_dev = dw_dev; 611 612 ctx->q_data[DW100_QUEUE_SRC].fmt = &formats[0]; 613 614 pix_fmt = &ctx->q_data[DW100_QUEUE_SRC].pix_fmt; 615 pix_fmt->field = V4L2_FIELD_NONE; 616 pix_fmt->colorspace = V4L2_COLORSPACE_REC709; 617 pix_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix_fmt->colorspace); 618 pix_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix_fmt->colorspace); 619 pix_fmt->quantization = 620 V4L2_MAP_QUANTIZATION_DEFAULT(false, pix_fmt->colorspace, 621 pix_fmt->ycbcr_enc); 622 623 v4l2_fill_pixfmt_mp(pix_fmt, formats[0].fourcc, DW100_DEF_W, DW100_DEF_H); 624 625 ctx->q_data[DW100_QUEUE_SRC].crop.top = 0; 626 ctx->q_data[DW100_QUEUE_SRC].crop.left = 0; 627 ctx->q_data[DW100_QUEUE_SRC].crop.width = DW100_DEF_W; 628 ctx->q_data[DW100_QUEUE_SRC].crop.height = DW100_DEF_H; 629 630 ctx->q_data[DW100_QUEUE_DST] = ctx->q_data[DW100_QUEUE_SRC]; 631 632 hdl = &ctx->hdl; 633 v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(controls)); 634 for (i = 0; i < ARRAY_SIZE(controls); i++) { 635 ctx->ctrls[i] = v4l2_ctrl_new_custom(hdl, &controls[i], NULL); 636 if (hdl->error) { 637 dev_err(&ctx->dw_dev->pdev->dev, 638 "Adding control (%d) failed\n", i); 639 ret = hdl->error; 640 goto err; 641 } 642 } 643 ctx->fh.ctrl_handler = hdl; 644 645 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev, 646 ctx, &dw100_m2m_queue_init); 647 648 if (IS_ERR(ctx->fh.m2m_ctx)) { 649 ret = PTR_ERR(ctx->fh.m2m_ctx); 650 goto err; 651 } 652 653 v4l2_fh_add(&ctx->fh, file); 654 655 return 0; 656 657 err: 658 v4l2_ctrl_handler_free(hdl); 659 v4l2_fh_exit(&ctx->fh); 660 mutex_destroy(&ctx->vq_mutex); 661 kfree(ctx); 662 663 return ret; 664 } 665 666 static int dw100_release(struct file *file) 667 { 668 struct dw100_ctx *ctx = dw100_file2ctx(file); 669 670 v4l2_fh_del(&ctx->fh, file); 671 v4l2_fh_exit(&ctx->fh); 672 v4l2_ctrl_handler_free(&ctx->hdl); 673 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 674 mutex_destroy(&ctx->vq_mutex); 675 kfree(ctx); 676 677 return 0; 678 } 679 680 static const struct v4l2_file_operations dw100_fops = { 681 .owner = THIS_MODULE, 682 .open = dw100_open, 683 .release = dw100_release, 684 .poll = v4l2_m2m_fop_poll, 685 .unlocked_ioctl = video_ioctl2, 686 .mmap = v4l2_m2m_fop_mmap, 687 }; 688 689 static int dw100_querycap(struct file *file, void *priv, 690 struct v4l2_capability *cap) 691 { 692 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); 693 strscpy(cap->card, "DW100 dewarper", sizeof(cap->card)); 694 695 return 0; 696 } 697 698 static int dw100_enum_fmt_vid(struct file *file, void *priv, 699 struct v4l2_fmtdesc *f) 700 { 701 int i, num = 0; 702 703 for (i = 0; i < ARRAY_SIZE(formats); i++) { 704 if (formats[i].types & to_dw100_fmt_type(f->type)) { 705 if (num == f->index) { 706 f->pixelformat = formats[i].fourcc; 707 return 0; 708 } 709 ++num; 710 } 711 } 712 713 return -EINVAL; 714 } 715 716 static int dw100_enum_framesizes(struct file *file, void *priv, 717 struct v4l2_frmsizeenum *fsize) 718 { 719 const struct dw100_fmt *fmt; 720 721 if (fsize->index) 722 return -EINVAL; 723 724 fmt = dw100_find_pixel_format(fsize->pixel_format, 725 DW100_FMT_OUTPUT | DW100_FMT_CAPTURE); 726 if (!fmt) 727 return -EINVAL; 728 729 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 730 fsize->stepwise = dw100_frmsize_stepwise; 731 732 return 0; 733 } 734 735 static int dw100_g_fmt_vid(struct file *file, void *priv, struct v4l2_format *f) 736 { 737 struct dw100_ctx *ctx = dw100_file2ctx(file); 738 struct vb2_queue *vq; 739 struct dw100_q_data *q_data; 740 741 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 742 if (!vq) 743 return -EINVAL; 744 745 q_data = dw100_get_q_data(ctx, f->type); 746 747 f->fmt.pix_mp = q_data->pix_fmt; 748 749 return 0; 750 } 751 752 static int dw100_try_fmt(struct file *file, struct v4l2_format *f) 753 { 754 struct dw100_ctx *ctx = dw100_file2ctx(file); 755 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; 756 const struct dw100_fmt *fmt; 757 758 fmt = dw100_find_format(f); 759 if (!fmt) { 760 fmt = &formats[0]; 761 pix->pixelformat = fmt->fourcc; 762 } 763 764 v4l2_apply_frmsize_constraints(&pix->width, &pix->height, 765 &dw100_frmsize_stepwise); 766 767 v4l2_fill_pixfmt_mp(pix, fmt->fourcc, pix->width, pix->height); 768 769 pix->field = V4L2_FIELD_NONE; 770 771 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 772 if (pix->colorspace == V4L2_COLORSPACE_DEFAULT) 773 pix->colorspace = V4L2_COLORSPACE_REC709; 774 if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT) 775 pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace); 776 if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) 777 pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace); 778 if (pix->quantization == V4L2_QUANTIZATION_DEFAULT) 779 pix->quantization = 780 V4L2_MAP_QUANTIZATION_DEFAULT(false, 781 pix->colorspace, 782 pix->ycbcr_enc); 783 } else { 784 /* 785 * The DW100 can't perform colorspace conversion, the colorspace 786 * on the capture queue must be identical to the output queue. 787 */ 788 const struct dw100_q_data *q_data = 789 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 790 791 pix->colorspace = q_data->pix_fmt.colorspace; 792 pix->xfer_func = q_data->pix_fmt.xfer_func; 793 pix->ycbcr_enc = q_data->pix_fmt.ycbcr_enc; 794 pix->quantization = q_data->pix_fmt.quantization; 795 } 796 797 return 0; 798 } 799 800 static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f) 801 { 802 struct dw100_q_data *q_data; 803 struct vb2_queue *vq; 804 805 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 806 if (!vq) 807 return -EINVAL; 808 809 q_data = dw100_get_q_data(ctx, f->type); 810 if (!q_data) 811 return -EINVAL; 812 813 if (vb2_is_busy(vq)) { 814 dev_dbg(&ctx->dw_dev->pdev->dev, "%s queue busy\n", __func__); 815 return -EBUSY; 816 } 817 818 q_data->fmt = dw100_find_format(f); 819 q_data->pix_fmt = f->fmt.pix_mp; 820 q_data->crop.top = 0; 821 q_data->crop.left = 0; 822 q_data->crop.width = f->fmt.pix_mp.width; 823 q_data->crop.height = f->fmt.pix_mp.height; 824 825 /* Propagate buffers encoding */ 826 827 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 828 struct dw100_q_data *dst_q_data = 829 dw100_get_q_data(ctx, 830 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 831 832 dst_q_data->pix_fmt.colorspace = q_data->pix_fmt.colorspace; 833 dst_q_data->pix_fmt.ycbcr_enc = q_data->pix_fmt.ycbcr_enc; 834 dst_q_data->pix_fmt.quantization = q_data->pix_fmt.quantization; 835 dst_q_data->pix_fmt.xfer_func = q_data->pix_fmt.xfer_func; 836 } 837 838 dev_dbg(&ctx->dw_dev->pdev->dev, 839 "Setting format for type %u, wxh: %ux%u, fmt: %p4cc\n", 840 f->type, q_data->pix_fmt.width, q_data->pix_fmt.height, 841 &q_data->pix_fmt.pixelformat); 842 843 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { 844 int ret; 845 u32 dims[V4L2_CTRL_MAX_DIMS] = {}; 846 struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP]; 847 848 dims[0] = dw100_get_n_vertices_from_length(q_data->pix_fmt.width); 849 dims[1] = dw100_get_n_vertices_from_length(q_data->pix_fmt.height); 850 851 ret = v4l2_ctrl_modify_dimensions(ctrl, dims); 852 853 if (ret) { 854 dev_err(&ctx->dw_dev->pdev->dev, 855 "Modifying LUT dimensions failed with error %d\n", 856 ret); 857 return ret; 858 } 859 } 860 861 return 0; 862 } 863 864 static int dw100_try_fmt_vid_cap(struct file *file, void *priv, 865 struct v4l2_format *f) 866 { 867 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) 868 return -EINVAL; 869 870 return dw100_try_fmt(file, f); 871 } 872 873 static int dw100_s_fmt_vid_cap(struct file *file, void *priv, 874 struct v4l2_format *f) 875 { 876 struct dw100_ctx *ctx = dw100_file2ctx(file); 877 int ret; 878 879 ret = dw100_try_fmt_vid_cap(file, priv, f); 880 if (ret) 881 return ret; 882 883 ret = dw100_s_fmt(ctx, f); 884 if (ret) 885 return ret; 886 887 return 0; 888 } 889 890 static int dw100_try_fmt_vid_out(struct file *file, void *priv, 891 struct v4l2_format *f) 892 { 893 if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 894 return -EINVAL; 895 896 return dw100_try_fmt(file, f); 897 } 898 899 static int dw100_s_fmt_vid_out(struct file *file, void *priv, 900 struct v4l2_format *f) 901 { 902 struct dw100_ctx *ctx = dw100_file2ctx(file); 903 int ret; 904 905 ret = dw100_try_fmt_vid_out(file, priv, f); 906 if (ret) 907 return ret; 908 909 ret = dw100_s_fmt(ctx, f); 910 if (ret) 911 return ret; 912 913 return 0; 914 } 915 916 static int dw100_g_selection(struct file *file, void *fh, 917 struct v4l2_selection *sel) 918 { 919 struct dw100_ctx *ctx = dw100_file2ctx(file); 920 struct dw100_q_data *src_q_data; 921 922 if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 923 return -EINVAL; 924 925 src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 926 927 switch (sel->target) { 928 case V4L2_SEL_TGT_CROP_DEFAULT: 929 case V4L2_SEL_TGT_CROP_BOUNDS: 930 sel->r.top = 0; 931 sel->r.left = 0; 932 sel->r.width = src_q_data->pix_fmt.width; 933 sel->r.height = src_q_data->pix_fmt.height; 934 break; 935 case V4L2_SEL_TGT_CROP: 936 sel->r.top = src_q_data->crop.top; 937 sel->r.left = src_q_data->crop.left; 938 sel->r.width = src_q_data->crop.width; 939 sel->r.height = src_q_data->crop.height; 940 break; 941 default: 942 return -EINVAL; 943 } 944 945 return 0; 946 } 947 948 static int dw100_s_selection(struct file *file, void *fh, 949 struct v4l2_selection *sel) 950 { 951 struct dw100_ctx *ctx = dw100_file2ctx(file); 952 struct dw100_q_data *src_q_data; 953 u32 qscalex, qscaley, qscale; 954 int x, y, w, h; 955 unsigned int wframe, hframe; 956 957 if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 958 return -EINVAL; 959 960 src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 961 962 dev_dbg(&ctx->dw_dev->pdev->dev, 963 ">>> Buffer Type: %u Target: %u Rect: (%d,%d)/%ux%u\n", 964 sel->type, sel->target, 965 sel->r.left, sel->r.top, sel->r.width, sel->r.height); 966 967 switch (sel->target) { 968 case V4L2_SEL_TGT_CROP: 969 wframe = src_q_data->pix_fmt.width; 970 hframe = src_q_data->pix_fmt.height; 971 972 sel->r.top = clamp_t(int, sel->r.top, 0, hframe - DW100_MIN_H); 973 sel->r.left = clamp_t(int, sel->r.left, 0, wframe - DW100_MIN_W); 974 sel->r.height = 975 clamp(sel->r.height, DW100_MIN_H, hframe - sel->r.top); 976 sel->r.width = 977 clamp(sel->r.width, DW100_MIN_W, wframe - sel->r.left); 978 979 /* UQ16.16 for float operations */ 980 qscalex = (sel->r.width << 16) / wframe; 981 qscaley = (sel->r.height << 16) / hframe; 982 y = sel->r.top; 983 x = sel->r.left; 984 if (qscalex == qscaley) { 985 qscale = qscalex; 986 } else { 987 switch (sel->flags) { 988 case 0: 989 qscale = (qscalex + qscaley) / 2; 990 break; 991 case V4L2_SEL_FLAG_GE: 992 qscale = max(qscaley, qscalex); 993 break; 994 case V4L2_SEL_FLAG_LE: 995 qscale = min(qscaley, qscalex); 996 break; 997 case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE: 998 return -ERANGE; 999 default: 1000 return -EINVAL; 1001 } 1002 } 1003 1004 w = (u32)((((u64)wframe << 16) * qscale) >> 32); 1005 h = (u32)((((u64)hframe << 16) * qscale) >> 32); 1006 x = x + (sel->r.width - w) / 2; 1007 y = y + (sel->r.height - h) / 2; 1008 x = min(wframe - w, (unsigned int)max(0, x)); 1009 y = min(hframe - h, (unsigned int)max(0, y)); 1010 1011 sel->r.top = y; 1012 sel->r.left = x; 1013 sel->r.width = w; 1014 sel->r.height = h; 1015 1016 src_q_data->crop.top = sel->r.top; 1017 src_q_data->crop.left = sel->r.left; 1018 src_q_data->crop.width = sel->r.width; 1019 src_q_data->crop.height = sel->r.height; 1020 break; 1021 1022 default: 1023 return -EINVAL; 1024 } 1025 1026 dev_dbg(&ctx->dw_dev->pdev->dev, 1027 "<<< Buffer Type: %u Target: %u Rect: (%d,%d)/%ux%u\n", 1028 sel->type, sel->target, 1029 sel->r.left, sel->r.top, sel->r.width, sel->r.height); 1030 1031 return 0; 1032 } 1033 1034 static const struct v4l2_ioctl_ops dw100_ioctl_ops = { 1035 .vidioc_querycap = dw100_querycap, 1036 1037 .vidioc_enum_fmt_vid_cap = dw100_enum_fmt_vid, 1038 .vidioc_enum_framesizes = dw100_enum_framesizes, 1039 .vidioc_g_fmt_vid_cap_mplane = dw100_g_fmt_vid, 1040 .vidioc_try_fmt_vid_cap_mplane = dw100_try_fmt_vid_cap, 1041 .vidioc_s_fmt_vid_cap_mplane = dw100_s_fmt_vid_cap, 1042 1043 .vidioc_enum_fmt_vid_out = dw100_enum_fmt_vid, 1044 .vidioc_g_fmt_vid_out_mplane = dw100_g_fmt_vid, 1045 .vidioc_try_fmt_vid_out_mplane = dw100_try_fmt_vid_out, 1046 .vidioc_s_fmt_vid_out_mplane = dw100_s_fmt_vid_out, 1047 1048 .vidioc_g_selection = dw100_g_selection, 1049 .vidioc_s_selection = dw100_s_selection, 1050 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 1051 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 1052 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 1053 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 1054 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 1055 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 1056 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 1057 1058 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 1059 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 1060 1061 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1062 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1063 }; 1064 1065 static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error) 1066 { 1067 struct dw100_ctx *curr_ctx; 1068 struct vb2_v4l2_buffer *src_vb, *dst_vb; 1069 enum vb2_buffer_state buf_state; 1070 1071 curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev); 1072 1073 if (!curr_ctx) { 1074 dev_err(&dw_dev->pdev->dev, 1075 "Instance released before the end of transaction\n"); 1076 return; 1077 } 1078 1079 src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx); 1080 dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx); 1081 1082 if (likely(!with_error)) 1083 buf_state = VB2_BUF_STATE_DONE; 1084 else 1085 buf_state = VB2_BUF_STATE_ERROR; 1086 1087 v4l2_m2m_buf_done(src_vb, buf_state); 1088 v4l2_m2m_buf_done(dst_vb, buf_state); 1089 1090 dev_dbg(&dw_dev->pdev->dev, "Finishing transaction with%s error(s)\n", 1091 with_error ? "" : "out"); 1092 1093 v4l2_m2m_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx); 1094 } 1095 1096 static void dw100_hw_reset(struct dw100_device *dw_dev) 1097 { 1098 u32 val; 1099 1100 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1101 val |= DW100_DEWARP_CTRL_ENABLE; 1102 val |= DW100_DEWARP_CTRL_SOFT_RESET; 1103 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1104 val &= ~DW100_DEWARP_CTRL_SOFT_RESET; 1105 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1106 } 1107 1108 static void _dw100_hw_set_master_bus_enable(struct dw100_device *dw_dev, 1109 unsigned int enable) 1110 { 1111 u32 val; 1112 1113 dev_dbg(&dw_dev->pdev->dev, "%sable master bus\n", 1114 enable ? "En" : "Dis"); 1115 1116 val = dw100_read(dw_dev, DW100_BUS_CTRL); 1117 1118 if (enable) 1119 val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE; 1120 else 1121 val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE; 1122 1123 dw100_write(dw_dev, DW100_BUS_CTRL, val); 1124 } 1125 1126 static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev) 1127 { 1128 _dw100_hw_set_master_bus_enable(dw_dev, 1); 1129 } 1130 1131 static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev) 1132 { 1133 _dw100_hw_set_master_bus_enable(dw_dev, 0); 1134 } 1135 1136 static void dw100_hw_dewarp_start(struct dw100_device *dw_dev) 1137 { 1138 u32 val; 1139 1140 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1141 1142 dev_dbg(&dw_dev->pdev->dev, "Starting Hardware CTRL:0x%08x\n", val); 1143 dw100_write(dw_dev, DW100_DEWARP_CTRL, val | DW100_DEWARP_CTRL_START); 1144 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1145 } 1146 1147 static void dw100_hw_init_ctrl(struct dw100_device *dw_dev) 1148 { 1149 u32 val; 1150 /* 1151 * Input format YUV422_SP 1152 * Output format YUV422_SP 1153 * No hardware handshake (SW) 1154 * No automatic double src buffering (Single) 1155 * No automatic double dst buffering (Single) 1156 * No Black Line 1157 * Prefetch image pixel traversal 1158 */ 1159 1160 val = DW100_DEWARP_CTRL_ENABLE 1161 /* Valid only for auto prefetch mode*/ 1162 | DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32); 1163 1164 /* 1165 * Calculation mode required to support any scaling factor, 1166 * but x4 slower than traversal mode. 1167 * 1168 * DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL 1169 * DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION 1170 * DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO 1171 * 1172 * TODO: Find heuristics requiring calculation mode 1173 */ 1174 val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION; 1175 1176 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1177 } 1178 1179 static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev) 1180 { 1181 u32 val; 1182 1183 val = DW100_BOUNDARY_PIXEL_V(128) 1184 | DW100_BOUNDARY_PIXEL_U(128) 1185 | DW100_BOUNDARY_PIXEL_Y(0); 1186 1187 dw100_write(dw_dev, DW100_BOUNDARY_PIXEL, val); 1188 } 1189 1190 static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale) 1191 { 1192 dev_dbg(&dw_dev->pdev->dev, "Setting scale factor to %u\n", scale); 1193 1194 dw100_write(dw_dev, DW100_SCALE_FACTOR, scale); 1195 } 1196 1197 static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y) 1198 { 1199 u32 val; 1200 1201 dev_dbg(&dw_dev->pdev->dev, "Setting ROI region to %u.%u\n", x, y); 1202 1203 val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y); 1204 1205 dw100_write(dw_dev, DW100_ROI_START, val); 1206 } 1207 1208 static void dw100_hw_set_src_crop(struct dw100_device *dw_dev, 1209 const struct dw100_q_data *src_q_data, 1210 const struct dw100_q_data *dst_q_data) 1211 { 1212 const struct v4l2_rect *rect = &src_q_data->crop; 1213 u32 src_scale, qscale, left_scale, top_scale; 1214 1215 /* HW Scale is UQ1.7 encoded */ 1216 src_scale = (rect->width << 7) / src_q_data->pix_fmt.width; 1217 dw100_hw_set_scale(dw_dev, src_scale); 1218 1219 qscale = (dst_q_data->pix_fmt.width << 7) / src_q_data->pix_fmt.width; 1220 1221 left_scale = ((rect->left << 7) * qscale) >> 14; 1222 top_scale = ((rect->top << 7) * qscale) >> 14; 1223 1224 dw100_hw_set_roi(dw_dev, left_scale, top_scale); 1225 } 1226 1227 static void dw100_hw_set_source(struct dw100_device *dw_dev, 1228 const struct dw100_q_data *q_data, 1229 struct vb2_buffer *buffer) 1230 { 1231 u32 width, height, stride, fourcc, val; 1232 const struct dw100_fmt *fmt = q_data->fmt; 1233 dma_addr_t addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0); 1234 dma_addr_t addr_uv; 1235 1236 width = q_data->pix_fmt.width; 1237 height = q_data->pix_fmt.height; 1238 stride = q_data->pix_fmt.plane_fmt[0].bytesperline; 1239 fourcc = q_data->fmt->fourcc; 1240 1241 if (q_data->pix_fmt.num_planes == 2) 1242 addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1); 1243 else 1244 addr_uv = addr_y + (stride * height); 1245 1246 dev_dbg(&dw_dev->pdev->dev, 1247 "Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n", 1248 width, height, stride, &fourcc, &addr_y); 1249 1250 /* Pixel Format */ 1251 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1252 1253 val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK; 1254 val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format); 1255 1256 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1257 1258 /* Swap */ 1259 val = dw100_read(dw_dev, DW100_SWAP_CONTROL); 1260 1261 val &= ~DW100_SWAP_CONTROL_SRC_MASK; 1262 /* 1263 * Data swapping is performed only on Y plane for source image. 1264 */ 1265 if (fmt->reg_swap_uv && 1266 fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) 1267 val |= DW100_SWAP_CONTROL_SRC(DW100_SWAP_CONTROL_Y 1268 (DW100_SWAP_CONTROL_BYTE)); 1269 1270 dw100_write(dw_dev, DW100_SWAP_CONTROL, val); 1271 1272 /* Image resolution */ 1273 dw100_write(dw_dev, DW100_SRC_IMG_SIZE, 1274 DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height)); 1275 1276 dw100_write(dw_dev, DW100_SRC_IMG_STRIDE, stride); 1277 1278 /* Buffers */ 1279 dw100_write(dw_dev, DW100_SRC_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y)); 1280 dw100_write(dw_dev, DW100_SRC_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv)); 1281 } 1282 1283 static void dw100_hw_set_destination(struct dw100_device *dw_dev, 1284 const struct dw100_q_data *q_data, 1285 const struct dw100_fmt *ifmt, 1286 struct vb2_buffer *buffer) 1287 { 1288 u32 width, height, stride, fourcc, val, size_y, size_uv; 1289 const struct dw100_fmt *fmt = q_data->fmt; 1290 dma_addr_t addr_y, addr_uv; 1291 1292 width = q_data->pix_fmt.width; 1293 height = q_data->pix_fmt.height; 1294 stride = q_data->pix_fmt.plane_fmt[0].bytesperline; 1295 fourcc = fmt->fourcc; 1296 1297 addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0); 1298 size_y = q_data->pix_fmt.plane_fmt[0].sizeimage; 1299 1300 if (q_data->pix_fmt.num_planes == 2) { 1301 addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1); 1302 size_uv = q_data->pix_fmt.plane_fmt[1].sizeimage; 1303 } else { 1304 addr_uv = addr_y + ALIGN(stride * height, 16); 1305 size_uv = size_y; 1306 if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP) 1307 size_uv /= 2; 1308 } 1309 1310 dev_dbg(&dw_dev->pdev->dev, 1311 "Set HW destination registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n", 1312 width, height, stride, &fourcc, &addr_y); 1313 1314 /* Pixel Format */ 1315 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1316 1317 val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK; 1318 val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format); 1319 1320 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1321 1322 /* Swap */ 1323 val = dw100_read(dw_dev, DW100_SWAP_CONTROL); 1324 1325 val &= ~DW100_SWAP_CONTROL_DST_MASK; 1326 1327 /* 1328 * Avoid to swap twice 1329 */ 1330 if (fmt->reg_swap_uv ^ 1331 (ifmt->reg_swap_uv && ifmt->reg_format != 1332 DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) { 1333 if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) 1334 val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_Y 1335 (DW100_SWAP_CONTROL_BYTE)); 1336 else 1337 val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_UV 1338 (DW100_SWAP_CONTROL_BYTE)); 1339 } 1340 1341 dw100_write(dw_dev, DW100_SWAP_CONTROL, val); 1342 1343 /* Image resolution */ 1344 dw100_write(dw_dev, DW100_DST_IMG_SIZE, 1345 DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height)); 1346 dw100_write(dw_dev, DW100_DST_IMG_STRIDE, stride); 1347 dw100_write(dw_dev, DW100_DST_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y)); 1348 dw100_write(dw_dev, DW100_DST_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv)); 1349 dw100_write(dw_dev, DW100_DST_IMG_Y_SIZE1, DW100_DST_IMG_Y_SIZE(size_y)); 1350 dw100_write(dw_dev, DW100_DST_IMG_UV_SIZE1, 1351 DW100_DST_IMG_UV_SIZE(size_uv)); 1352 } 1353 1354 static void dw100_hw_set_mapping(struct dw100_device *dw_dev, dma_addr_t addr, 1355 u32 width, u32 height) 1356 { 1357 dev_dbg(&dw_dev->pdev->dev, 1358 "Set HW mapping registers for %ux%u addr:%pad", 1359 width, height, &addr); 1360 1361 dw100_write(dw_dev, DW100_MAP_LUT_ADDR, DW100_MAP_LUT_ADDR_ADDR(addr)); 1362 dw100_write(dw_dev, DW100_MAP_LUT_SIZE, DW100_MAP_LUT_SIZE_WIDTH(width) 1363 | DW100_MAP_LUT_SIZE_HEIGHT(height)); 1364 } 1365 1366 static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq) 1367 { 1368 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 1369 DW100_INTERRUPT_STATUS_INT_CLEAR(irq)); 1370 } 1371 1372 static void dw100_hw_enable_irq(struct dw100_device *dw_dev) 1373 { 1374 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 1375 DW100_INTERRUPT_STATUS_INT_ENABLE_MASK); 1376 } 1377 1378 static void dw100_hw_disable_irq(struct dw100_device *dw_dev) 1379 { 1380 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 0); 1381 } 1382 1383 static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev) 1384 { 1385 u32 val; 1386 1387 val = dw100_read(dw_dev, DW100_INTERRUPT_STATUS); 1388 1389 return DW100_INTERRUPT_STATUS_INT_STATUS(val); 1390 } 1391 1392 static irqreturn_t dw100_irq_handler(int irq, void *dev_id) 1393 { 1394 struct dw100_device *dw_dev = dev_id; 1395 u32 pending_irqs, err_irqs, frame_done_irq; 1396 bool with_error = true; 1397 1398 pending_irqs = dw_hw_get_pending_irqs(dw_dev); 1399 frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE; 1400 err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs); 1401 1402 if (frame_done_irq) { 1403 dev_dbg(&dw_dev->pdev->dev, "Frame done interrupt\n"); 1404 with_error = false; 1405 err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS 1406 (DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE); 1407 } 1408 1409 if (err_irqs) 1410 dev_err(&dw_dev->pdev->dev, "Interrupt error: %#x\n", err_irqs); 1411 1412 dw100_hw_disable_irq(dw_dev); 1413 dw100_hw_master_bus_disable(dw_dev); 1414 dw100_hw_clear_irq(dw_dev, pending_irqs | 1415 DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT); 1416 1417 dw100_job_finish(dw_dev, with_error); 1418 1419 return IRQ_HANDLED; 1420 } 1421 1422 static void dw100_start(struct dw100_ctx *ctx, struct vb2_v4l2_buffer *in_vb, 1423 struct vb2_v4l2_buffer *out_vb) 1424 { 1425 struct dw100_device *dw_dev = ctx->dw_dev; 1426 1427 out_vb->sequence = 1428 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)->sequence++; 1429 in_vb->sequence = 1430 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)->sequence++; 1431 1432 dev_dbg(&ctx->dw_dev->pdev->dev, 1433 "Starting queues %p->%p, sequence %u->%u\n", 1434 v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 1435 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE), 1436 v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 1437 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE), 1438 in_vb->sequence, out_vb->sequence); 1439 1440 v4l2_m2m_buf_copy_metadata(in_vb, out_vb, true); 1441 1442 /* Now, let's deal with hardware ... */ 1443 dw100_hw_master_bus_disable(dw_dev); 1444 dw100_hw_init_ctrl(dw_dev); 1445 dw100_hw_set_pixel_boundary(dw_dev); 1446 dw100_hw_set_src_crop(dw_dev, &ctx->q_data[DW100_QUEUE_SRC], 1447 &ctx->q_data[DW100_QUEUE_DST]); 1448 dw100_hw_set_source(dw_dev, &ctx->q_data[DW100_QUEUE_SRC], 1449 &in_vb->vb2_buf); 1450 dw100_hw_set_destination(dw_dev, &ctx->q_data[DW100_QUEUE_DST], 1451 ctx->q_data[DW100_QUEUE_SRC].fmt, 1452 &out_vb->vb2_buf); 1453 dw100_hw_set_mapping(dw_dev, ctx->map_dma, 1454 ctx->map_width, ctx->map_height); 1455 dw100_hw_enable_irq(dw_dev); 1456 dw100_hw_dewarp_start(dw_dev); 1457 1458 /* Enable Bus */ 1459 dw100_hw_master_bus_enable(dw_dev); 1460 } 1461 1462 static void dw100_device_run(void *priv) 1463 { 1464 struct dw100_ctx *ctx = priv; 1465 struct vb2_v4l2_buffer *src_buf, *dst_buf; 1466 1467 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 1468 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 1469 1470 dw100_start(ctx, src_buf, dst_buf); 1471 } 1472 1473 static const struct v4l2_m2m_ops dw100_m2m_ops = { 1474 .device_run = dw100_device_run, 1475 }; 1476 1477 static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev) 1478 { 1479 struct video_device *vfd = &dw_dev->vfd; 1480 1481 vfd->vfl_dir = VFL_DIR_M2M; 1482 vfd->fops = &dw100_fops; 1483 vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; 1484 vfd->ioctl_ops = &dw100_ioctl_ops; 1485 vfd->minor = -1; 1486 vfd->release = video_device_release_empty; 1487 vfd->v4l2_dev = &dw_dev->v4l2_dev; 1488 vfd->lock = &dw_dev->vfd_mutex; 1489 1490 strscpy(vfd->name, DRV_NAME, sizeof(vfd->name)); 1491 mutex_init(vfd->lock); 1492 video_set_drvdata(vfd, dw_dev); 1493 1494 return vfd; 1495 } 1496 1497 static int dw100_dump_regs_show(struct seq_file *m, void *private) 1498 { 1499 struct dw100_device *dw_dev = m->private; 1500 int ret; 1501 1502 ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev); 1503 if (ret < 0) 1504 return ret; 1505 1506 ret = dw100_dump_regs(m); 1507 1508 pm_runtime_put_sync(&dw_dev->pdev->dev); 1509 1510 return ret; 1511 } 1512 DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs); 1513 1514 static void dw100_debugfs_init(struct dw100_device *dw_dev) 1515 { 1516 dw_dev->debugfs_root = 1517 debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL); 1518 1519 debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev, 1520 &dw100_dump_regs_fops); 1521 } 1522 1523 static void dw100_debugfs_exit(struct dw100_device *dw_dev) 1524 { 1525 debugfs_remove_recursive(dw_dev->debugfs_root); 1526 } 1527 1528 static int dw100_probe(struct platform_device *pdev) 1529 { 1530 struct dw100_device *dw_dev; 1531 struct video_device *vfd; 1532 int ret, irq; 1533 1534 dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL); 1535 if (!dw_dev) 1536 return -ENOMEM; 1537 dw_dev->pdev = pdev; 1538 1539 ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks); 1540 if (ret < 0) { 1541 dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret); 1542 return ret; 1543 } 1544 dw_dev->num_clks = ret; 1545 1546 dw_dev->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1547 if (IS_ERR(dw_dev->mmio)) 1548 return PTR_ERR(dw_dev->mmio); 1549 1550 irq = platform_get_irq(pdev, 0); 1551 if (irq < 0) 1552 return irq; 1553 1554 platform_set_drvdata(pdev, dw_dev); 1555 1556 pm_runtime_enable(&pdev->dev); 1557 ret = pm_runtime_resume_and_get(&pdev->dev); 1558 if (ret < 0) { 1559 dev_err(&pdev->dev, "Unable to resume the device: %d\n", ret); 1560 goto err_pm; 1561 } 1562 1563 pm_runtime_put_sync(&pdev->dev); 1564 1565 ret = devm_request_irq(&pdev->dev, irq, dw100_irq_handler, IRQF_ONESHOT, 1566 dev_name(&pdev->dev), dw_dev); 1567 if (ret < 0) { 1568 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 1569 goto err_pm; 1570 } 1571 1572 ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev); 1573 if (ret) 1574 goto err_pm; 1575 1576 vfd = dw100_init_video_device(dw_dev); 1577 1578 dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops); 1579 if (IS_ERR(dw_dev->m2m_dev)) { 1580 dev_err(&pdev->dev, "Failed to init mem2mem device\n"); 1581 ret = PTR_ERR(dw_dev->m2m_dev); 1582 goto err_v4l2; 1583 } 1584 1585 dw_dev->mdev.dev = &pdev->dev; 1586 strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model)); 1587 media_device_init(&dw_dev->mdev); 1588 dw_dev->v4l2_dev.mdev = &dw_dev->mdev; 1589 1590 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); 1591 if (ret) { 1592 dev_err(&pdev->dev, "Failed to register video device\n"); 1593 goto err_m2m; 1594 } 1595 1596 ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd, 1597 MEDIA_ENT_F_PROC_VIDEO_SCALER); 1598 if (ret) { 1599 dev_err(&pdev->dev, "Failed to init mem2mem media controller\n"); 1600 goto error_v4l2; 1601 } 1602 1603 ret = media_device_register(&dw_dev->mdev); 1604 if (ret) { 1605 dev_err(&pdev->dev, "Failed to register mem2mem media device\n"); 1606 goto error_m2m_mc; 1607 } 1608 1609 dw100_debugfs_init(dw_dev); 1610 1611 dev_info(&pdev->dev, 1612 "dw100 v4l2 m2m registered as /dev/video%u\n", vfd->num); 1613 1614 return 0; 1615 1616 error_m2m_mc: 1617 v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); 1618 error_v4l2: 1619 video_unregister_device(vfd); 1620 err_m2m: 1621 media_device_cleanup(&dw_dev->mdev); 1622 v4l2_m2m_release(dw_dev->m2m_dev); 1623 err_v4l2: 1624 v4l2_device_unregister(&dw_dev->v4l2_dev); 1625 err_pm: 1626 pm_runtime_disable(&pdev->dev); 1627 1628 return ret; 1629 } 1630 1631 static void dw100_remove(struct platform_device *pdev) 1632 { 1633 struct dw100_device *dw_dev = platform_get_drvdata(pdev); 1634 1635 dw100_debugfs_exit(dw_dev); 1636 1637 pm_runtime_disable(&pdev->dev); 1638 1639 media_device_unregister(&dw_dev->mdev); 1640 v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); 1641 media_device_cleanup(&dw_dev->mdev); 1642 1643 video_unregister_device(&dw_dev->vfd); 1644 mutex_destroy(dw_dev->vfd.lock); 1645 v4l2_m2m_release(dw_dev->m2m_dev); 1646 v4l2_device_unregister(&dw_dev->v4l2_dev); 1647 } 1648 1649 static int __maybe_unused dw100_runtime_suspend(struct device *dev) 1650 { 1651 struct dw100_device *dw_dev = dev_get_drvdata(dev); 1652 1653 clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks); 1654 1655 return 0; 1656 } 1657 1658 static int __maybe_unused dw100_runtime_resume(struct device *dev) 1659 { 1660 int ret; 1661 struct dw100_device *dw_dev = dev_get_drvdata(dev); 1662 1663 ret = clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks); 1664 1665 if (ret) 1666 return ret; 1667 1668 dw100_hw_reset(dw_dev); 1669 1670 return 0; 1671 } 1672 1673 static const struct dev_pm_ops dw100_pm = { 1674 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1675 pm_runtime_force_resume) 1676 SET_RUNTIME_PM_OPS(dw100_runtime_suspend, 1677 dw100_runtime_resume, NULL) 1678 }; 1679 1680 static const struct of_device_id dw100_dt_ids[] = { 1681 { .compatible = "nxp,imx8mp-dw100", .data = NULL }, 1682 { }, 1683 }; 1684 MODULE_DEVICE_TABLE(of, dw100_dt_ids); 1685 1686 static struct platform_driver dw100_driver = { 1687 .probe = dw100_probe, 1688 .remove = dw100_remove, 1689 .driver = { 1690 .name = DRV_NAME, 1691 .pm = &dw100_pm, 1692 .of_match_table = dw100_dt_ids, 1693 }, 1694 }; 1695 1696 module_platform_driver(dw100_driver); 1697 1698 MODULE_DESCRIPTION("DW100 Hardware dewarper"); 1699 MODULE_AUTHOR("Xavier Roumegue <Xavier.Roumegue@oss.nxp.com>"); 1700 MODULE_LICENSE("GPL"); 1701