1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NVIDIA Tegra Video decoder driver 4 * 5 * Copyright (C) 2019-2022 Dmitry Osipenko <digetx@gmail.com> 6 * 7 * Based on Cedrus driver by Bootlin. 8 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> 9 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 10 * 11 * Based on Rockchip driver by Collabora. 12 * Copyright (C) 2019 Boris Brezillon <boris.brezillon@collabora.com> 13 */ 14 15 #include <linux/err.h> 16 #include <linux/slab.h> 17 18 #include "vde.h" 19 20 static const struct v4l2_ctrl_config ctrl_cfgs[] = { 21 { .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, }, 22 { .id = V4L2_CID_STATELESS_H264_SPS, }, 23 { .id = V4L2_CID_STATELESS_H264_PPS, }, 24 { 25 .id = V4L2_CID_STATELESS_H264_DECODE_MODE, 26 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 27 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 28 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 29 }, 30 { 31 .id = V4L2_CID_STATELESS_H264_START_CODE, 32 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 33 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 34 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 35 }, 36 { 37 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, 38 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 39 .max = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 40 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 41 }, 42 { 43 .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, 44 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, 45 .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 46 }, 47 }; 48 49 static inline struct tegra_ctx *fh_to_tegra_ctx(struct v4l2_fh *fh) 50 { 51 return container_of(fh, struct tegra_ctx, fh); 52 } 53 54 static void tegra_set_control_data(struct tegra_ctx *ctx, void *data, u32 id) 55 { 56 switch (id) { 57 case V4L2_CID_STATELESS_H264_DECODE_PARAMS: 58 ctx->h264.decode_params = data; 59 break; 60 case V4L2_CID_STATELESS_H264_SPS: 61 ctx->h264.sps = data; 62 break; 63 case V4L2_CID_STATELESS_H264_PPS: 64 ctx->h264.pps = data; 65 break; 66 } 67 } 68 69 void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id) 70 { 71 unsigned int i; 72 73 for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) { 74 if (ctx->ctrls[i]->id == id) { 75 tegra_set_control_data(ctx, ctx->ctrls[i]->p_cur.p, id); 76 return; 77 } 78 } 79 80 tegra_set_control_data(ctx, NULL, id); 81 } 82 83 static int tegra_queue_setup(struct vb2_queue *vq, 84 unsigned int *nbufs, 85 unsigned int *num_planes, 86 unsigned int sizes[], 87 struct device *alloc_devs[]) 88 { 89 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 90 struct v4l2_format *f; 91 unsigned int i; 92 93 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 94 f = &ctx->coded_fmt; 95 else 96 f = &ctx->decoded_fmt; 97 98 if (*num_planes) { 99 if (*num_planes != f->fmt.pix_mp.num_planes) 100 return -EINVAL; 101 102 for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { 103 if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage) 104 return -EINVAL; 105 } 106 } else { 107 *num_planes = f->fmt.pix_mp.num_planes; 108 109 for (i = 0; i < f->fmt.pix_mp.num_planes; i++) 110 sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage; 111 } 112 113 return 0; 114 } 115 116 static int tegra_buf_out_validate(struct vb2_buffer *vb) 117 { 118 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 119 120 vbuf->field = V4L2_FIELD_NONE; 121 return 0; 122 } 123 124 static void __tegra_buf_cleanup(struct vb2_buffer *vb, unsigned int i) 125 { 126 struct vb2_queue *vq = vb->vb2_queue; 127 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 128 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 129 130 while (i--) { 131 if (tb->a[i]) { 132 tegra_vde_dmabuf_cache_unmap(ctx->vde, tb->a[i], true); 133 tb->a[i] = NULL; 134 } 135 136 if (tb->iova[i]) { 137 tegra_vde_iommu_unmap(ctx->vde, tb->iova[i]); 138 tb->iova[i] = NULL; 139 } 140 } 141 142 if (tb->aux) { 143 tegra_vde_free_bo(tb->aux); 144 tb->aux = NULL; 145 } 146 } 147 148 static int tegra_buf_init(struct vb2_buffer *vb) 149 { 150 struct vb2_queue *vq = vb->vb2_queue; 151 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 152 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 153 struct tegra_vde *vde = ctx->vde; 154 enum dma_data_direction dma_dir; 155 struct sg_table *sgt; 156 unsigned int i; 157 int err; 158 159 if (V4L2_TYPE_IS_CAPTURE(vq->type) && vb->num_planes > 1) { 160 /* 161 * Tegra decoder writes auxiliary data for I/P frames. 162 * This data is needed for decoding of B frames. 163 */ 164 err = tegra_vde_alloc_bo(vde, &tb->aux, DMA_FROM_DEVICE, 165 vb2_plane_size(vb, 1)); 166 if (err) 167 return err; 168 } 169 170 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 171 dma_dir = DMA_TO_DEVICE; 172 else 173 dma_dir = DMA_FROM_DEVICE; 174 175 for (i = 0; i < vb->num_planes; i++) { 176 if (vq->memory == VB2_MEMORY_DMABUF) { 177 get_dma_buf(vb->planes[i].dbuf); 178 179 err = tegra_vde_dmabuf_cache_map(vde, vb->planes[i].dbuf, 180 dma_dir, &tb->a[i], 181 &tb->dma_base[i]); 182 if (err) { 183 dma_buf_put(vb->planes[i].dbuf); 184 goto cleanup; 185 } 186 187 continue; 188 } 189 190 if (vde->domain) { 191 sgt = vb2_dma_sg_plane_desc(vb, i); 192 193 err = tegra_vde_iommu_map(vde, sgt, &tb->iova[i], 194 vb2_plane_size(vb, i)); 195 if (err) 196 goto cleanup; 197 198 tb->dma_base[i] = iova_dma_addr(&vde->iova, tb->iova[i]); 199 } else { 200 tb->dma_base[i] = vb2_dma_contig_plane_dma_addr(vb, i); 201 } 202 } 203 204 return 0; 205 206 cleanup: 207 __tegra_buf_cleanup(vb, i); 208 209 return err; 210 } 211 212 static void tegra_buf_cleanup(struct vb2_buffer *vb) 213 { 214 __tegra_buf_cleanup(vb, vb->num_planes); 215 } 216 217 static int tegra_buf_prepare(struct vb2_buffer *vb) 218 { 219 struct vb2_queue *vq = vb->vb2_queue; 220 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 221 struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); 222 size_t hw_align, hw_size, hw_payload, size, offset; 223 struct v4l2_pix_format_mplane *pixfmt; 224 unsigned int i; 225 void *vb_data; 226 227 if (V4L2_TYPE_IS_OUTPUT(vq->type)) { 228 hw_align = BSEV_ALIGN; 229 pixfmt = &ctx->coded_fmt.fmt.pix_mp; 230 } else { 231 hw_align = FRAMEID_ALIGN; 232 pixfmt = &ctx->decoded_fmt.fmt.pix_mp; 233 } 234 235 for (i = 0; i < vb->num_planes; i++) { 236 offset = vb->planes[i].data_offset; 237 238 if (offset & (hw_align - 1)) 239 return -EINVAL; 240 241 if (V4L2_TYPE_IS_CAPTURE(vq->type)) { 242 size = pixfmt->plane_fmt[i].sizeimage; 243 hw_payload = ALIGN(size, VDE_ATOM); 244 } else { 245 size = vb2_get_plane_payload(vb, i) - offset; 246 hw_payload = ALIGN(size + VDE_ATOM, SXE_BUFFER); 247 } 248 249 hw_size = offset + hw_payload; 250 251 if (vb2_plane_size(vb, i) < hw_size) 252 return -EINVAL; 253 254 vb2_set_plane_payload(vb, i, hw_payload); 255 256 if (V4L2_TYPE_IS_OUTPUT(vq->type)) { 257 vb_data = vb2_plane_vaddr(vb, i); 258 259 /* 260 * Hardware requires zero-padding of coded data. 261 * Otherwise it will fail to parse the trailing 262 * data and abort the decoding. 263 */ 264 if (vb_data) 265 memset(vb_data + offset + size, 0, 266 hw_size - offset - size); 267 } 268 269 tb->dma_addr[i] = tb->dma_base[i] + offset; 270 } 271 272 switch (pixfmt->pixelformat) { 273 case V4L2_PIX_FMT_YVU420M: 274 swap(tb->dma_addr[1], tb->dma_addr[2]); 275 break; 276 } 277 278 return 0; 279 } 280 281 static void tegra_buf_queue(struct vb2_buffer *vb) 282 { 283 struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 284 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 285 286 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 287 } 288 289 static void tegra_buf_request_complete(struct vb2_buffer *vb) 290 { 291 struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 292 293 v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl); 294 } 295 296 static int tegra_start_streaming(struct vb2_queue *vq, unsigned int count) 297 { 298 return 0; 299 } 300 301 static void tegra_stop_streaming(struct vb2_queue *vq) 302 { 303 struct tegra_ctx *ctx = vb2_get_drv_priv(vq); 304 305 while (true) { 306 struct vb2_v4l2_buffer *vbuf; 307 308 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 309 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 310 else 311 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 312 313 if (!vbuf) 314 break; 315 316 v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, &ctx->hdl); 317 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); 318 } 319 } 320 321 static const struct vb2_ops tegra_qops = { 322 .queue_setup = tegra_queue_setup, 323 .buf_init = tegra_buf_init, 324 .buf_cleanup = tegra_buf_cleanup, 325 .buf_prepare = tegra_buf_prepare, 326 .buf_queue = tegra_buf_queue, 327 .buf_out_validate = tegra_buf_out_validate, 328 .buf_request_complete = tegra_buf_request_complete, 329 .start_streaming = tegra_start_streaming, 330 .stop_streaming = tegra_stop_streaming, 331 }; 332 333 static int tegra_queue_init(void *priv, 334 struct vb2_queue *src_vq, 335 struct vb2_queue *dst_vq) 336 { 337 struct tegra_ctx *ctx = priv; 338 struct tegra_vde *vde = ctx->vde; 339 const struct vb2_mem_ops *mem_ops; 340 unsigned long dma_attrs; 341 int err; 342 343 /* 344 * TODO: Switch to use of vb2_dma_contig_memops uniformly once we 345 * will add IOMMU_DOMAIN support for video decoder to tegra-smmu 346 * driver. For now we need to stick with SG ops in order to be able 347 * to get SGT table easily. This is suboptimal since SG mappings are 348 * wasting CPU cache and we don't need that caching. 349 */ 350 if (vde->domain) 351 mem_ops = &vb2_dma_sg_memops; 352 else 353 mem_ops = &vb2_dma_contig_memops; 354 355 dma_attrs = DMA_ATTR_WRITE_COMBINE; 356 357 src_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer); 358 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 359 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 360 src_vq->io_modes = VB2_DMABUF | VB2_MMAP; 361 src_vq->supports_requests = true; 362 src_vq->requires_requests = true; 363 src_vq->lock = &vde->v4l2_lock; 364 src_vq->dma_attrs = dma_attrs; 365 src_vq->mem_ops = mem_ops; 366 src_vq->ops = &tegra_qops; 367 src_vq->drv_priv = ctx; 368 src_vq->dev = vde->dev; 369 370 err = vb2_queue_init(src_vq); 371 if (err) { 372 v4l2_err(&vde->v4l2_dev, 373 "failed to initialize src queue: %d\n", err); 374 return err; 375 } 376 377 /* 378 * We may need to zero the end of bitstream in kernel if userspace 379 * doesn't do that, hence kmap is needed for the coded data. It's not 380 * needed for framebuffers. 381 */ 382 dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 383 384 dst_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer); 385 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 386 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 387 dst_vq->io_modes = VB2_DMABUF | VB2_MMAP; 388 dst_vq->lock = &vde->v4l2_lock; 389 dst_vq->dma_attrs = dma_attrs; 390 dst_vq->mem_ops = mem_ops; 391 dst_vq->ops = &tegra_qops; 392 dst_vq->drv_priv = ctx; 393 dst_vq->dev = vde->dev; 394 395 err = vb2_queue_init(dst_vq); 396 if (err) { 397 v4l2_err(&vde->v4l2_dev, 398 "failed to initialize dst queue: %d\n", err); 399 return err; 400 } 401 402 return 0; 403 } 404 405 static void tegra_reset_fmt(struct tegra_ctx *ctx, struct v4l2_format *f, 406 u32 fourcc) 407 { 408 memset(f, 0, sizeof(*f)); 409 f->fmt.pix_mp.pixelformat = fourcc; 410 f->fmt.pix_mp.field = V4L2_FIELD_NONE; 411 f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; 412 f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 413 f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; 414 f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; 415 } 416 417 static void tegra_reset_coded_fmt(struct tegra_ctx *ctx) 418 { 419 const struct tegra_vde_soc *soc = ctx->vde->soc; 420 struct v4l2_format *f = &ctx->coded_fmt; 421 422 ctx->coded_fmt_desc = &soc->coded_fmts[0]; 423 tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); 424 425 f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 426 f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width; 427 f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height; 428 } 429 430 static void tegra_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, 431 u32 pixelformat, u32 width, u32 height) 432 { 433 const struct v4l2_format_info *info = v4l2_format_info(pixelformat); 434 struct v4l2_plane_pix_format *plane; 435 unsigned int i; 436 437 switch (pixelformat) { 438 case V4L2_PIX_FMT_YUV420M: 439 case V4L2_PIX_FMT_YVU420M: 440 pixfmt->width = width; 441 pixfmt->height = height; 442 pixfmt->pixelformat = pixelformat; 443 pixfmt->num_planes = info->mem_planes; 444 445 for (i = 0; i < pixfmt->num_planes; i++) { 446 unsigned int hdiv = (i == 0) ? 1 : 2; 447 unsigned int vdiv = (i == 0) ? 1 : 2; 448 449 /* 450 * VDE is connected to Graphics Memory using 128bit port, 451 * all memory accesses are made using 16B atoms. 452 * 453 * V4L requires Cb/Cr strides to be exactly half of the 454 * Y stride, hence we're aligning Y to 16B x 2. 455 */ 456 plane = &pixfmt->plane_fmt[i]; 457 plane->bytesperline = ALIGN(width, VDE_ATOM * 2) / hdiv; 458 plane->sizeimage = plane->bytesperline * height / vdiv; 459 } 460 461 break; 462 } 463 } 464 465 static void tegra_reset_decoded_fmt(struct tegra_ctx *ctx) 466 { 467 struct v4l2_format *f = &ctx->decoded_fmt; 468 469 tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); 470 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 471 tegra_fill_pixfmt_mp(&f->fmt.pix_mp, 472 ctx->coded_fmt_desc->decoded_fmts[0], 473 ctx->coded_fmt.fmt.pix_mp.width, 474 ctx->coded_fmt.fmt.pix_mp.height); 475 } 476 477 static void tegra_job_finish(struct tegra_ctx *ctx, 478 enum vb2_buffer_state result) 479 { 480 v4l2_m2m_buf_done_and_job_finish(ctx->vde->m2m, ctx->fh.m2m_ctx, 481 result); 482 } 483 484 static void tegra_decode_complete(struct work_struct *work) 485 { 486 struct tegra_ctx *ctx = container_of(work, struct tegra_ctx, work); 487 int err; 488 489 err = ctx->coded_fmt_desc->decode_wait(ctx); 490 if (err) 491 tegra_job_finish(ctx, VB2_BUF_STATE_ERROR); 492 else 493 tegra_job_finish(ctx, VB2_BUF_STATE_DONE); 494 } 495 496 static int tegra_querycap(struct file *file, void *priv, 497 struct v4l2_capability *cap) 498 { 499 strscpy(cap->bus_info, "platform:tegra-vde", sizeof(cap->bus_info)); 500 strscpy(cap->driver, "tegra-vde", sizeof(cap->driver)); 501 strscpy(cap->card, "tegra-vde", sizeof(cap->card)); 502 503 return 0; 504 } 505 506 static int tegra_enum_decoded_fmt(struct file *file, void *priv, 507 struct v4l2_fmtdesc *f) 508 { 509 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 510 511 if (WARN_ON(!ctx->coded_fmt_desc)) 512 return -EINVAL; 513 514 if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) 515 return -EINVAL; 516 517 f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index]; 518 519 return 0; 520 } 521 522 static int tegra_g_decoded_fmt(struct file *file, void *priv, 523 struct v4l2_format *f) 524 { 525 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 526 527 *f = ctx->decoded_fmt; 528 return 0; 529 } 530 531 static int tegra_try_decoded_fmt(struct file *file, void *priv, 532 struct v4l2_format *f) 533 { 534 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; 535 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 536 const struct tegra_coded_fmt_desc *coded_desc; 537 unsigned int i; 538 539 /* 540 * The codec context should point to a coded format desc, if the format 541 * on the coded end has not been set yet, it should point to the 542 * default value. 543 */ 544 coded_desc = ctx->coded_fmt_desc; 545 if (WARN_ON(!coded_desc)) 546 return -EINVAL; 547 548 if (!coded_desc->num_decoded_fmts) 549 return -EINVAL; 550 551 for (i = 0; i < coded_desc->num_decoded_fmts; i++) { 552 if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) 553 break; 554 } 555 556 if (i == coded_desc->num_decoded_fmts) 557 pix_mp->pixelformat = coded_desc->decoded_fmts[0]; 558 559 /* always apply the frmsize constraint of the coded end */ 560 v4l2_apply_frmsize_constraints(&pix_mp->width, 561 &pix_mp->height, 562 &coded_desc->frmsize); 563 564 tegra_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, 565 pix_mp->width, pix_mp->height); 566 pix_mp->field = V4L2_FIELD_NONE; 567 568 return 0; 569 } 570 571 static int tegra_s_decoded_fmt(struct file *file, void *priv, 572 struct v4l2_format *f) 573 { 574 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 575 struct vb2_queue *vq; 576 int err; 577 578 /* change not allowed if queue is busy */ 579 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 580 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 581 if (vb2_is_busy(vq)) 582 return -EBUSY; 583 584 err = tegra_try_decoded_fmt(file, priv, f); 585 if (err) 586 return err; 587 588 ctx->decoded_fmt = *f; 589 590 return 0; 591 } 592 593 static int tegra_enum_coded_fmt(struct file *file, void *priv, 594 struct v4l2_fmtdesc *f) 595 { 596 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 597 const struct tegra_vde_soc *soc = ctx->vde->soc; 598 599 if (f->index >= soc->num_coded_fmts) 600 return -EINVAL; 601 602 f->pixelformat = soc->coded_fmts[f->index].fourcc; 603 604 return 0; 605 } 606 607 static int tegra_g_coded_fmt(struct file *file, void *priv, 608 struct v4l2_format *f) 609 { 610 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 611 612 *f = ctx->coded_fmt; 613 return 0; 614 } 615 616 static const struct tegra_coded_fmt_desc * 617 tegra_find_coded_fmt_desc(struct tegra_ctx *ctx, u32 fourcc) 618 { 619 const struct tegra_vde_soc *soc = ctx->vde->soc; 620 unsigned int i; 621 622 for (i = 0; i < soc->num_coded_fmts; i++) { 623 if (soc->coded_fmts[i].fourcc == fourcc) 624 return &soc->coded_fmts[i]; 625 } 626 627 return NULL; 628 } 629 630 static int tegra_try_coded_fmt(struct file *file, void *priv, 631 struct v4l2_format *f) 632 { 633 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; 634 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 635 const struct tegra_vde_soc *soc = ctx->vde->soc; 636 int size = pix_mp->plane_fmt[0].sizeimage; 637 const struct tegra_coded_fmt_desc *desc; 638 639 desc = tegra_find_coded_fmt_desc(ctx, pix_mp->pixelformat); 640 if (!desc) { 641 pix_mp->pixelformat = soc->coded_fmts[0].fourcc; 642 desc = &soc->coded_fmts[0]; 643 } 644 645 v4l2_apply_frmsize_constraints(&pix_mp->width, 646 &pix_mp->height, 647 &desc->frmsize); 648 649 pix_mp->plane_fmt[0].sizeimage = max(ALIGN(size, SXE_BUFFER), SZ_2M); 650 pix_mp->field = V4L2_FIELD_NONE; 651 pix_mp->num_planes = 1; 652 653 return 0; 654 } 655 656 static int tegra_s_coded_fmt(struct file *file, void *priv, 657 struct v4l2_format *f) 658 { 659 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 660 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 661 const struct tegra_coded_fmt_desc *desc; 662 struct vb2_queue *peer_vq, *vq; 663 struct v4l2_format *cap_fmt; 664 int err; 665 666 /* 667 * In order to support dynamic resolution change, the decoder admits 668 * a resolution change, as long as the pixelformat remains. Can't be 669 * done if streaming. 670 */ 671 vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 672 if (vb2_is_streaming(vq) || 673 (vb2_is_busy(vq) && 674 f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat)) 675 return -EBUSY; 676 677 /* 678 * Since format change on the OUTPUT queue will reset the CAPTURE 679 * queue, we can't allow doing so when the CAPTURE queue has buffers 680 * allocated. 681 */ 682 peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 683 if (vb2_is_busy(peer_vq)) 684 return -EBUSY; 685 686 err = tegra_try_coded_fmt(file, priv, f); 687 if (err) 688 return err; 689 690 desc = tegra_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat); 691 if (!desc) 692 return -EINVAL; 693 694 ctx->coded_fmt_desc = desc; 695 ctx->coded_fmt = *f; 696 697 /* 698 * Current decoded format might have become invalid with newly 699 * selected codec, so reset it to default just to be safe and 700 * keep internal driver state sane. User is mandated to set 701 * the decoded format again after we return, so we don't need 702 * anything smarter. 703 * 704 * Note that this will propagates any size changes to the decoded format. 705 */ 706 tegra_reset_decoded_fmt(ctx); 707 708 /* propagate colorspace information to capture */ 709 cap_fmt = &ctx->decoded_fmt; 710 cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func; 711 cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; 712 cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace; 713 cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization; 714 715 return 0; 716 } 717 718 static int tegra_enum_framesizes(struct file *file, void *priv, 719 struct v4l2_frmsizeenum *fsize) 720 { 721 struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); 722 const struct tegra_coded_fmt_desc *fmt; 723 724 if (fsize->index) 725 return -EINVAL; 726 727 fmt = tegra_find_coded_fmt_desc(ctx, fsize->pixel_format); 728 if (!fmt) 729 return -EINVAL; 730 731 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 732 fsize->stepwise = fmt->frmsize; 733 734 return 0; 735 } 736 737 static const struct v4l2_ioctl_ops tegra_v4l2_ioctl_ops = { 738 .vidioc_querycap = tegra_querycap, 739 .vidioc_enum_framesizes = tegra_enum_framesizes, 740 741 .vidioc_try_fmt_vid_out_mplane = tegra_try_coded_fmt, 742 .vidioc_g_fmt_vid_out_mplane = tegra_g_coded_fmt, 743 .vidioc_s_fmt_vid_out_mplane = tegra_s_coded_fmt, 744 .vidioc_enum_fmt_vid_out = tegra_enum_coded_fmt, 745 746 .vidioc_try_fmt_vid_cap_mplane = tegra_try_decoded_fmt, 747 .vidioc_g_fmt_vid_cap_mplane = tegra_g_decoded_fmt, 748 .vidioc_s_fmt_vid_cap_mplane = tegra_s_decoded_fmt, 749 .vidioc_enum_fmt_vid_cap = tegra_enum_decoded_fmt, 750 751 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 752 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 753 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 754 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 755 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 756 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 757 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 758 759 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 760 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 761 762 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 763 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 764 }; 765 766 static int tegra_init_ctrls(struct tegra_ctx *ctx) 767 { 768 unsigned int i; 769 int err; 770 771 err = v4l2_ctrl_handler_init(&ctx->hdl, ARRAY_SIZE(ctrl_cfgs)); 772 if (err) 773 return err; 774 775 for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) { 776 ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->hdl, &ctrl_cfgs[i], 777 NULL); 778 if (ctx->hdl.error) { 779 err = ctx->hdl.error; 780 goto free_ctrls; 781 } 782 } 783 784 err = v4l2_ctrl_handler_setup(&ctx->hdl); 785 if (err) 786 goto free_ctrls; 787 788 ctx->fh.ctrl_handler = &ctx->hdl; 789 790 return 0; 791 792 free_ctrls: 793 v4l2_ctrl_handler_free(&ctx->hdl); 794 795 return err; 796 } 797 798 static int tegra_init_m2m(struct tegra_ctx *ctx) 799 { 800 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ctx->vde->m2m, 801 ctx, tegra_queue_init); 802 if (IS_ERR(ctx->fh.m2m_ctx)) 803 return PTR_ERR(ctx->fh.m2m_ctx); 804 805 return 0; 806 } 807 808 static int tegra_open(struct file *file) 809 { 810 struct tegra_vde *vde = video_drvdata(file); 811 struct tegra_ctx *ctx; 812 int err; 813 814 ctx = kzalloc(struct_size(ctx, ctrls, ARRAY_SIZE(ctrl_cfgs)), 815 GFP_KERNEL); 816 if (!ctx) 817 return -ENOMEM; 818 819 ctx->vde = vde; 820 v4l2_fh_init(&ctx->fh, video_devdata(file)); 821 INIT_WORK(&ctx->work, tegra_decode_complete); 822 823 err = tegra_init_ctrls(ctx); 824 if (err) { 825 v4l2_err(&vde->v4l2_dev, "failed to add controls: %d\n", err); 826 goto free_ctx; 827 } 828 829 err = tegra_init_m2m(ctx); 830 if (err) { 831 v4l2_err(&vde->v4l2_dev, "failed to initialize m2m: %d\n", err); 832 goto free_ctrls; 833 } 834 835 file->private_data = &ctx->fh; 836 v4l2_fh_add(&ctx->fh); 837 838 tegra_reset_coded_fmt(ctx); 839 tegra_try_coded_fmt(file, file->private_data, &ctx->coded_fmt); 840 841 tegra_reset_decoded_fmt(ctx); 842 tegra_try_decoded_fmt(file, file->private_data, &ctx->decoded_fmt); 843 844 return 0; 845 846 free_ctrls: 847 v4l2_ctrl_handler_free(&ctx->hdl); 848 free_ctx: 849 kfree(ctx); 850 851 return err; 852 } 853 854 static int tegra_release(struct file *file) 855 { 856 struct v4l2_fh *fh = file->private_data; 857 struct tegra_ctx *ctx = fh_to_tegra_ctx(fh); 858 struct tegra_vde *vde = ctx->vde; 859 860 v4l2_fh_del(fh); 861 v4l2_m2m_ctx_release(fh->m2m_ctx); 862 v4l2_ctrl_handler_free(&ctx->hdl); 863 v4l2_fh_exit(fh); 864 kfree(ctx); 865 866 tegra_vde_dmabuf_cache_unmap_sync(vde); 867 868 return 0; 869 } 870 871 static const struct v4l2_file_operations tegra_v4l2_fops = { 872 .owner = THIS_MODULE, 873 .open = tegra_open, 874 .poll = v4l2_m2m_fop_poll, 875 .mmap = v4l2_m2m_fop_mmap, 876 .release = tegra_release, 877 .unlocked_ioctl = video_ioctl2, 878 }; 879 880 static void tegra_device_run(void *priv) 881 { 882 struct tegra_ctx *ctx = priv; 883 struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 884 struct media_request *src_req = src->vb2_buf.req_obj.req; 885 int err; 886 887 v4l2_ctrl_request_setup(src_req, &ctx->hdl); 888 889 err = ctx->coded_fmt_desc->decode_run(ctx); 890 891 v4l2_ctrl_request_complete(src_req, &ctx->hdl); 892 893 if (err) 894 tegra_job_finish(ctx, VB2_BUF_STATE_ERROR); 895 else 896 queue_work(ctx->vde->wq, &ctx->work); 897 } 898 899 static const struct v4l2_m2m_ops tegra_v4l2_m2m_ops = { 900 .device_run = tegra_device_run, 901 }; 902 903 static int tegra_request_validate(struct media_request *req) 904 { 905 unsigned int count; 906 907 count = vb2_request_buffer_cnt(req); 908 if (!count) 909 return -ENOENT; 910 else if (count > 1) 911 return -EINVAL; 912 913 return vb2_request_validate(req); 914 } 915 916 static const struct media_device_ops tegra_media_device_ops = { 917 .req_validate = tegra_request_validate, 918 .req_queue = v4l2_m2m_request_queue, 919 }; 920 921 int tegra_vde_v4l2_init(struct tegra_vde *vde) 922 { 923 struct device *dev = vde->dev; 924 int err; 925 926 mutex_init(&vde->v4l2_lock); 927 media_device_init(&vde->mdev); 928 video_set_drvdata(&vde->vdev, vde); 929 930 vde->vdev.lock = &vde->v4l2_lock; 931 vde->vdev.fops = &tegra_v4l2_fops; 932 vde->vdev.vfl_dir = VFL_DIR_M2M; 933 vde->vdev.release = video_device_release_empty; 934 vde->vdev.v4l2_dev = &vde->v4l2_dev; 935 vde->vdev.ioctl_ops = &tegra_v4l2_ioctl_ops; 936 vde->vdev.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; 937 938 vde->v4l2_dev.mdev = &vde->mdev; 939 vde->mdev.ops = &tegra_media_device_ops; 940 vde->mdev.dev = dev; 941 942 strscpy(vde->mdev.model, "tegra-vde", sizeof(vde->mdev.model)); 943 strscpy(vde->vdev.name, "tegra-vde", sizeof(vde->vdev.name)); 944 strscpy(vde->mdev.bus_info, "platform:tegra-vde", 945 sizeof(vde->mdev.bus_info)); 946 947 vde->wq = create_workqueue("tegra-vde"); 948 if (!vde->wq) 949 return -ENOMEM; 950 951 err = media_device_register(&vde->mdev); 952 if (err) { 953 dev_err(dev, "failed to register media device: %d\n", err); 954 goto clean_up_media_device; 955 } 956 957 err = v4l2_device_register(dev, &vde->v4l2_dev); 958 if (err) { 959 dev_err(dev, "failed to register v4l2 device: %d\n", err); 960 goto unreg_media_device; 961 } 962 963 err = video_register_device(&vde->vdev, VFL_TYPE_VIDEO, -1); 964 if (err) { 965 dev_err(dev, "failed to register video device: %d\n", err); 966 goto unreg_v4l2; 967 } 968 969 vde->m2m = v4l2_m2m_init(&tegra_v4l2_m2m_ops); 970 err = PTR_ERR_OR_ZERO(vde->m2m); 971 if (err) { 972 dev_err(dev, "failed to initialize m2m device: %d\n", err); 973 goto unreg_video_device; 974 } 975 976 err = v4l2_m2m_register_media_controller(vde->m2m, &vde->vdev, 977 MEDIA_ENT_F_PROC_VIDEO_DECODER); 978 if (err) { 979 dev_err(dev, "failed to register media controller: %d\n", err); 980 goto release_m2m; 981 } 982 983 v4l2_info(&vde->v4l2_dev, "v4l2 device registered as /dev/video%d\n", 984 vde->vdev.num); 985 986 return 0; 987 988 release_m2m: 989 v4l2_m2m_release(vde->m2m); 990 unreg_video_device: 991 video_unregister_device(&vde->vdev); 992 unreg_v4l2: 993 v4l2_device_unregister(&vde->v4l2_dev); 994 unreg_media_device: 995 media_device_unregister(&vde->mdev); 996 clean_up_media_device: 997 media_device_cleanup(&vde->mdev); 998 999 destroy_workqueue(vde->wq); 1000 1001 return err; 1002 } 1003 1004 void tegra_vde_v4l2_deinit(struct tegra_vde *vde) 1005 { 1006 v4l2_m2m_unregister_media_controller(vde->m2m); 1007 v4l2_m2m_release(vde->m2m); 1008 1009 video_unregister_device(&vde->vdev); 1010 v4l2_device_unregister(&vde->v4l2_dev); 1011 1012 media_device_unregister(&vde->mdev); 1013 media_device_cleanup(&vde->mdev); 1014 1015 destroy_workqueue(vde->wq); 1016 } 1017