1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Microchip Image Sensor Controller (ISC) common driver base 4 * 5 * Copyright (C) 2016-2019 Microchip Technology, Inc. 6 * 7 * Author: Songjun Wu 8 * Author: Eugen Hristev <eugen.hristev@microchip.com> 9 * 10 */ 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/math64.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/videodev2.h> 21 #include <linux/atmel-isc-media.h> 22 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-event.h> 26 #include <media/v4l2-image-sizes.h> 27 #include <media/v4l2-ioctl.h> 28 #include <media/v4l2-fwnode.h> 29 #include <media/v4l2-subdev.h> 30 #include <media/videobuf2-dma-contig.h> 31 32 #include "microchip-isc-regs.h" 33 #include "microchip-isc.h" 34 35 #define ISC_IS_FORMAT_RAW(mbus_code) \ 36 (((mbus_code) & 0xf000) == 0x3000) 37 38 #define ISC_IS_FORMAT_GREY(mbus_code) \ 39 (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \ 40 (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8))) 41 42 static inline void isc_update_v4l2_ctrls(struct isc_device *isc) 43 { 44 struct isc_ctrls *ctrls = &isc->ctrls; 45 46 /* In here we set the v4l2 controls w.r.t. our pipeline config */ 47 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]); 48 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]); 49 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]); 50 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]); 51 52 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]); 53 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]); 54 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]); 55 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]); 56 } 57 58 static inline void isc_update_awb_ctrls(struct isc_device *isc) 59 { 60 struct isc_ctrls *ctrls = &isc->ctrls; 61 62 /* In here we set our actual hw pipeline config */ 63 64 regmap_write(isc->regmap, ISC_WB_O_RGR, 65 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | 66 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); 67 regmap_write(isc->regmap, ISC_WB_O_BGB, 68 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | 69 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); 70 regmap_write(isc->regmap, ISC_WB_G_RGR, 71 ctrls->gain[ISC_HIS_CFG_MODE_R] | 72 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); 73 regmap_write(isc->regmap, ISC_WB_G_BGB, 74 ctrls->gain[ISC_HIS_CFG_MODE_B] | 75 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); 76 } 77 78 static inline void isc_reset_awb_ctrls(struct isc_device *isc) 79 { 80 unsigned int c; 81 82 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) { 83 /* gains have a fixed point at 9 decimals */ 84 isc->ctrls.gain[c] = 1 << 9; 85 /* offsets are in 2's complements */ 86 isc->ctrls.offset[c] = 0; 87 } 88 } 89 90 static int isc_queue_setup(struct vb2_queue *vq, 91 unsigned int *nbuffers, unsigned int *nplanes, 92 unsigned int sizes[], struct device *alloc_devs[]) 93 { 94 struct isc_device *isc = vb2_get_drv_priv(vq); 95 unsigned int size = isc->fmt.fmt.pix.sizeimage; 96 97 if (*nplanes) 98 return sizes[0] < size ? -EINVAL : 0; 99 100 *nplanes = 1; 101 sizes[0] = size; 102 103 return 0; 104 } 105 106 static int isc_buffer_prepare(struct vb2_buffer *vb) 107 { 108 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 109 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); 110 unsigned long size = isc->fmt.fmt.pix.sizeimage; 111 112 if (vb2_plane_size(vb, 0) < size) { 113 dev_err(isc->dev, "buffer too small (%lu < %lu)\n", 114 vb2_plane_size(vb, 0), size); 115 return -EINVAL; 116 } 117 118 vb2_set_plane_payload(vb, 0, size); 119 120 vbuf->field = isc->fmt.fmt.pix.field; 121 122 return 0; 123 } 124 125 static void isc_crop_pfe(struct isc_device *isc) 126 { 127 struct regmap *regmap = isc->regmap; 128 u32 h, w; 129 130 h = isc->fmt.fmt.pix.height; 131 w = isc->fmt.fmt.pix.width; 132 133 /* 134 * In case the sensor is not RAW, it will output a pixel (12-16 bits) 135 * with two samples on the ISC Data bus (which is 8-12) 136 * ISC will count each sample, so, we need to multiply these values 137 * by two, to get the real number of samples for the required pixels. 138 */ 139 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) { 140 h <<= 1; 141 w <<= 1; 142 } 143 144 /* 145 * We limit the column/row count that the ISC will output according 146 * to the configured resolution that we want. 147 * This will avoid the situation where the sensor is misconfigured, 148 * sending more data, and the ISC will just take it and DMA to memory, 149 * causing corruption. 150 */ 151 regmap_write(regmap, ISC_PFE_CFG1, 152 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) | 153 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK)); 154 155 regmap_write(regmap, ISC_PFE_CFG2, 156 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) | 157 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK)); 158 159 regmap_update_bits(regmap, ISC_PFE_CFG0, 160 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN, 161 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); 162 } 163 164 static void isc_start_dma(struct isc_device *isc) 165 { 166 struct regmap *regmap = isc->regmap; 167 u32 sizeimage = isc->fmt.fmt.pix.sizeimage; 168 u32 dctrl_dview; 169 dma_addr_t addr0; 170 171 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); 172 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); 173 174 switch (isc->config.fourcc) { 175 case V4L2_PIX_FMT_YUV420: 176 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, 177 addr0 + (sizeimage * 2) / 3); 178 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, 179 addr0 + (sizeimage * 5) / 6); 180 break; 181 case V4L2_PIX_FMT_YUV422P: 182 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, 183 addr0 + sizeimage / 2); 184 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, 185 addr0 + (sizeimage * 3) / 4); 186 break; 187 default: 188 break; 189 } 190 191 dctrl_dview = isc->config.dctrl_dview; 192 193 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, 194 dctrl_dview | ISC_DCTRL_IE_IS); 195 spin_lock(&isc->awb_lock); 196 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); 197 spin_unlock(&isc->awb_lock); 198 } 199 200 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) 201 { 202 struct regmap *regmap = isc->regmap; 203 struct isc_ctrls *ctrls = &isc->ctrls; 204 u32 val, bay_cfg; 205 const u32 *gamma; 206 unsigned int i; 207 208 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ 209 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { 210 val = pipeline & BIT(i) ? 1 : 0; 211 regmap_field_write(isc->pipeline[i], val); 212 } 213 214 if (!pipeline) 215 return; 216 217 bay_cfg = isc->config.sd_format->cfa_baycfg; 218 219 regmap_write(regmap, ISC_WB_CFG, bay_cfg); 220 isc_update_awb_ctrls(isc); 221 isc_update_v4l2_ctrls(isc); 222 223 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); 224 225 gamma = &isc->gamma_table[ctrls->gamma_index][0]; 226 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); 227 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); 228 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); 229 230 isc->config_dpc(isc); 231 isc->config_csc(isc); 232 isc->config_cbc(isc); 233 isc->config_cc(isc); 234 isc->config_gam(isc); 235 } 236 237 static int isc_update_profile(struct isc_device *isc) 238 { 239 struct regmap *regmap = isc->regmap; 240 u32 sr; 241 int counter = 100; 242 243 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO); 244 245 regmap_read(regmap, ISC_CTRLSR, &sr); 246 while ((sr & ISC_CTRL_UPPRO) && counter--) { 247 usleep_range(1000, 2000); 248 regmap_read(regmap, ISC_CTRLSR, &sr); 249 } 250 251 if (counter < 0) { 252 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n"); 253 return -ETIMEDOUT; 254 } 255 256 return 0; 257 } 258 259 static void isc_set_histogram(struct isc_device *isc, bool enable) 260 { 261 struct regmap *regmap = isc->regmap; 262 struct isc_ctrls *ctrls = &isc->ctrls; 263 264 if (enable) { 265 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, 266 ISC_HIS_CFG_MODE_GR | 267 (isc->config.sd_format->cfa_baycfg 268 << ISC_HIS_CFG_BAYSEL_SHIFT) | 269 ISC_HIS_CFG_RAR); 270 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, 271 ISC_HIS_CTRL_EN); 272 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); 273 ctrls->hist_id = ISC_HIS_CFG_MODE_GR; 274 isc_update_profile(isc); 275 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); 276 277 ctrls->hist_stat = HIST_ENABLED; 278 } else { 279 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); 280 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, 281 ISC_HIS_CTRL_DIS); 282 283 ctrls->hist_stat = HIST_DISABLED; 284 } 285 } 286 287 static int isc_configure(struct isc_device *isc) 288 { 289 struct regmap *regmap = isc->regmap; 290 u32 pfe_cfg0, dcfg, mask, pipeline; 291 struct isc_subdev_entity *subdev = isc->current_subdev; 292 293 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; 294 pipeline = isc->config.bits_pipeline; 295 296 dcfg = isc->config.dcfg_imode | isc->dcfg; 297 298 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; 299 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | 300 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | 301 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | 302 ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; 303 304 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); 305 306 isc->config_rlp(isc); 307 308 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); 309 310 /* Set the pipeline */ 311 isc_set_pipeline(isc, pipeline); 312 313 /* 314 * The current implemented histogram is available for RAW R, B, GB, GR 315 * channels. We need to check if sensor is outputting RAW BAYER 316 */ 317 if (isc->ctrls.awb && 318 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) 319 isc_set_histogram(isc, true); 320 else 321 isc_set_histogram(isc, false); 322 323 /* Update profile */ 324 return isc_update_profile(isc); 325 } 326 327 static int isc_prepare_streaming(struct vb2_queue *vq) 328 { 329 struct isc_device *isc = vb2_get_drv_priv(vq); 330 331 return media_pipeline_start(isc->video_dev.entity.pads, &isc->mpipe); 332 } 333 334 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count) 335 { 336 struct isc_device *isc = vb2_get_drv_priv(vq); 337 struct regmap *regmap = isc->regmap; 338 struct isc_buffer *buf; 339 unsigned long flags; 340 int ret; 341 342 /* Enable stream on the sub device */ 343 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1); 344 if (ret && ret != -ENOIOCTLCMD) { 345 dev_err(isc->dev, "stream on failed in subdev %d\n", ret); 346 goto err_start_stream; 347 } 348 349 ret = pm_runtime_resume_and_get(isc->dev); 350 if (ret < 0) { 351 dev_err(isc->dev, "RPM resume failed in subdev %d\n", 352 ret); 353 goto err_pm_get; 354 } 355 356 ret = isc_configure(isc); 357 if (unlikely(ret)) 358 goto err_configure; 359 360 /* Enable DMA interrupt */ 361 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE); 362 363 spin_lock_irqsave(&isc->dma_queue_lock, flags); 364 365 isc->sequence = 0; 366 isc->stop = false; 367 reinit_completion(&isc->comp); 368 369 isc->cur_frm = list_first_entry(&isc->dma_queue, 370 struct isc_buffer, list); 371 list_del(&isc->cur_frm->list); 372 373 isc_crop_pfe(isc); 374 isc_start_dma(isc); 375 376 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 377 378 /* if we streaming from RAW, we can do one-shot white balance adj */ 379 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) 380 v4l2_ctrl_activate(isc->do_wb_ctrl, true); 381 382 return 0; 383 384 err_configure: 385 pm_runtime_put_sync(isc->dev); 386 err_pm_get: 387 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); 388 389 err_start_stream: 390 spin_lock_irqsave(&isc->dma_queue_lock, flags); 391 list_for_each_entry(buf, &isc->dma_queue, list) 392 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); 393 INIT_LIST_HEAD(&isc->dma_queue); 394 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 395 396 return ret; 397 } 398 399 static void isc_unprepare_streaming(struct vb2_queue *vq) 400 { 401 struct isc_device *isc = vb2_get_drv_priv(vq); 402 403 /* Stop media pipeline */ 404 media_pipeline_stop(isc->video_dev.entity.pads); 405 } 406 407 static void isc_stop_streaming(struct vb2_queue *vq) 408 { 409 struct isc_device *isc = vb2_get_drv_priv(vq); 410 unsigned long flags; 411 struct isc_buffer *buf; 412 int ret; 413 414 mutex_lock(&isc->awb_mutex); 415 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 416 417 isc->stop = true; 418 419 /* Wait until the end of the current frame */ 420 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ)) 421 dev_err(isc->dev, "Timeout waiting for end of the capture\n"); 422 423 mutex_unlock(&isc->awb_mutex); 424 425 /* Disable DMA interrupt */ 426 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); 427 428 pm_runtime_put_sync(isc->dev); 429 430 /* Disable stream on the sub device */ 431 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); 432 if (ret && ret != -ENOIOCTLCMD) 433 dev_err(isc->dev, "stream off failed in subdev\n"); 434 435 /* Release all active buffers */ 436 spin_lock_irqsave(&isc->dma_queue_lock, flags); 437 if (unlikely(isc->cur_frm)) { 438 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf, 439 VB2_BUF_STATE_ERROR); 440 isc->cur_frm = NULL; 441 } 442 list_for_each_entry(buf, &isc->dma_queue, list) 443 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 444 INIT_LIST_HEAD(&isc->dma_queue); 445 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 446 } 447 448 static void isc_buffer_queue(struct vb2_buffer *vb) 449 { 450 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 451 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb); 452 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue); 453 unsigned long flags; 454 455 spin_lock_irqsave(&isc->dma_queue_lock, flags); 456 if (!isc->cur_frm && list_empty(&isc->dma_queue) && 457 vb2_start_streaming_called(vb->vb2_queue)) { 458 isc->cur_frm = buf; 459 isc_start_dma(isc); 460 } else { 461 list_add_tail(&buf->list, &isc->dma_queue); 462 } 463 spin_unlock_irqrestore(&isc->dma_queue_lock, flags); 464 } 465 466 static const struct vb2_ops isc_vb2_ops = { 467 .queue_setup = isc_queue_setup, 468 .wait_prepare = vb2_ops_wait_prepare, 469 .wait_finish = vb2_ops_wait_finish, 470 .buf_prepare = isc_buffer_prepare, 471 .start_streaming = isc_start_streaming, 472 .stop_streaming = isc_stop_streaming, 473 .buf_queue = isc_buffer_queue, 474 .prepare_streaming = isc_prepare_streaming, 475 .unprepare_streaming = isc_unprepare_streaming, 476 }; 477 478 static int isc_querycap(struct file *file, void *priv, 479 struct v4l2_capability *cap) 480 { 481 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); 482 strscpy(cap->card, "Microchip Image Sensor Controller", sizeof(cap->card)); 483 484 return 0; 485 } 486 487 static int isc_enum_fmt_vid_cap(struct file *file, void *priv, 488 struct v4l2_fmtdesc *f) 489 { 490 struct isc_device *isc = video_drvdata(file); 491 u32 index = f->index; 492 u32 i, supported_index = 0; 493 struct isc_format *fmt; 494 495 /* 496 * If we are not asked a specific mbus_code, we have to report all 497 * the formats that we can output. 498 */ 499 if (!f->mbus_code) { 500 if (index >= isc->controller_formats_size) 501 return -EINVAL; 502 503 f->pixelformat = isc->controller_formats[index].fourcc; 504 505 return 0; 506 } 507 508 /* 509 * If a specific mbus_code is requested, check if we support 510 * this mbus_code as input for the ISC. 511 * If it's supported, then we report the corresponding pixelformat 512 * as first possible option for the ISC. 513 * E.g. mbus MEDIA_BUS_FMT_YUYV8_2X8 and report 514 * 'YUYV' (YUYV 4:2:2) 515 */ 516 fmt = isc_find_format_by_code(isc, f->mbus_code, &i); 517 if (!fmt) 518 return -EINVAL; 519 520 if (!index) { 521 f->pixelformat = fmt->fourcc; 522 523 return 0; 524 } 525 526 supported_index++; 527 528 /* If the index is not raw, we don't have anymore formats to report */ 529 if (!ISC_IS_FORMAT_RAW(f->mbus_code)) 530 return -EINVAL; 531 532 /* 533 * We are asked for a specific mbus code, which is raw. 534 * We have to search through the formats we can convert to. 535 * We have to skip the raw formats, we cannot convert to raw. 536 * E.g. 'AR12' (16-bit ARGB 4-4-4-4), 'AR15' (16-bit ARGB 1-5-5-5), etc. 537 */ 538 for (i = 0; i < isc->controller_formats_size; i++) { 539 if (isc->controller_formats[i].raw) 540 continue; 541 if (index == supported_index) { 542 f->pixelformat = isc->controller_formats[i].fourcc; 543 return 0; 544 } 545 supported_index++; 546 } 547 548 return -EINVAL; 549 } 550 551 static int isc_g_fmt_vid_cap(struct file *file, void *priv, 552 struct v4l2_format *fmt) 553 { 554 struct isc_device *isc = video_drvdata(file); 555 556 *fmt = isc->fmt; 557 558 return 0; 559 } 560 561 /* 562 * Checks the current configured format, if ISC can output it, 563 * considering which type of format the ISC receives from the sensor 564 */ 565 static int isc_try_validate_formats(struct isc_device *isc) 566 { 567 int ret; 568 bool bayer = false, yuv = false, rgb = false, grey = false; 569 570 /* all formats supported by the RLP module are OK */ 571 switch (isc->try_config.fourcc) { 572 case V4L2_PIX_FMT_SBGGR8: 573 case V4L2_PIX_FMT_SGBRG8: 574 case V4L2_PIX_FMT_SGRBG8: 575 case V4L2_PIX_FMT_SRGGB8: 576 case V4L2_PIX_FMT_SBGGR10: 577 case V4L2_PIX_FMT_SGBRG10: 578 case V4L2_PIX_FMT_SGRBG10: 579 case V4L2_PIX_FMT_SRGGB10: 580 case V4L2_PIX_FMT_SBGGR12: 581 case V4L2_PIX_FMT_SGBRG12: 582 case V4L2_PIX_FMT_SGRBG12: 583 case V4L2_PIX_FMT_SRGGB12: 584 ret = 0; 585 bayer = true; 586 break; 587 588 case V4L2_PIX_FMT_YUV420: 589 case V4L2_PIX_FMT_YUV422P: 590 case V4L2_PIX_FMT_YUYV: 591 case V4L2_PIX_FMT_UYVY: 592 case V4L2_PIX_FMT_VYUY: 593 ret = 0; 594 yuv = true; 595 break; 596 597 case V4L2_PIX_FMT_RGB565: 598 case V4L2_PIX_FMT_ABGR32: 599 case V4L2_PIX_FMT_XBGR32: 600 case V4L2_PIX_FMT_ARGB444: 601 case V4L2_PIX_FMT_ARGB555: 602 ret = 0; 603 rgb = true; 604 break; 605 case V4L2_PIX_FMT_GREY: 606 case V4L2_PIX_FMT_Y10: 607 case V4L2_PIX_FMT_Y16: 608 ret = 0; 609 grey = true; 610 break; 611 default: 612 /* any other different formats are not supported */ 613 dev_err(isc->dev, "Requested unsupported format.\n"); 614 ret = -EINVAL; 615 } 616 dev_dbg(isc->dev, 617 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n", 618 rgb, yuv, grey, bayer); 619 620 if (bayer && 621 !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 622 dev_err(isc->dev, "Cannot output RAW if we do not receive RAW.\n"); 623 return -EINVAL; 624 } 625 626 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) && 627 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) { 628 dev_err(isc->dev, "Cannot output GREY if we do not receive RAW/GREY.\n"); 629 return -EINVAL; 630 } 631 632 if ((rgb || bayer || yuv) && 633 ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) { 634 dev_err(isc->dev, "Cannot convert GREY to another format.\n"); 635 return -EINVAL; 636 } 637 638 return ret; 639 } 640 641 /* 642 * Configures the RLP and DMA modules, depending on the output format 643 * configured for the ISC. 644 * If direct_dump == true, just dump raw data 8/16 bits depending on format. 645 */ 646 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) 647 { 648 isc->try_config.rlp_cfg_mode = 0; 649 650 switch (isc->try_config.fourcc) { 651 case V4L2_PIX_FMT_SBGGR8: 652 case V4L2_PIX_FMT_SGBRG8: 653 case V4L2_PIX_FMT_SGRBG8: 654 case V4L2_PIX_FMT_SRGGB8: 655 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; 656 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; 657 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 658 isc->try_config.bpp = 8; 659 isc->try_config.bpp_v4l2 = 8; 660 break; 661 case V4L2_PIX_FMT_SBGGR10: 662 case V4L2_PIX_FMT_SGBRG10: 663 case V4L2_PIX_FMT_SGRBG10: 664 case V4L2_PIX_FMT_SRGGB10: 665 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10; 666 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 667 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 668 isc->try_config.bpp = 16; 669 isc->try_config.bpp_v4l2 = 16; 670 break; 671 case V4L2_PIX_FMT_SBGGR12: 672 case V4L2_PIX_FMT_SGBRG12: 673 case V4L2_PIX_FMT_SGRBG12: 674 case V4L2_PIX_FMT_SRGGB12: 675 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12; 676 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 677 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 678 isc->try_config.bpp = 16; 679 isc->try_config.bpp_v4l2 = 16; 680 break; 681 case V4L2_PIX_FMT_RGB565: 682 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565; 683 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 684 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 685 isc->try_config.bpp = 16; 686 isc->try_config.bpp_v4l2 = 16; 687 break; 688 case V4L2_PIX_FMT_ARGB444: 689 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444; 690 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 691 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 692 isc->try_config.bpp = 16; 693 isc->try_config.bpp_v4l2 = 16; 694 break; 695 case V4L2_PIX_FMT_ARGB555: 696 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555; 697 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 698 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 699 isc->try_config.bpp = 16; 700 isc->try_config.bpp_v4l2 = 16; 701 break; 702 case V4L2_PIX_FMT_ABGR32: 703 case V4L2_PIX_FMT_XBGR32: 704 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32; 705 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 706 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 707 isc->try_config.bpp = 32; 708 isc->try_config.bpp_v4l2 = 32; 709 break; 710 case V4L2_PIX_FMT_YUV420: 711 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; 712 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P; 713 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; 714 isc->try_config.bpp = 12; 715 isc->try_config.bpp_v4l2 = 8; /* only first plane */ 716 break; 717 case V4L2_PIX_FMT_YUV422P: 718 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; 719 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P; 720 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR; 721 isc->try_config.bpp = 16; 722 isc->try_config.bpp_v4l2 = 8; /* only first plane */ 723 break; 724 case V4L2_PIX_FMT_YUYV: 725 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; 726 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 727 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 728 isc->try_config.bpp = 16; 729 isc->try_config.bpp_v4l2 = 16; 730 break; 731 case V4L2_PIX_FMT_UYVY: 732 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; 733 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 734 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 735 isc->try_config.bpp = 16; 736 isc->try_config.bpp_v4l2 = 16; 737 break; 738 case V4L2_PIX_FMT_VYUY: 739 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; 740 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; 741 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 742 isc->try_config.bpp = 16; 743 isc->try_config.bpp_v4l2 = 16; 744 break; 745 case V4L2_PIX_FMT_GREY: 746 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8; 747 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; 748 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 749 isc->try_config.bpp = 8; 750 isc->try_config.bpp_v4l2 = 8; 751 break; 752 case V4L2_PIX_FMT_Y16: 753 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; 754 fallthrough; 755 case V4L2_PIX_FMT_Y10: 756 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; 757 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; 758 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 759 isc->try_config.bpp = 16; 760 isc->try_config.bpp_v4l2 = 16; 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 if (direct_dump) { 767 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8; 768 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8; 769 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; 770 return 0; 771 } 772 773 return 0; 774 } 775 776 /* 777 * Configuring pipeline modules, depending on which format the ISC outputs 778 * and considering which format it has as input from the sensor. 779 */ 780 static int isc_try_configure_pipeline(struct isc_device *isc) 781 { 782 switch (isc->try_config.fourcc) { 783 case V4L2_PIX_FMT_RGB565: 784 case V4L2_PIX_FMT_ARGB555: 785 case V4L2_PIX_FMT_ARGB444: 786 case V4L2_PIX_FMT_ABGR32: 787 case V4L2_PIX_FMT_XBGR32: 788 /* if sensor format is RAW, we convert inside ISC */ 789 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 790 isc->try_config.bits_pipeline = CFA_ENABLE | 791 WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | 792 CC_ENABLE; 793 } else { 794 isc->try_config.bits_pipeline = 0x0; 795 } 796 break; 797 case V4L2_PIX_FMT_YUV420: 798 /* if sensor format is RAW, we convert inside ISC */ 799 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 800 isc->try_config.bits_pipeline = CFA_ENABLE | 801 CSC_ENABLE | GAM_ENABLES | WB_ENABLE | 802 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | 803 DPC_BLCENABLE; 804 } else { 805 isc->try_config.bits_pipeline = 0x0; 806 } 807 break; 808 case V4L2_PIX_FMT_YUV422P: 809 /* if sensor format is RAW, we convert inside ISC */ 810 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 811 isc->try_config.bits_pipeline = CFA_ENABLE | 812 CSC_ENABLE | WB_ENABLE | GAM_ENABLES | 813 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; 814 } else { 815 isc->try_config.bits_pipeline = 0x0; 816 } 817 break; 818 case V4L2_PIX_FMT_YUYV: 819 case V4L2_PIX_FMT_UYVY: 820 case V4L2_PIX_FMT_VYUY: 821 /* if sensor format is RAW, we convert inside ISC */ 822 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 823 isc->try_config.bits_pipeline = CFA_ENABLE | 824 CSC_ENABLE | WB_ENABLE | GAM_ENABLES | 825 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; 826 } else { 827 isc->try_config.bits_pipeline = 0x0; 828 } 829 break; 830 case V4L2_PIX_FMT_GREY: 831 case V4L2_PIX_FMT_Y16: 832 /* if sensor format is RAW, we convert inside ISC */ 833 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { 834 isc->try_config.bits_pipeline = CFA_ENABLE | 835 CSC_ENABLE | WB_ENABLE | GAM_ENABLES | 836 CBC_ENABLE | DPC_BLCENABLE; 837 } else { 838 isc->try_config.bits_pipeline = 0x0; 839 } 840 break; 841 default: 842 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) 843 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; 844 else 845 isc->try_config.bits_pipeline = 0x0; 846 } 847 848 /* Tune the pipeline to product specific */ 849 isc->adapt_pipeline(isc); 850 851 return 0; 852 } 853 854 static void isc_try_fse(struct isc_device *isc, 855 struct v4l2_subdev_state *sd_state) 856 { 857 struct v4l2_subdev_frame_size_enum fse = { 858 .which = V4L2_SUBDEV_FORMAT_TRY, 859 }; 860 int ret; 861 862 /* 863 * If we do not know yet which format the subdev is using, we cannot 864 * do anything. 865 */ 866 if (!isc->config.sd_format) 867 return; 868 869 fse.code = isc->try_config.sd_format->mbus_code; 870 871 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size, 872 sd_state, &fse); 873 /* 874 * Attempt to obtain format size from subdev. If not available, 875 * just use the maximum ISC can receive. 876 */ 877 if (ret) { 878 sd_state->pads->try_crop.width = isc->max_width; 879 sd_state->pads->try_crop.height = isc->max_height; 880 } else { 881 sd_state->pads->try_crop.width = fse.max_width; 882 sd_state->pads->try_crop.height = fse.max_height; 883 } 884 } 885 886 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f) 887 { 888 struct v4l2_pix_format *pixfmt = &f->fmt.pix; 889 unsigned int i; 890 891 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 892 return -EINVAL; 893 894 isc->try_config.fourcc = isc->controller_formats[0].fourcc; 895 896 /* find if the format requested is supported */ 897 for (i = 0; i < isc->controller_formats_size; i++) 898 if (isc->controller_formats[i].fourcc == pixfmt->pixelformat) { 899 isc->try_config.fourcc = pixfmt->pixelformat; 900 break; 901 } 902 903 isc_try_configure_rlp_dma(isc, false); 904 905 /* Limit to Microchip ISC hardware capabilities */ 906 v4l_bound_align_image(&pixfmt->width, 16, isc->max_width, 0, 907 &pixfmt->height, 16, isc->max_height, 0, 0); 908 /* If we did not find the requested format, we will fallback here */ 909 pixfmt->pixelformat = isc->try_config.fourcc; 910 pixfmt->colorspace = V4L2_COLORSPACE_SRGB; 911 pixfmt->field = V4L2_FIELD_NONE; 912 913 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3; 914 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) * 915 pixfmt->height; 916 917 isc->try_fmt = *f; 918 919 return 0; 920 } 921 922 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f) 923 { 924 isc_try_fmt(isc, f); 925 926 /* make the try configuration active */ 927 isc->config = isc->try_config; 928 isc->fmt = isc->try_fmt; 929 930 dev_dbg(isc->dev, "ISC set_fmt to %.4s @%dx%d\n", 931 (char *)&f->fmt.pix.pixelformat, 932 f->fmt.pix.width, f->fmt.pix.height); 933 934 return 0; 935 } 936 937 static int isc_validate(struct isc_device *isc) 938 { 939 int ret; 940 int i; 941 struct isc_format *sd_fmt = NULL; 942 struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix; 943 struct v4l2_subdev_format format = { 944 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 945 .pad = isc->remote_pad, 946 }; 947 struct v4l2_subdev_pad_config pad_cfg = {}; 948 struct v4l2_subdev_state pad_state = { 949 .pads = &pad_cfg, 950 }; 951 952 /* Get current format from subdev */ 953 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, get_fmt, NULL, 954 &format); 955 if (ret) 956 return ret; 957 958 /* Identify the subdev's format configuration */ 959 for (i = 0; i < isc->formats_list_size; i++) 960 if (isc->formats_list[i].mbus_code == format.format.code) { 961 sd_fmt = &isc->formats_list[i]; 962 break; 963 } 964 965 /* Check if the format is not supported */ 966 if (!sd_fmt) { 967 dev_err(isc->dev, 968 "Current subdevice is streaming a media bus code that is not supported 0x%x\n", 969 format.format.code); 970 return -EPIPE; 971 } 972 973 /* At this moment we know which format the subdev will use */ 974 isc->try_config.sd_format = sd_fmt; 975 976 /* If the sensor is not RAW, we can only do a direct dump */ 977 if (!ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) 978 isc_try_configure_rlp_dma(isc, true); 979 980 /* Limit to Microchip ISC hardware capabilities */ 981 v4l_bound_align_image(&format.format.width, 16, isc->max_width, 0, 982 &format.format.height, 16, isc->max_height, 0, 0); 983 984 /* Check if the frame size is the same. Otherwise we may overflow */ 985 if (pixfmt->height != format.format.height || 986 pixfmt->width != format.format.width) { 987 dev_err(isc->dev, 988 "ISC not configured with the proper frame size: %dx%d\n", 989 format.format.width, format.format.height); 990 return -EPIPE; 991 } 992 993 dev_dbg(isc->dev, 994 "Identified subdev using format %.4s with %dx%d %d bpp\n", 995 (char *)&sd_fmt->fourcc, pixfmt->width, pixfmt->height, 996 isc->try_config.bpp); 997 998 /* Reset and restart AWB if the subdevice changed the format */ 999 if (isc->try_config.sd_format && isc->config.sd_format && 1000 isc->try_config.sd_format != isc->config.sd_format) { 1001 isc->ctrls.hist_stat = HIST_INIT; 1002 isc_reset_awb_ctrls(isc); 1003 isc_update_v4l2_ctrls(isc); 1004 } 1005 1006 /* Validate formats */ 1007 ret = isc_try_validate_formats(isc); 1008 if (ret) 1009 return ret; 1010 1011 /* Obtain frame sizes if possible to have crop requirements ready */ 1012 isc_try_fse(isc, &pad_state); 1013 1014 /* Configure ISC pipeline for the config */ 1015 ret = isc_try_configure_pipeline(isc); 1016 if (ret) 1017 return ret; 1018 1019 isc->config = isc->try_config; 1020 1021 dev_dbg(isc->dev, "New ISC configuration in place\n"); 1022 1023 return 0; 1024 } 1025 1026 static int isc_s_fmt_vid_cap(struct file *file, void *priv, 1027 struct v4l2_format *f) 1028 { 1029 struct isc_device *isc = video_drvdata(file); 1030 1031 if (vb2_is_busy(&isc->vb2_vidq)) 1032 return -EBUSY; 1033 1034 return isc_set_fmt(isc, f); 1035 } 1036 1037 static int isc_try_fmt_vid_cap(struct file *file, void *priv, 1038 struct v4l2_format *f) 1039 { 1040 struct isc_device *isc = video_drvdata(file); 1041 1042 return isc_try_fmt(isc, f); 1043 } 1044 1045 static int isc_enum_input(struct file *file, void *priv, 1046 struct v4l2_input *inp) 1047 { 1048 if (inp->index != 0) 1049 return -EINVAL; 1050 1051 inp->type = V4L2_INPUT_TYPE_CAMERA; 1052 inp->std = 0; 1053 strscpy(inp->name, "Camera", sizeof(inp->name)); 1054 1055 return 0; 1056 } 1057 1058 static int isc_g_input(struct file *file, void *priv, unsigned int *i) 1059 { 1060 *i = 0; 1061 1062 return 0; 1063 } 1064 1065 static int isc_s_input(struct file *file, void *priv, unsigned int i) 1066 { 1067 if (i > 0) 1068 return -EINVAL; 1069 1070 return 0; 1071 } 1072 1073 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1074 { 1075 struct isc_device *isc = video_drvdata(file); 1076 1077 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a); 1078 } 1079 1080 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) 1081 { 1082 struct isc_device *isc = video_drvdata(file); 1083 1084 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a); 1085 } 1086 1087 static int isc_enum_framesizes(struct file *file, void *fh, 1088 struct v4l2_frmsizeenum *fsize) 1089 { 1090 struct isc_device *isc = video_drvdata(file); 1091 int ret = -EINVAL; 1092 int i; 1093 1094 if (fsize->index) 1095 return -EINVAL; 1096 1097 for (i = 0; i < isc->controller_formats_size; i++) 1098 if (isc->controller_formats[i].fourcc == fsize->pixel_format) 1099 ret = 0; 1100 1101 if (ret) 1102 return ret; 1103 1104 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; 1105 1106 fsize->stepwise.min_width = 16; 1107 fsize->stepwise.max_width = isc->max_width; 1108 fsize->stepwise.min_height = 16; 1109 fsize->stepwise.max_height = isc->max_height; 1110 fsize->stepwise.step_width = 1; 1111 fsize->stepwise.step_height = 1; 1112 1113 return 0; 1114 } 1115 1116 static const struct v4l2_ioctl_ops isc_ioctl_ops = { 1117 .vidioc_querycap = isc_querycap, 1118 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap, 1119 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap, 1120 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap, 1121 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap, 1122 1123 .vidioc_enum_input = isc_enum_input, 1124 .vidioc_g_input = isc_g_input, 1125 .vidioc_s_input = isc_s_input, 1126 1127 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1128 .vidioc_querybuf = vb2_ioctl_querybuf, 1129 .vidioc_qbuf = vb2_ioctl_qbuf, 1130 .vidioc_expbuf = vb2_ioctl_expbuf, 1131 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1132 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1133 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1134 .vidioc_streamon = vb2_ioctl_streamon, 1135 .vidioc_streamoff = vb2_ioctl_streamoff, 1136 1137 .vidioc_g_parm = isc_g_parm, 1138 .vidioc_s_parm = isc_s_parm, 1139 .vidioc_enum_framesizes = isc_enum_framesizes, 1140 1141 .vidioc_log_status = v4l2_ctrl_log_status, 1142 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1143 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1144 }; 1145 1146 static int isc_open(struct file *file) 1147 { 1148 struct isc_device *isc = video_drvdata(file); 1149 struct v4l2_subdev *sd = isc->current_subdev->sd; 1150 int ret; 1151 1152 if (mutex_lock_interruptible(&isc->lock)) 1153 return -ERESTARTSYS; 1154 1155 ret = v4l2_fh_open(file); 1156 if (ret < 0) 1157 goto unlock; 1158 1159 if (!v4l2_fh_is_singular_file(file)) 1160 goto unlock; 1161 1162 ret = v4l2_subdev_call(sd, core, s_power, 1); 1163 if (ret < 0 && ret != -ENOIOCTLCMD) { 1164 v4l2_fh_release(file); 1165 goto unlock; 1166 } 1167 1168 ret = isc_set_fmt(isc, &isc->fmt); 1169 if (ret) { 1170 v4l2_subdev_call(sd, core, s_power, 0); 1171 v4l2_fh_release(file); 1172 } 1173 1174 unlock: 1175 mutex_unlock(&isc->lock); 1176 return ret; 1177 } 1178 1179 static int isc_release(struct file *file) 1180 { 1181 struct isc_device *isc = video_drvdata(file); 1182 struct v4l2_subdev *sd = isc->current_subdev->sd; 1183 bool fh_singular; 1184 int ret; 1185 1186 mutex_lock(&isc->lock); 1187 1188 fh_singular = v4l2_fh_is_singular_file(file); 1189 1190 ret = _vb2_fop_release(file, NULL); 1191 1192 if (fh_singular) 1193 v4l2_subdev_call(sd, core, s_power, 0); 1194 1195 mutex_unlock(&isc->lock); 1196 1197 return ret; 1198 } 1199 1200 static const struct v4l2_file_operations isc_fops = { 1201 .owner = THIS_MODULE, 1202 .open = isc_open, 1203 .release = isc_release, 1204 .unlocked_ioctl = video_ioctl2, 1205 .read = vb2_fop_read, 1206 .mmap = vb2_fop_mmap, 1207 .poll = vb2_fop_poll, 1208 }; 1209 1210 irqreturn_t microchip_isc_interrupt(int irq, void *dev_id) 1211 { 1212 struct isc_device *isc = (struct isc_device *)dev_id; 1213 struct regmap *regmap = isc->regmap; 1214 u32 isc_intsr, isc_intmask, pending; 1215 irqreturn_t ret = IRQ_NONE; 1216 1217 regmap_read(regmap, ISC_INTSR, &isc_intsr); 1218 regmap_read(regmap, ISC_INTMASK, &isc_intmask); 1219 1220 pending = isc_intsr & isc_intmask; 1221 1222 if (likely(pending & ISC_INT_DDONE)) { 1223 spin_lock(&isc->dma_queue_lock); 1224 if (isc->cur_frm) { 1225 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb; 1226 struct vb2_buffer *vb = &vbuf->vb2_buf; 1227 1228 vb->timestamp = ktime_get_ns(); 1229 vbuf->sequence = isc->sequence++; 1230 vb2_buffer_done(vb, VB2_BUF_STATE_DONE); 1231 isc->cur_frm = NULL; 1232 } 1233 1234 if (!list_empty(&isc->dma_queue) && !isc->stop) { 1235 isc->cur_frm = list_first_entry(&isc->dma_queue, 1236 struct isc_buffer, list); 1237 list_del(&isc->cur_frm->list); 1238 1239 isc_start_dma(isc); 1240 } 1241 1242 if (isc->stop) 1243 complete(&isc->comp); 1244 1245 ret = IRQ_HANDLED; 1246 spin_unlock(&isc->dma_queue_lock); 1247 } 1248 1249 if (pending & ISC_INT_HISDONE) { 1250 schedule_work(&isc->awb_work); 1251 ret = IRQ_HANDLED; 1252 } 1253 1254 return ret; 1255 } 1256 EXPORT_SYMBOL_GPL(microchip_isc_interrupt); 1257 1258 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) 1259 { 1260 struct regmap *regmap = isc->regmap; 1261 struct isc_ctrls *ctrls = &isc->ctrls; 1262 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id]; 1263 u32 *hist_entry = &ctrls->hist_entry[0]; 1264 u32 i; 1265 1266 *min = 0; 1267 *max = HIST_ENTRIES; 1268 1269 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, 1270 hist_entry, HIST_ENTRIES); 1271 1272 *hist_count = 0; 1273 /* 1274 * we deliberately ignore the end of the histogram, 1275 * the most white pixels 1276 */ 1277 for (i = 1; i < HIST_ENTRIES; i++) { 1278 if (*hist_entry && !*min) 1279 *min = i; 1280 if (*hist_entry) 1281 *max = i; 1282 *hist_count += i * (*hist_entry++); 1283 } 1284 1285 if (!*min) 1286 *min = 1; 1287 1288 dev_dbg(isc->dev, "isc wb: hist_id %u, hist_count %u", 1289 ctrls->hist_id, *hist_count); 1290 } 1291 1292 static void isc_wb_update(struct isc_ctrls *ctrls) 1293 { 1294 struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls); 1295 u32 *hist_count = &ctrls->hist_count[0]; 1296 u32 c, offset[4]; 1297 u64 avg = 0; 1298 /* We compute two gains, stretch gain and grey world gain */ 1299 u32 s_gain[4], gw_gain[4]; 1300 1301 /* 1302 * According to Grey World, we need to set gains for R/B to normalize 1303 * them towards the green channel. 1304 * Thus we want to keep Green as fixed and adjust only Red/Blue 1305 * Compute the average of the both green channels first 1306 */ 1307 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] + 1308 (u64)hist_count[ISC_HIS_CFG_MODE_GB]; 1309 avg >>= 1; 1310 1311 dev_dbg(isc->dev, "isc wb: green components average %llu\n", avg); 1312 1313 /* Green histogram is null, nothing to do */ 1314 if (!avg) 1315 return; 1316 1317 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) { 1318 /* 1319 * the color offset is the minimum value of the histogram. 1320 * we stretch this color to the full range by substracting 1321 * this value from the color component. 1322 */ 1323 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX]; 1324 /* 1325 * The offset is always at least 1. If the offset is 1, we do 1326 * not need to adjust it, so our result must be zero. 1327 * the offset is computed in a histogram on 9 bits (0..512) 1328 * but the offset in register is based on 1329 * 12 bits pipeline (0..4096). 1330 * we need to shift with the 3 bits that the histogram is 1331 * ignoring 1332 */ 1333 ctrls->offset[c] = (offset[c] - 1) << 3; 1334 1335 /* 1336 * the offset is then taken and converted to 2's complements, 1337 * and must be negative, as we subtract this value from the 1338 * color components 1339 */ 1340 ctrls->offset[c] = -ctrls->offset[c]; 1341 1342 /* 1343 * the stretch gain is the total number of histogram bins 1344 * divided by the actual range of color component (Max - Min) 1345 * If we compute gain like this, the actual color component 1346 * will be stretched to the full histogram. 1347 * We need to shift 9 bits for precision, we have 9 bits for 1348 * decimals 1349 */ 1350 s_gain[c] = (HIST_ENTRIES << 9) / 1351 (ctrls->hist_minmax[c][HIST_MAX_INDEX] - 1352 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1); 1353 1354 /* 1355 * Now we have to compute the gain w.r.t. the average. 1356 * Add/lose gain to the component towards the average. 1357 * If it happens that the component is zero, use the 1358 * fixed point value : 1.0 gain. 1359 */ 1360 if (hist_count[c]) 1361 gw_gain[c] = div_u64(avg << 9, hist_count[c]); 1362 else 1363 gw_gain[c] = 1 << 9; 1364 1365 dev_dbg(isc->dev, 1366 "isc wb: component %d, s_gain %u, gw_gain %u\n", 1367 c, s_gain[c], gw_gain[c]); 1368 /* multiply both gains and adjust for decimals */ 1369 ctrls->gain[c] = s_gain[c] * gw_gain[c]; 1370 ctrls->gain[c] >>= 9; 1371 1372 /* make sure we are not out of range */ 1373 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0)); 1374 1375 dev_dbg(isc->dev, "isc wb: component %d, final gain %u\n", 1376 c, ctrls->gain[c]); 1377 } 1378 } 1379 1380 static void isc_awb_work(struct work_struct *w) 1381 { 1382 struct isc_device *isc = 1383 container_of(w, struct isc_device, awb_work); 1384 struct regmap *regmap = isc->regmap; 1385 struct isc_ctrls *ctrls = &isc->ctrls; 1386 u32 hist_id = ctrls->hist_id; 1387 u32 baysel; 1388 unsigned long flags; 1389 u32 min, max; 1390 int ret; 1391 1392 if (ctrls->hist_stat != HIST_ENABLED) 1393 return; 1394 1395 isc_hist_count(isc, &min, &max); 1396 1397 dev_dbg(isc->dev, 1398 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max); 1399 1400 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min; 1401 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max; 1402 1403 if (hist_id != ISC_HIS_CFG_MODE_B) { 1404 hist_id++; 1405 } else { 1406 isc_wb_update(ctrls); 1407 hist_id = ISC_HIS_CFG_MODE_GR; 1408 } 1409 1410 ctrls->hist_id = hist_id; 1411 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; 1412 1413 ret = pm_runtime_resume_and_get(isc->dev); 1414 if (ret < 0) 1415 return; 1416 1417 /* 1418 * only update if we have all the required histograms and controls 1419 * if awb has been disabled, we need to reset registers as well. 1420 */ 1421 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) { 1422 /* 1423 * It may happen that DMA Done IRQ will trigger while we are 1424 * updating white balance registers here. 1425 * In that case, only parts of the controls have been updated. 1426 * We can avoid that by locking the section. 1427 */ 1428 spin_lock_irqsave(&isc->awb_lock, flags); 1429 isc_update_awb_ctrls(isc); 1430 spin_unlock_irqrestore(&isc->awb_lock, flags); 1431 1432 /* 1433 * if we are doing just the one time white balance adjustment, 1434 * we are basically done. 1435 */ 1436 if (ctrls->awb == ISC_WB_ONETIME) { 1437 dev_info(isc->dev, 1438 "Completed one time white-balance adjustment.\n"); 1439 /* update the v4l2 controls values */ 1440 isc_update_v4l2_ctrls(isc); 1441 ctrls->awb = ISC_WB_NONE; 1442 } 1443 } 1444 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, 1445 hist_id | baysel | ISC_HIS_CFG_RAR); 1446 1447 /* 1448 * We have to make sure the streaming has not stopped meanwhile. 1449 * ISC requires a frame to clock the internal profile update. 1450 * To avoid issues, lock the sequence with a mutex 1451 */ 1452 mutex_lock(&isc->awb_mutex); 1453 1454 /* streaming is not active anymore */ 1455 if (isc->stop) { 1456 mutex_unlock(&isc->awb_mutex); 1457 return; 1458 } 1459 1460 isc_update_profile(isc); 1461 1462 mutex_unlock(&isc->awb_mutex); 1463 1464 /* if awb has been disabled, we don't need to start another histogram */ 1465 if (ctrls->awb) 1466 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); 1467 1468 pm_runtime_put_sync(isc->dev); 1469 } 1470 1471 static int isc_s_ctrl(struct v4l2_ctrl *ctrl) 1472 { 1473 struct isc_device *isc = container_of(ctrl->handler, 1474 struct isc_device, ctrls.handler); 1475 struct isc_ctrls *ctrls = &isc->ctrls; 1476 1477 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 1478 return 0; 1479 1480 switch (ctrl->id) { 1481 case V4L2_CID_BRIGHTNESS: 1482 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK; 1483 break; 1484 case V4L2_CID_CONTRAST: 1485 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK; 1486 break; 1487 case V4L2_CID_GAMMA: 1488 ctrls->gamma_index = ctrl->val; 1489 break; 1490 default: 1491 return -EINVAL; 1492 } 1493 1494 return 0; 1495 } 1496 1497 static const struct v4l2_ctrl_ops isc_ctrl_ops = { 1498 .s_ctrl = isc_s_ctrl, 1499 }; 1500 1501 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) 1502 { 1503 struct isc_device *isc = container_of(ctrl->handler, 1504 struct isc_device, ctrls.handler); 1505 struct isc_ctrls *ctrls = &isc->ctrls; 1506 1507 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 1508 return 0; 1509 1510 switch (ctrl->id) { 1511 case V4L2_CID_AUTO_WHITE_BALANCE: 1512 if (ctrl->val == 1) 1513 ctrls->awb = ISC_WB_AUTO; 1514 else 1515 ctrls->awb = ISC_WB_NONE; 1516 1517 /* configure the controls with new values from v4l2 */ 1518 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new) 1519 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val; 1520 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new) 1521 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val; 1522 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new) 1523 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val; 1524 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new) 1525 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val; 1526 1527 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new) 1528 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val; 1529 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new) 1530 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val; 1531 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new) 1532 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val; 1533 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new) 1534 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val; 1535 1536 isc_update_awb_ctrls(isc); 1537 1538 mutex_lock(&isc->awb_mutex); 1539 if (vb2_is_streaming(&isc->vb2_vidq)) { 1540 /* 1541 * If we are streaming, we can update profile to 1542 * have the new settings in place. 1543 */ 1544 isc_update_profile(isc); 1545 } else { 1546 /* 1547 * The auto cluster will activate automatically this 1548 * control. This has to be deactivated when not 1549 * streaming. 1550 */ 1551 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 1552 } 1553 mutex_unlock(&isc->awb_mutex); 1554 1555 /* if we have autowhitebalance on, start histogram procedure */ 1556 if (ctrls->awb == ISC_WB_AUTO && 1557 vb2_is_streaming(&isc->vb2_vidq) && 1558 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) 1559 isc_set_histogram(isc, true); 1560 1561 /* 1562 * for one time whitebalance adjustment, check the button, 1563 * if it's pressed, perform the one time operation. 1564 */ 1565 if (ctrls->awb == ISC_WB_NONE && 1566 ctrl->cluster[ISC_CTRL_DO_WB]->is_new && 1567 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags & 1568 V4L2_CTRL_FLAG_INACTIVE)) { 1569 ctrls->awb = ISC_WB_ONETIME; 1570 isc_set_histogram(isc, true); 1571 dev_dbg(isc->dev, "One time white-balance started.\n"); 1572 } 1573 return 0; 1574 } 1575 return 0; 1576 } 1577 1578 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl) 1579 { 1580 struct isc_device *isc = container_of(ctrl->handler, 1581 struct isc_device, ctrls.handler); 1582 struct isc_ctrls *ctrls = &isc->ctrls; 1583 1584 switch (ctrl->id) { 1585 /* being a cluster, this id will be called for every control */ 1586 case V4L2_CID_AUTO_WHITE_BALANCE: 1587 ctrl->cluster[ISC_CTRL_R_GAIN]->val = 1588 ctrls->gain[ISC_HIS_CFG_MODE_R]; 1589 ctrl->cluster[ISC_CTRL_B_GAIN]->val = 1590 ctrls->gain[ISC_HIS_CFG_MODE_B]; 1591 ctrl->cluster[ISC_CTRL_GR_GAIN]->val = 1592 ctrls->gain[ISC_HIS_CFG_MODE_GR]; 1593 ctrl->cluster[ISC_CTRL_GB_GAIN]->val = 1594 ctrls->gain[ISC_HIS_CFG_MODE_GB]; 1595 1596 ctrl->cluster[ISC_CTRL_R_OFF]->val = 1597 ctrls->offset[ISC_HIS_CFG_MODE_R]; 1598 ctrl->cluster[ISC_CTRL_B_OFF]->val = 1599 ctrls->offset[ISC_HIS_CFG_MODE_B]; 1600 ctrl->cluster[ISC_CTRL_GR_OFF]->val = 1601 ctrls->offset[ISC_HIS_CFG_MODE_GR]; 1602 ctrl->cluster[ISC_CTRL_GB_OFF]->val = 1603 ctrls->offset[ISC_HIS_CFG_MODE_GB]; 1604 break; 1605 } 1606 return 0; 1607 } 1608 1609 static const struct v4l2_ctrl_ops isc_awb_ops = { 1610 .s_ctrl = isc_s_awb_ctrl, 1611 .g_volatile_ctrl = isc_g_volatile_awb_ctrl, 1612 }; 1613 1614 #define ISC_CTRL_OFF(_name, _id, _name_str) \ 1615 static const struct v4l2_ctrl_config _name = { \ 1616 .ops = &isc_awb_ops, \ 1617 .id = _id, \ 1618 .name = _name_str, \ 1619 .type = V4L2_CTRL_TYPE_INTEGER, \ 1620 .flags = V4L2_CTRL_FLAG_SLIDER, \ 1621 .min = -4095, \ 1622 .max = 4095, \ 1623 .step = 1, \ 1624 .def = 0, \ 1625 } 1626 1627 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset"); 1628 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset"); 1629 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset"); 1630 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset"); 1631 1632 #define ISC_CTRL_GAIN(_name, _id, _name_str) \ 1633 static const struct v4l2_ctrl_config _name = { \ 1634 .ops = &isc_awb_ops, \ 1635 .id = _id, \ 1636 .name = _name_str, \ 1637 .type = V4L2_CTRL_TYPE_INTEGER, \ 1638 .flags = V4L2_CTRL_FLAG_SLIDER, \ 1639 .min = 0, \ 1640 .max = 8191, \ 1641 .step = 1, \ 1642 .def = 512, \ 1643 } 1644 1645 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain"); 1646 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain"); 1647 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain"); 1648 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain"); 1649 1650 static int isc_ctrl_init(struct isc_device *isc) 1651 { 1652 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops; 1653 struct isc_ctrls *ctrls = &isc->ctrls; 1654 struct v4l2_ctrl_handler *hdl = &ctrls->handler; 1655 int ret; 1656 1657 ctrls->hist_stat = HIST_INIT; 1658 isc_reset_awb_ctrls(isc); 1659 1660 ret = v4l2_ctrl_handler_init(hdl, 13); 1661 if (ret < 0) 1662 return ret; 1663 1664 /* Initialize product specific controls. For example, contrast */ 1665 isc->config_ctrls(isc, ops); 1666 1667 ctrls->brightness = 0; 1668 1669 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); 1670 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, 1671 isc->gamma_max); 1672 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, 1673 V4L2_CID_AUTO_WHITE_BALANCE, 1674 0, 1, 1, 1); 1675 1676 /* do_white_balance is a button, so min,max,step,default are ignored */ 1677 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, 1678 V4L2_CID_DO_WHITE_BALANCE, 1679 0, 0, 0, 0); 1680 1681 if (!isc->do_wb_ctrl) { 1682 ret = hdl->error; 1683 v4l2_ctrl_handler_free(hdl); 1684 return ret; 1685 } 1686 1687 v4l2_ctrl_activate(isc->do_wb_ctrl, false); 1688 1689 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL); 1690 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL); 1691 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL); 1692 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL); 1693 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL); 1694 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL); 1695 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL); 1696 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL); 1697 1698 /* 1699 * The cluster is in auto mode with autowhitebalance enabled 1700 * and manual mode otherwise. 1701 */ 1702 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true); 1703 1704 v4l2_ctrl_handler_setup(hdl); 1705 1706 return 0; 1707 } 1708 1709 static int isc_async_bound(struct v4l2_async_notifier *notifier, 1710 struct v4l2_subdev *subdev, 1711 struct v4l2_async_connection *asd) 1712 { 1713 struct isc_device *isc = container_of(notifier->v4l2_dev, 1714 struct isc_device, v4l2_dev); 1715 struct isc_subdev_entity *subdev_entity = 1716 container_of(notifier, struct isc_subdev_entity, notifier); 1717 int pad; 1718 1719 if (video_is_registered(&isc->video_dev)) { 1720 dev_err(isc->dev, "only supports one sub-device.\n"); 1721 return -EBUSY; 1722 } 1723 1724 subdev_entity->sd = subdev; 1725 1726 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, 1727 MEDIA_PAD_FL_SOURCE); 1728 if (pad < 0) { 1729 dev_err(isc->dev, "failed to find pad for %s\n", subdev->name); 1730 return pad; 1731 } 1732 1733 isc->remote_pad = pad; 1734 1735 return 0; 1736 } 1737 1738 static void isc_async_unbind(struct v4l2_async_notifier *notifier, 1739 struct v4l2_subdev *subdev, 1740 struct v4l2_async_connection *asd) 1741 { 1742 struct isc_device *isc = container_of(notifier->v4l2_dev, 1743 struct isc_device, v4l2_dev); 1744 mutex_destroy(&isc->awb_mutex); 1745 cancel_work_sync(&isc->awb_work); 1746 video_unregister_device(&isc->video_dev); 1747 v4l2_ctrl_handler_free(&isc->ctrls.handler); 1748 } 1749 1750 struct isc_format *isc_find_format_by_code(struct isc_device *isc, 1751 unsigned int code, int *index) 1752 { 1753 struct isc_format *fmt = &isc->formats_list[0]; 1754 unsigned int i; 1755 1756 for (i = 0; i < isc->formats_list_size; i++) { 1757 if (fmt->mbus_code == code) { 1758 *index = i; 1759 return fmt; 1760 } 1761 1762 fmt++; 1763 } 1764 1765 return NULL; 1766 } 1767 EXPORT_SYMBOL_GPL(isc_find_format_by_code); 1768 1769 static int isc_set_default_fmt(struct isc_device *isc) 1770 { 1771 struct v4l2_format f = { 1772 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, 1773 .fmt.pix = { 1774 .width = VGA_WIDTH, 1775 .height = VGA_HEIGHT, 1776 .field = V4L2_FIELD_NONE, 1777 .pixelformat = isc->controller_formats[0].fourcc, 1778 }, 1779 }; 1780 int ret; 1781 1782 ret = isc_try_fmt(isc, &f); 1783 if (ret) 1784 return ret; 1785 1786 isc->fmt = f; 1787 return 0; 1788 } 1789 1790 static int isc_async_complete(struct v4l2_async_notifier *notifier) 1791 { 1792 struct isc_device *isc = container_of(notifier->v4l2_dev, 1793 struct isc_device, v4l2_dev); 1794 struct video_device *vdev = &isc->video_dev; 1795 struct vb2_queue *q = &isc->vb2_vidq; 1796 int ret = 0; 1797 1798 INIT_WORK(&isc->awb_work, isc_awb_work); 1799 1800 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev); 1801 if (ret < 0) { 1802 dev_err(isc->dev, "Failed to register subdev nodes\n"); 1803 return ret; 1804 } 1805 1806 isc->current_subdev = container_of(notifier, 1807 struct isc_subdev_entity, notifier); 1808 mutex_init(&isc->lock); 1809 mutex_init(&isc->awb_mutex); 1810 1811 init_completion(&isc->comp); 1812 1813 /* Initialize videobuf2 queue */ 1814 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 1815 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; 1816 q->drv_priv = isc; 1817 q->buf_struct_size = sizeof(struct isc_buffer); 1818 q->ops = &isc_vb2_ops; 1819 q->mem_ops = &vb2_dma_contig_memops; 1820 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1821 q->lock = &isc->lock; 1822 q->min_buffers_needed = 1; 1823 q->dev = isc->dev; 1824 1825 ret = vb2_queue_init(q); 1826 if (ret < 0) { 1827 dev_err(isc->dev, "vb2_queue_init() failed: %d\n", ret); 1828 goto isc_async_complete_err; 1829 } 1830 1831 /* Init video dma queues */ 1832 INIT_LIST_HEAD(&isc->dma_queue); 1833 spin_lock_init(&isc->dma_queue_lock); 1834 spin_lock_init(&isc->awb_lock); 1835 1836 ret = isc_set_default_fmt(isc); 1837 if (ret) { 1838 dev_err(isc->dev, "Could not set default format\n"); 1839 goto isc_async_complete_err; 1840 } 1841 1842 ret = isc_ctrl_init(isc); 1843 if (ret) { 1844 dev_err(isc->dev, "Init isc ctrols failed: %d\n", ret); 1845 goto isc_async_complete_err; 1846 } 1847 1848 /* Register video device */ 1849 strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); 1850 vdev->release = video_device_release_empty; 1851 vdev->fops = &isc_fops; 1852 vdev->ioctl_ops = &isc_ioctl_ops; 1853 vdev->v4l2_dev = &isc->v4l2_dev; 1854 vdev->vfl_dir = VFL_DIR_RX; 1855 vdev->queue = q; 1856 vdev->lock = &isc->lock; 1857 vdev->ctrl_handler = &isc->ctrls.handler; 1858 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE | 1859 V4L2_CAP_IO_MC; 1860 video_set_drvdata(vdev, isc); 1861 1862 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1863 if (ret < 0) { 1864 dev_err(isc->dev, "video_register_device failed: %d\n", ret); 1865 goto isc_async_complete_err; 1866 } 1867 1868 ret = isc_scaler_link(isc); 1869 if (ret < 0) 1870 goto isc_async_complete_unregister_device; 1871 1872 ret = media_device_register(&isc->mdev); 1873 if (ret < 0) 1874 goto isc_async_complete_unregister_device; 1875 1876 return 0; 1877 1878 isc_async_complete_unregister_device: 1879 video_unregister_device(vdev); 1880 1881 isc_async_complete_err: 1882 mutex_destroy(&isc->awb_mutex); 1883 mutex_destroy(&isc->lock); 1884 return ret; 1885 } 1886 1887 const struct v4l2_async_notifier_operations microchip_isc_async_ops = { 1888 .bound = isc_async_bound, 1889 .unbind = isc_async_unbind, 1890 .complete = isc_async_complete, 1891 }; 1892 EXPORT_SYMBOL_GPL(microchip_isc_async_ops); 1893 1894 void microchip_isc_subdev_cleanup(struct isc_device *isc) 1895 { 1896 struct isc_subdev_entity *subdev_entity; 1897 1898 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { 1899 v4l2_async_nf_unregister(&subdev_entity->notifier); 1900 v4l2_async_nf_cleanup(&subdev_entity->notifier); 1901 } 1902 1903 INIT_LIST_HEAD(&isc->subdev_entities); 1904 } 1905 EXPORT_SYMBOL_GPL(microchip_isc_subdev_cleanup); 1906 1907 int microchip_isc_pipeline_init(struct isc_device *isc) 1908 { 1909 struct device *dev = isc->dev; 1910 struct regmap *regmap = isc->regmap; 1911 struct regmap_field *regs; 1912 unsigned int i; 1913 1914 /* 1915 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> 1916 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 1917 */ 1918 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { 1919 REG_FIELD(ISC_DPC_CTRL, 0, 0), 1920 REG_FIELD(ISC_DPC_CTRL, 1, 1), 1921 REG_FIELD(ISC_DPC_CTRL, 2, 2), 1922 REG_FIELD(ISC_WB_CTRL, 0, 0), 1923 REG_FIELD(ISC_CFA_CTRL, 0, 0), 1924 REG_FIELD(ISC_CC_CTRL, 0, 0), 1925 REG_FIELD(ISC_GAM_CTRL, 0, 0), 1926 REG_FIELD(ISC_GAM_CTRL, 1, 1), 1927 REG_FIELD(ISC_GAM_CTRL, 2, 2), 1928 REG_FIELD(ISC_GAM_CTRL, 3, 3), 1929 REG_FIELD(ISC_VHXS_CTRL, 0, 0), 1930 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), 1931 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), 1932 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), 1933 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), 1934 }; 1935 1936 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { 1937 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]); 1938 if (IS_ERR(regs)) 1939 return PTR_ERR(regs); 1940 1941 isc->pipeline[i] = regs; 1942 } 1943 1944 return 0; 1945 } 1946 EXPORT_SYMBOL_GPL(microchip_isc_pipeline_init); 1947 1948 static int isc_link_validate(struct media_link *link) 1949 { 1950 struct video_device *vdev = 1951 media_entity_to_video_device(link->sink->entity); 1952 struct isc_device *isc = video_get_drvdata(vdev); 1953 int ret; 1954 1955 ret = v4l2_subdev_link_validate(link); 1956 if (ret) 1957 return ret; 1958 1959 return isc_validate(isc); 1960 } 1961 1962 static const struct media_entity_operations isc_entity_operations = { 1963 .link_validate = isc_link_validate, 1964 }; 1965 1966 int isc_mc_init(struct isc_device *isc, u32 ver) 1967 { 1968 const struct of_device_id *match; 1969 int ret; 1970 1971 isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L; 1972 isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT; 1973 isc->video_dev.entity.ops = &isc_entity_operations; 1974 1975 isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 1976 1977 ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM, 1978 isc->pads); 1979 if (ret < 0) { 1980 dev_err(isc->dev, "media entity init failed\n"); 1981 return ret; 1982 } 1983 1984 isc->mdev.dev = isc->dev; 1985 1986 match = of_match_node(isc->dev->driver->of_match_table, 1987 isc->dev->of_node); 1988 1989 strscpy(isc->mdev.driver_name, KBUILD_MODNAME, 1990 sizeof(isc->mdev.driver_name)); 1991 strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model)); 1992 isc->mdev.hw_revision = ver; 1993 1994 media_device_init(&isc->mdev); 1995 1996 isc->v4l2_dev.mdev = &isc->mdev; 1997 1998 return isc_scaler_init(isc); 1999 } 2000 EXPORT_SYMBOL_GPL(isc_mc_init); 2001 2002 void isc_mc_cleanup(struct isc_device *isc) 2003 { 2004 media_entity_cleanup(&isc->video_dev.entity); 2005 media_device_cleanup(&isc->mdev); 2006 } 2007 EXPORT_SYMBOL_GPL(isc_mc_cleanup); 2008 2009 /* regmap configuration */ 2010 #define MICROCHIP_ISC_REG_MAX 0xd5c 2011 const struct regmap_config microchip_isc_regmap_config = { 2012 .reg_bits = 32, 2013 .reg_stride = 4, 2014 .val_bits = 32, 2015 .max_register = MICROCHIP_ISC_REG_MAX, 2016 }; 2017 EXPORT_SYMBOL_GPL(microchip_isc_regmap_config); 2018 2019 MODULE_AUTHOR("Songjun Wu"); 2020 MODULE_AUTHOR("Eugen Hristev"); 2021 MODULE_DESCRIPTION("Microchip ISC common code base"); 2022 MODULE_LICENSE("GPL v2"); 2023