1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5 */ 6 7 #ifndef __MDP_SM_MT8183_H__ 8 #define __MDP_SM_MT8183_H__ 9 10 #include "mtk-mdp3-type.h" 11 12 /* 13 * ISP-MDP generic output information 14 * MD5 of the target SCP prebuild: 15 * 2d995ddb5c3b0cf26e96d6a823481886 16 */ 17 18 #define IMG_MAX_SUBFRAMES_8183 14 19 20 struct img_comp_frame_8183 { 21 u32 output_disable:1; 22 u32 bypass:1; 23 u16 in_width; 24 u16 in_height; 25 u16 out_width; 26 u16 out_height; 27 struct img_crop crop; 28 u16 in_total_width; 29 u16 out_total_width; 30 } __packed; 31 32 struct img_comp_subfrm_8183 { 33 u32 tile_disable:1; 34 struct img_region in; 35 struct img_region out; 36 struct img_offset luma; 37 struct img_offset chroma; 38 s16 out_vertical; /* Output vertical index */ 39 s16 out_horizontal; /* Output horizontal index */ 40 } __packed; 41 42 struct mdp_rdma_subfrm_8183 { 43 u32 offset[IMG_MAX_PLANES]; 44 u32 offset_0_p; 45 u32 src; 46 u32 clip; 47 u32 clip_ofst; 48 } __packed; 49 50 struct mdp_rdma_data_8183 { 51 u32 src_ctrl; 52 u32 control; 53 u32 iova[IMG_MAX_PLANES]; 54 u32 iova_end[IMG_MAX_PLANES]; 55 u32 mf_bkgd; 56 u32 mf_bkgd_in_pxl; 57 u32 sf_bkgd; 58 u32 ufo_dec_y; 59 u32 ufo_dec_c; 60 u32 transform; 61 struct mdp_rdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; 62 } __packed; 63 64 struct mdp_rsz_subfrm_8183 { 65 u32 control2; 66 u32 src; 67 u32 clip; 68 } __packed; 69 70 struct mdp_rsz_data_8183 { 71 u32 coeff_step_x; 72 u32 coeff_step_y; 73 u32 control1; 74 u32 control2; 75 struct mdp_rsz_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; 76 } __packed; 77 78 struct mdp_wrot_subfrm_8183 { 79 u32 offset[IMG_MAX_PLANES]; 80 u32 src; 81 u32 clip; 82 u32 clip_ofst; 83 u32 main_buf; 84 } __packed; 85 86 struct mdp_wrot_data_8183 { 87 u32 iova[IMG_MAX_PLANES]; 88 u32 control; 89 u32 stride[IMG_MAX_PLANES]; 90 u32 mat_ctrl; 91 u32 fifo_test; 92 u32 filter; 93 struct mdp_wrot_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; 94 } __packed; 95 96 struct mdp_wdma_subfrm_8183 { 97 u32 offset[IMG_MAX_PLANES]; 98 u32 src; 99 u32 clip; 100 u32 clip_ofst; 101 } __packed; 102 103 struct mdp_wdma_data_8183 { 104 u32 wdma_cfg; 105 u32 iova[IMG_MAX_PLANES]; 106 u32 w_in_byte; 107 u32 uv_stride; 108 struct mdp_wdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; 109 } __packed; 110 111 struct isp_data_8183 { 112 u64 dl_flags; /* 1 << (enum mdp_comp_type) */ 113 u32 smxi_iova[4]; 114 u32 cq_idx; 115 u32 cq_iova; 116 u32 tpipe_iova[IMG_MAX_SUBFRAMES_8183]; 117 } __packed; 118 119 struct img_compparam_8183 { 120 u16 type; /* enum mdp_comp_id */ 121 u16 id; /* engine alias_id */ 122 u32 input; 123 u32 outputs[IMG_MAX_HW_OUTPUTS]; 124 u32 num_outputs; 125 struct img_comp_frame_8183 frame; 126 struct img_comp_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; 127 u32 num_subfrms; 128 union { 129 struct mdp_rdma_data_8183 rdma; 130 struct mdp_rsz_data_8183 rsz; 131 struct mdp_wrot_data_8183 wrot; 132 struct mdp_wdma_data_8183 wdma; 133 struct isp_data_8183 isp; 134 }; 135 } __packed; 136 137 struct img_config_8183 { 138 struct img_compparam_8183 components[IMG_MAX_COMPONENTS]; 139 u32 num_components; 140 struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES_8183]; 141 u32 num_subfrms; 142 } __packed; 143 144 #endif /* __MDP_SM_MT8183_H__ */ 145