1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5 */ 6 7 #ifndef __MDP_REG_WDMA_H__ 8 #define __MDP_REG_WDMA_H__ 9 10 #define WDMA_EN 0x008 11 #define WDMA_RST 0x00c 12 #define WDMA_CFG 0x014 13 #define WDMA_SRC_SIZE 0x018 14 #define WDMA_CLIP_SIZE 0x01c 15 #define WDMA_CLIP_COORD 0x020 16 #define WDMA_DST_W_IN_BYTE 0x028 17 #define WDMA_ALPHA 0x02c 18 #define WDMA_BUF_CON2 0x03c 19 #define WDMA_DST_UV_PITCH 0x078 20 #define WDMA_DST_ADDR_OFFSET 0x080 21 #define WDMA_DST_U_ADDR_OFFSET 0x084 22 #define WDMA_DST_V_ADDR_OFFSET 0x088 23 #define WDMA_FLOW_CTRL_DBG 0x0a0 24 #define WDMA_DST_ADDR 0xf00 25 #define WDMA_DST_U_ADDR 0xf04 26 #define WDMA_DST_V_ADDR 0xf08 27 28 /* MASK */ 29 #define WDMA_EN_MASK 0x00000001 30 #define WDMA_RST_MASK 0x00000001 31 #define WDMA_CFG_MASK 0xff03bff0 32 #define WDMA_SRC_SIZE_MASK 0x3fff3fff 33 #define WDMA_CLIP_SIZE_MASK 0x3fff3fff 34 #define WDMA_CLIP_COORD_MASK 0x3fff3fff 35 #define WDMA_DST_W_IN_BYTE_MASK 0x0000ffff 36 #define WDMA_ALPHA_MASK 0x800000ff 37 #define WDMA_BUF_CON2_MASK 0xffffffff 38 #define WDMA_DST_UV_PITCH_MASK 0x0000ffff 39 #define WDMA_DST_ADDR_OFFSET_MASK 0x0fffffff 40 #define WDMA_DST_U_ADDR_OFFSET_MASK 0x0fffffff 41 #define WDMA_DST_V_ADDR_OFFSET_MASK 0x0fffffff 42 #define WDMA_FLOW_CTRL_DBG_MASK 0x0000f3ff 43 #define WDMA_DST_ADDR_MASK 0xffffffff 44 #define WDMA_DST_U_ADDR_MASK 0xffffffff 45 #define WDMA_DST_V_ADDR_MASK 0xffffffff 46 47 #endif // __MDP_REG_WDMA_H__ 48