1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5 */ 6 7 #ifndef __MDP_REG_RDMA_H__ 8 #define __MDP_REG_RDMA_H__ 9 10 #define MDP_RDMA_EN 0x000 11 #define MDP_RDMA_RESET 0x008 12 #define MDP_RDMA_CON 0x020 13 #define MDP_RDMA_GMCIF_CON 0x028 14 #define MDP_RDMA_SRC_CON 0x030 15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068 17 #define MDP_RDMA_MF_SRC_SIZE 0x070 18 #define MDP_RDMA_MF_CLIP_SIZE 0x078 19 #define MDP_RDMA_MF_OFFSET_1 0x080 20 #define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090 21 #define MDP_RDMA_SRC_END_0 0x100 22 #define MDP_RDMA_SRC_END_1 0x108 23 #define MDP_RDMA_SRC_END_2 0x110 24 #define MDP_RDMA_SRC_OFFSET_0 0x118 25 #define MDP_RDMA_SRC_OFFSET_1 0x120 26 #define MDP_RDMA_SRC_OFFSET_2 0x128 27 #define MDP_RDMA_SRC_OFFSET_0_P 0x148 28 #define MDP_RDMA_TRANSFORM_0 0x200 29 #define MDP_RDMA_DMABUF_CON_0 0x240 30 #define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248 31 #define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250 32 #define MDP_RDMA_DMABUF_CON_1 0x258 33 #define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260 34 #define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268 35 #define MDP_RDMA_DMABUF_CON_2 0x270 36 #define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278 37 #define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280 38 #define MDP_RDMA_DMABUF_CON_3 0x288 39 #define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290 40 #define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298 41 #define MDP_RDMA_RESV_DUMMY_0 0x2a0 42 #define MDP_RDMA_MON_STA_1 0x408 43 #define MDP_RDMA_SRC_BASE_0 0xf00 44 #define MDP_RDMA_SRC_BASE_1 0xf08 45 #define MDP_RDMA_SRC_BASE_2 0xf10 46 #define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y 0xf20 47 #define MDP_RDMA_UFO_DEC_LENGTH_BASE_C 0xf28 48 49 /* MASK */ 50 #define MDP_RDMA_EN_MASK 0x00000001 51 #define MDP_RDMA_RESET_MASK 0x00000001 52 #define MDP_RDMA_CON_MASK 0x00001110 53 #define MDP_RDMA_GMCIF_CON_MASK 0xfffb3771 54 #define MDP_RDMA_SRC_CON_MASK 0xf3ffffff 55 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff 56 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff 57 #define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff 58 #define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff 59 #define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f 60 #define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff 61 #define MDP_RDMA_SRC_END_0_MASK 0xffffffff 62 #define MDP_RDMA_SRC_END_1_MASK 0xffffffff 63 #define MDP_RDMA_SRC_END_2_MASK 0xffffffff 64 #define MDP_RDMA_SRC_OFFSET_0_MASK 0xffffffff 65 #define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff 66 #define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff 67 #define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff 68 #define MDP_RDMA_TRANSFORM_0_MASK 0xff110777 69 #define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff 70 #define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff 71 #define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff 72 #define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f 73 #define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff 74 #define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff 75 #define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f 76 #define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff 77 #define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff 78 #define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f 79 #define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff 80 #define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff 81 #define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff 82 #define MDP_RDMA_MON_STA_1_MASK 0xffffffff 83 #define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff 84 #define MDP_RDMA_SRC_BASE_1_MASK 0xffffffff 85 #define MDP_RDMA_SRC_BASE_2_MASK 0xffffffff 86 #define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y_MASK 0xffffffff 87 #define MDP_RDMA_UFO_DEC_LENGTH_BASE_C_MASK 0xffffffff 88 89 #endif // __MDP_REG_RDMA_H__ 90