1*73e00953SMoudy Ho /* SPDX-License-Identifier: GPL-2.0-only */ 2*73e00953SMoudy Ho /* 3*73e00953SMoudy Ho * Copyright (c) 2022 MediaTek Inc. 4*73e00953SMoudy Ho * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5*73e00953SMoudy Ho */ 6*73e00953SMoudy Ho 7*73e00953SMoudy Ho #ifndef __MDP_REG_FG_H__ 8*73e00953SMoudy Ho #define __MDP_REG_FG_H__ 9*73e00953SMoudy Ho 10*73e00953SMoudy Ho #define MDP_FG_TRIGGER (0x0) 11*73e00953SMoudy Ho #define MDP_FG_FG_CTRL_0 (0x20) 12*73e00953SMoudy Ho #define MDP_FG_FG_CK_EN (0x24) 13*73e00953SMoudy Ho #define MDP_FG_TILE_INFO_0 (0x418) 14*73e00953SMoudy Ho #define MDP_FG_TILE_INFO_1 (0x41c) 15*73e00953SMoudy Ho 16*73e00953SMoudy Ho /* MASK */ 17*73e00953SMoudy Ho #define MDP_FG_TRIGGER_MASK (0x00000007) 18*73e00953SMoudy Ho #define MDP_FG_FG_CTRL_0_MASK (0x00000033) 19*73e00953SMoudy Ho #define MDP_FG_FG_CK_EN_MASK (0x0000000F) 20*73e00953SMoudy Ho #define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF) 21*73e00953SMoudy Ho #define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF) 22*73e00953SMoudy Ho 23*73e00953SMoudy Ho #endif //__MDP_REG_FG_H__ 24