1*73e00953SMoudy Ho /* SPDX-License-Identifier: GPL-2.0-only */ 2*73e00953SMoudy Ho /* 3*73e00953SMoudy Ho * Copyright (c) 2022 MediaTek Inc. 4*73e00953SMoudy Ho * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5*73e00953SMoudy Ho */ 6*73e00953SMoudy Ho 7*73e00953SMoudy Ho #ifndef __MDP_REG_AAL_H__ 8*73e00953SMoudy Ho #define __MDP_REG_AAL_H__ 9*73e00953SMoudy Ho 10*73e00953SMoudy Ho #define MDP_AAL_EN (0x000) 11*73e00953SMoudy Ho #define MDP_AAL_CFG (0x020) 12*73e00953SMoudy Ho #define MDP_AAL_SIZE (0x030) 13*73e00953SMoudy Ho #define MDP_AAL_OUTPUT_SIZE (0x034) 14*73e00953SMoudy Ho #define MDP_AAL_OUTPUT_OFFSET (0x038) 15*73e00953SMoudy Ho #define MDP_AAL_CFG_MAIN (0x200) 16*73e00953SMoudy Ho 17*73e00953SMoudy Ho /* MASK */ 18*73e00953SMoudy Ho #define MDP_AAL_EN_MASK (0x01) 19*73e00953SMoudy Ho #define MDP_AAL_CFG_MASK (0x70FF00B3) 20*73e00953SMoudy Ho #define MDP_AAL_SIZE_MASK (0x1FFF1FFF) 21*73e00953SMoudy Ho #define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF) 22*73e00953SMoudy Ho #define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF) 23*73e00953SMoudy Ho #define MDP_AAL_CFG_MAIN_MASK (0x0FE) 24*73e00953SMoudy Ho 25*73e00953SMoudy Ho #endif // __MDP_REG_AAL_H__ 26