1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5 */ 6 7 #include "mtk-img-ipi.h" 8 #include "mtk-mdp3-cfg.h" 9 #include "mtk-mdp3-core.h" 10 #include "mtk-mdp3-comp.h" 11 #include "mtk-mdp3-regs.h" 12 13 enum mt8183_mdp_comp_id { 14 /* ISP */ 15 MT8183_MDP_COMP_WPEI = 0, 16 MT8183_MDP_COMP_WPEO, /* 1 */ 17 MT8183_MDP_COMP_WPEI2, /* 2 */ 18 MT8183_MDP_COMP_WPEO2, /* 3 */ 19 MT8183_MDP_COMP_ISP_IMGI, /* 4 */ 20 MT8183_MDP_COMP_ISP_IMGO, /* 5 */ 21 MT8183_MDP_COMP_ISP_IMG2O, /* 6 */ 22 23 /* IPU */ 24 MT8183_MDP_COMP_IPUI, /* 7 */ 25 MT8183_MDP_COMP_IPUO, /* 8 */ 26 27 /* MDP */ 28 MT8183_MDP_COMP_CAMIN, /* 9 */ 29 MT8183_MDP_COMP_CAMIN2, /* 10 */ 30 MT8183_MDP_COMP_RDMA0, /* 11 */ 31 MT8183_MDP_COMP_AAL0, /* 12 */ 32 MT8183_MDP_COMP_CCORR0, /* 13 */ 33 MT8183_MDP_COMP_RSZ0, /* 14 */ 34 MT8183_MDP_COMP_RSZ1, /* 15 */ 35 MT8183_MDP_COMP_TDSHP0, /* 16 */ 36 MT8183_MDP_COMP_COLOR0, /* 17 */ 37 MT8183_MDP_COMP_PATH0_SOUT, /* 18 */ 38 MT8183_MDP_COMP_PATH1_SOUT, /* 19 */ 39 MT8183_MDP_COMP_WROT0, /* 20 */ 40 MT8183_MDP_COMP_WDMA, /* 21 */ 41 42 /* Dummy Engine */ 43 MT8183_MDP_COMP_RDMA1, /* 22 */ 44 MT8183_MDP_COMP_RSZ2, /* 23 */ 45 MT8183_MDP_COMP_TDSHP1, /* 24 */ 46 MT8183_MDP_COMP_WROT1, /* 25 */ 47 }; 48 49 enum mt8195_mdp_comp_id { 50 /* MT8195 Comp id */ 51 /* ISP */ 52 MT8195_MDP_COMP_WPEI = 0, 53 MT8195_MDP_COMP_WPEO, /* 1 */ 54 MT8195_MDP_COMP_WPEI2, /* 2 */ 55 MT8195_MDP_COMP_WPEO2, /* 3 */ 56 57 /* MDP */ 58 MT8195_MDP_COMP_CAMIN, /* 4 */ 59 MT8195_MDP_COMP_CAMIN2, /* 5 */ 60 MT8195_MDP_COMP_SPLIT, /* 6 */ 61 MT8195_MDP_COMP_SPLIT2, /* 7 */ 62 MT8195_MDP_COMP_RDMA0, /* 8 */ 63 MT8195_MDP_COMP_RDMA1, /* 9 */ 64 MT8195_MDP_COMP_RDMA2, /* 10 */ 65 MT8195_MDP_COMP_RDMA3, /* 11 */ 66 MT8195_MDP_COMP_STITCH, /* 12 */ 67 MT8195_MDP_COMP_FG0, /* 13 */ 68 MT8195_MDP_COMP_FG1, /* 14 */ 69 MT8195_MDP_COMP_FG2, /* 15 */ 70 MT8195_MDP_COMP_FG3, /* 16 */ 71 MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */ 72 MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */ 73 MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */ 74 MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */ 75 MT8195_MDP_COMP_VPP0_SOUT, /* 21 */ 76 MT8195_MDP_COMP_VPP1_SOUT, /* 22 */ 77 MT8195_MDP_COMP_PQ0_SOUT, /* 23 */ 78 MT8195_MDP_COMP_PQ1_SOUT, /* 24 */ 79 MT8195_MDP_COMP_HDR0, /* 25 */ 80 MT8195_MDP_COMP_HDR1, /* 26 */ 81 MT8195_MDP_COMP_HDR2, /* 27 */ 82 MT8195_MDP_COMP_HDR3, /* 28 */ 83 MT8195_MDP_COMP_AAL0, /* 29 */ 84 MT8195_MDP_COMP_AAL1, /* 30 */ 85 MT8195_MDP_COMP_AAL2, /* 31 */ 86 MT8195_MDP_COMP_AAL3, /* 32 */ 87 MT8195_MDP_COMP_RSZ0, /* 33 */ 88 MT8195_MDP_COMP_RSZ1, /* 34 */ 89 MT8195_MDP_COMP_RSZ2, /* 35 */ 90 MT8195_MDP_COMP_RSZ3, /* 36 */ 91 MT8195_MDP_COMP_TDSHP0, /* 37 */ 92 MT8195_MDP_COMP_TDSHP1, /* 38 */ 93 MT8195_MDP_COMP_TDSHP2, /* 39 */ 94 MT8195_MDP_COMP_TDSHP3, /* 40 */ 95 MT8195_MDP_COMP_COLOR0, /* 41 */ 96 MT8195_MDP_COMP_COLOR1, /* 42 */ 97 MT8195_MDP_COMP_COLOR2, /* 43 */ 98 MT8195_MDP_COMP_COLOR3, /* 44 */ 99 MT8195_MDP_COMP_OVL0, /* 45 */ 100 MT8195_MDP_COMP_OVL1, /* 46 */ 101 MT8195_MDP_COMP_PAD0, /* 47 */ 102 MT8195_MDP_COMP_PAD1, /* 48 */ 103 MT8195_MDP_COMP_PAD2, /* 49 */ 104 MT8195_MDP_COMP_PAD3, /* 50 */ 105 MT8195_MDP_COMP_TCC0, /* 51 */ 106 MT8195_MDP_COMP_TCC1, /* 52 */ 107 MT8195_MDP_COMP_WROT0, /* 53 */ 108 MT8195_MDP_COMP_WROT1, /* 54 */ 109 MT8195_MDP_COMP_WROT2, /* 55 */ 110 MT8195_MDP_COMP_WROT3, /* 56 */ 111 MT8195_MDP_COMP_MERGE2, /* 57 */ 112 MT8195_MDP_COMP_MERGE3, /* 58 */ 113 114 MT8195_MDP_COMP_VDO0DL0, /* 59 */ 115 MT8195_MDP_COMP_VDO1DL0, /* 60 */ 116 MT8195_MDP_COMP_VDO0DL1, /* 61 */ 117 MT8195_MDP_COMP_VDO1DL1, /* 62 */ 118 }; 119 120 static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = { 121 [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" }, 122 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8183-disp-mutex" }, 123 [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" } 124 }; 125 126 static const struct of_device_id mt8195_mdp_probe_infra[MDP_INFRA_MAX] = { 127 [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8195-vppsys0" }, 128 [MDP_INFRA_MMSYS2] = { .compatible = "mediatek,mt8195-vppsys1" }, 129 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8195-vpp-mutex" }, 130 [MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8195-vpp-mutex" }, 131 [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8195-scp" } 132 }; 133 134 static const struct mdp_platform_config mt8183_plat_cfg = { 135 .rdma_support_10bit = true, 136 .rdma_rsz1_sram_sharing = true, 137 .rdma_upsample_repeat_only = true, 138 .rdma_event_num = 1, 139 .rsz_disable_dcm_small_sample = false, 140 .wrot_filter_constraint = false, 141 .wrot_event_num = 1, 142 }; 143 144 static const struct mdp_platform_config mt8195_plat_cfg = { 145 .rdma_support_10bit = true, 146 .rdma_rsz1_sram_sharing = false, 147 .rdma_upsample_repeat_only = false, 148 .rdma_esl_setting = true, 149 .rdma_event_num = 4, 150 .rsz_disable_dcm_small_sample = false, 151 .rsz_etc_control = true, 152 .wrot_filter_constraint = false, 153 .wrot_event_num = 4, 154 .tdshp_hist_num = 17, 155 .tdshp_constrain = true, 156 .tdshp_contour = true, 157 }; 158 159 static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { 160 [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, 161 [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, 162 [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1, 163 [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0, 164 [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0, 165 [MDP_COMP_WDMA] = MUTEX_MOD_IDX_MDP_WDMA, 166 [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0, 167 [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0, 168 }; 169 170 static const u32 mt8195_mutex_idx[MDP_MAX_COMP_COUNT] = { 171 [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, 172 [MDP_COMP_RDMA1] = MUTEX_MOD_IDX_MDP_RDMA1, 173 [MDP_COMP_RDMA2] = MUTEX_MOD_IDX_MDP_RDMA2, 174 [MDP_COMP_RDMA3] = MUTEX_MOD_IDX_MDP_RDMA3, 175 [MDP_COMP_STITCH] = MUTEX_MOD_IDX_MDP_STITCH0, 176 [MDP_COMP_FG0] = MUTEX_MOD_IDX_MDP_FG0, 177 [MDP_COMP_FG1] = MUTEX_MOD_IDX_MDP_FG1, 178 [MDP_COMP_FG2] = MUTEX_MOD_IDX_MDP_FG2, 179 [MDP_COMP_FG3] = MUTEX_MOD_IDX_MDP_FG3, 180 [MDP_COMP_HDR0] = MUTEX_MOD_IDX_MDP_HDR0, 181 [MDP_COMP_HDR1] = MUTEX_MOD_IDX_MDP_HDR1, 182 [MDP_COMP_HDR2] = MUTEX_MOD_IDX_MDP_HDR2, 183 [MDP_COMP_HDR3] = MUTEX_MOD_IDX_MDP_HDR3, 184 [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0, 185 [MDP_COMP_AAL1] = MUTEX_MOD_IDX_MDP_AAL1, 186 [MDP_COMP_AAL2] = MUTEX_MOD_IDX_MDP_AAL2, 187 [MDP_COMP_AAL3] = MUTEX_MOD_IDX_MDP_AAL3, 188 [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, 189 [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1, 190 [MDP_COMP_RSZ2] = MUTEX_MOD_IDX_MDP_RSZ2, 191 [MDP_COMP_RSZ3] = MUTEX_MOD_IDX_MDP_RSZ3, 192 [MDP_COMP_MERGE2] = MUTEX_MOD_IDX_MDP_MERGE2, 193 [MDP_COMP_MERGE3] = MUTEX_MOD_IDX_MDP_MERGE3, 194 [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0, 195 [MDP_COMP_TDSHP1] = MUTEX_MOD_IDX_MDP_TDSHP1, 196 [MDP_COMP_TDSHP2] = MUTEX_MOD_IDX_MDP_TDSHP2, 197 [MDP_COMP_TDSHP3] = MUTEX_MOD_IDX_MDP_TDSHP3, 198 [MDP_COMP_COLOR0] = MUTEX_MOD_IDX_MDP_COLOR0, 199 [MDP_COMP_COLOR1] = MUTEX_MOD_IDX_MDP_COLOR1, 200 [MDP_COMP_COLOR2] = MUTEX_MOD_IDX_MDP_COLOR2, 201 [MDP_COMP_COLOR3] = MUTEX_MOD_IDX_MDP_COLOR3, 202 [MDP_COMP_OVL0] = MUTEX_MOD_IDX_MDP_OVL0, 203 [MDP_COMP_OVL1] = MUTEX_MOD_IDX_MDP_OVL1, 204 [MDP_COMP_PAD0] = MUTEX_MOD_IDX_MDP_PAD0, 205 [MDP_COMP_PAD1] = MUTEX_MOD_IDX_MDP_PAD1, 206 [MDP_COMP_PAD2] = MUTEX_MOD_IDX_MDP_PAD2, 207 [MDP_COMP_PAD3] = MUTEX_MOD_IDX_MDP_PAD3, 208 [MDP_COMP_TCC0] = MUTEX_MOD_IDX_MDP_TCC0, 209 [MDP_COMP_TCC1] = MUTEX_MOD_IDX_MDP_TCC1, 210 [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0, 211 [MDP_COMP_WROT1] = MUTEX_MOD_IDX_MDP_WROT1, 212 [MDP_COMP_WROT2] = MUTEX_MOD_IDX_MDP_WROT2, 213 [MDP_COMP_WROT3] = MUTEX_MOD_IDX_MDP_WROT3, 214 }; 215 216 static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = { 217 [MDP_COMP_WPEI] = { 218 {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, MDP_MM_SUBSYS_0}, 219 {0, 0, 0} 220 }, 221 [MDP_COMP_WPEO] = { 222 {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO, MDP_MM_SUBSYS_0}, 223 {0, 0, 0} 224 }, 225 [MDP_COMP_WPEI2] = { 226 {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0}, 227 {0, 0, 0} 228 }, 229 [MDP_COMP_WPEO2] = { 230 {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0}, 231 {0, 0, 0} 232 }, 233 [MDP_COMP_ISP_IMGI] = { 234 {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, MDP_MM_SUBSYS_0}, 235 {0, 0, 4} 236 }, 237 [MDP_COMP_ISP_IMGO] = { 238 {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO, MDP_MM_SUBSYS_0}, 239 {0, 0, 4} 240 }, 241 [MDP_COMP_ISP_IMG2O] = { 242 {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O, MDP_MM_SUBSYS_0}, 243 {0, 0, 0} 244 }, 245 [MDP_COMP_CAMIN] = { 246 {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0}, 247 {2, 2, 1} 248 }, 249 [MDP_COMP_CAMIN2] = { 250 {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0}, 251 {2, 4, 1} 252 }, 253 [MDP_COMP_RDMA0] = { 254 {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0}, 255 {2, 0, 0} 256 }, 257 [MDP_COMP_CCORR0] = { 258 {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0, MDP_MM_SUBSYS_0}, 259 {1, 0, 0} 260 }, 261 [MDP_COMP_RSZ0] = { 262 {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0}, 263 {1, 0, 0} 264 }, 265 [MDP_COMP_RSZ1] = { 266 {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1, MDP_MM_SUBSYS_0}, 267 {1, 0, 0} 268 }, 269 [MDP_COMP_TDSHP0] = { 270 {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0}, 271 {0, 0, 0} 272 }, 273 [MDP_COMP_PATH0_SOUT] = { 274 {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT, MDP_MM_SUBSYS_0}, 275 {0, 0, 0} 276 }, 277 [MDP_COMP_PATH1_SOUT] = { 278 {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT, MDP_MM_SUBSYS_0}, 279 {0, 0, 0} 280 }, 281 [MDP_COMP_WROT0] = { 282 {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0, MDP_MM_SUBSYS_0}, 283 {1, 0, 0} 284 }, 285 [MDP_COMP_WDMA] = { 286 {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA, MDP_MM_SUBSYS_0}, 287 {1, 0, 0} 288 }, 289 }; 290 291 static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT] = { 292 [MDP_COMP_WPEI] = { 293 {MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI, MDP_MM_SUBSYS_0}, 294 {0, 0, 0} 295 }, 296 [MDP_COMP_WPEO] = { 297 {MDP_COMP_TYPE_EXTO, 2, MT8195_MDP_COMP_WPEO, MDP_MM_SUBSYS_0}, 298 {0, 0, 0} 299 }, 300 [MDP_COMP_WPEI2] = { 301 {MDP_COMP_TYPE_WPEI, 1, MT8195_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0}, 302 {0, 0, 0} 303 }, 304 [MDP_COMP_WPEO2] = { 305 {MDP_COMP_TYPE_EXTO, 3, MT8195_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0}, 306 {0, 0, 0} 307 }, 308 [MDP_COMP_CAMIN] = { 309 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0}, 310 {3, 3, 0} 311 }, 312 [MDP_COMP_CAMIN2] = { 313 {MDP_COMP_TYPE_DL_PATH, 1, MT8195_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0}, 314 {3, 6, 0} 315 }, 316 [MDP_COMP_SPLIT] = { 317 {MDP_COMP_TYPE_SPLIT, 0, MT8195_MDP_COMP_SPLIT, MDP_MM_SUBSYS_1}, 318 {7, 0, 0} 319 }, 320 [MDP_COMP_SPLIT2] = { 321 {MDP_COMP_TYPE_SPLIT, 1, MT8195_MDP_COMP_SPLIT2, MDP_MM_SUBSYS_1}, 322 {7, 0, 0} 323 }, 324 [MDP_COMP_RDMA0] = { 325 {MDP_COMP_TYPE_RDMA, 0, MT8195_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0}, 326 {3, 0, 0} 327 }, 328 [MDP_COMP_RDMA1] = { 329 {MDP_COMP_TYPE_RDMA, 1, MT8195_MDP_COMP_RDMA1, MDP_MM_SUBSYS_1}, 330 {3, 0, 0} 331 }, 332 [MDP_COMP_RDMA2] = { 333 {MDP_COMP_TYPE_RDMA, 2, MT8195_MDP_COMP_RDMA2, MDP_MM_SUBSYS_1}, 334 {3, 0, 0} 335 }, 336 [MDP_COMP_RDMA3] = { 337 {MDP_COMP_TYPE_RDMA, 3, MT8195_MDP_COMP_RDMA3, MDP_MM_SUBSYS_1}, 338 {3, 0, 0} 339 }, 340 [MDP_COMP_STITCH] = { 341 {MDP_COMP_TYPE_STITCH, 0, MT8195_MDP_COMP_STITCH, MDP_MM_SUBSYS_0}, 342 {1, 0, 0} 343 }, 344 [MDP_COMP_FG0] = { 345 {MDP_COMP_TYPE_FG, 0, MT8195_MDP_COMP_FG0, MDP_MM_SUBSYS_0}, 346 {1, 0, 0} 347 }, 348 [MDP_COMP_FG1] = { 349 {MDP_COMP_TYPE_FG, 1, MT8195_MDP_COMP_FG1, MDP_MM_SUBSYS_1}, 350 {1, 0, 0} 351 }, 352 [MDP_COMP_FG2] = { 353 {MDP_COMP_TYPE_FG, 2, MT8195_MDP_COMP_FG2, MDP_MM_SUBSYS_1}, 354 {1, 0, 0} 355 }, 356 [MDP_COMP_FG3] = { 357 {MDP_COMP_TYPE_FG, 3, MT8195_MDP_COMP_FG3, MDP_MM_SUBSYS_1}, 358 {1, 0, 0} 359 }, 360 [MDP_COMP_HDR0] = { 361 {MDP_COMP_TYPE_HDR, 0, MT8195_MDP_COMP_HDR0, MDP_MM_SUBSYS_0}, 362 {1, 0, 0} 363 }, 364 [MDP_COMP_HDR1] = { 365 {MDP_COMP_TYPE_HDR, 1, MT8195_MDP_COMP_HDR1, MDP_MM_SUBSYS_1}, 366 {1, 0, 0} 367 }, 368 [MDP_COMP_HDR2] = { 369 {MDP_COMP_TYPE_HDR, 2, MT8195_MDP_COMP_HDR2, MDP_MM_SUBSYS_1}, 370 {1, 0, 0} 371 }, 372 [MDP_COMP_HDR3] = { 373 {MDP_COMP_TYPE_HDR, 3, MT8195_MDP_COMP_HDR3, MDP_MM_SUBSYS_1}, 374 {1, 0, 0} 375 }, 376 [MDP_COMP_AAL0] = { 377 {MDP_COMP_TYPE_AAL, 0, MT8195_MDP_COMP_AAL0, MDP_MM_SUBSYS_0}, 378 {1, 0, 0} 379 }, 380 [MDP_COMP_AAL1] = { 381 {MDP_COMP_TYPE_AAL, 1, MT8195_MDP_COMP_AAL1, MDP_MM_SUBSYS_1}, 382 {1, 0, 0} 383 }, 384 [MDP_COMP_AAL2] = { 385 {MDP_COMP_TYPE_AAL, 2, MT8195_MDP_COMP_AAL2, MDP_MM_SUBSYS_1}, 386 {1, 0, 0} 387 }, 388 [MDP_COMP_AAL3] = { 389 {MDP_COMP_TYPE_AAL, 3, MT8195_MDP_COMP_AAL3, MDP_MM_SUBSYS_1}, 390 {1, 0, 0} 391 }, 392 [MDP_COMP_RSZ0] = { 393 {MDP_COMP_TYPE_RSZ, 0, MT8195_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0}, 394 {1, 0, 0} 395 }, 396 [MDP_COMP_RSZ1] = { 397 {MDP_COMP_TYPE_RSZ, 1, MT8195_MDP_COMP_RSZ1, MDP_MM_SUBSYS_1}, 398 {1, 0, 0} 399 }, 400 [MDP_COMP_RSZ2] = { 401 {MDP_COMP_TYPE_RSZ, 2, MT8195_MDP_COMP_RSZ2, MDP_MM_SUBSYS_1}, 402 {2, 0, 0}, 403 {MDP_COMP_MERGE2, true, true} 404 }, 405 [MDP_COMP_RSZ3] = { 406 {MDP_COMP_TYPE_RSZ, 3, MT8195_MDP_COMP_RSZ3, MDP_MM_SUBSYS_1}, 407 {2, 0, 0}, 408 {MDP_COMP_MERGE3, true, true} 409 }, 410 [MDP_COMP_TDSHP0] = { 411 {MDP_COMP_TYPE_TDSHP, 0, MT8195_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0}, 412 {1, 0, 0} 413 }, 414 [MDP_COMP_TDSHP1] = { 415 {MDP_COMP_TYPE_TDSHP, 1, MT8195_MDP_COMP_TDSHP1, MDP_MM_SUBSYS_1}, 416 {1, 0, 0} 417 }, 418 [MDP_COMP_TDSHP2] = { 419 {MDP_COMP_TYPE_TDSHP, 2, MT8195_MDP_COMP_TDSHP2, MDP_MM_SUBSYS_1}, 420 {1, 0, 0} 421 }, 422 [MDP_COMP_TDSHP3] = { 423 {MDP_COMP_TYPE_TDSHP, 3, MT8195_MDP_COMP_TDSHP3, MDP_MM_SUBSYS_1}, 424 {1, 0, 0} 425 }, 426 [MDP_COMP_COLOR0] = { 427 {MDP_COMP_TYPE_COLOR, 0, MT8195_MDP_COMP_COLOR0, MDP_MM_SUBSYS_0}, 428 {1, 0, 0} 429 }, 430 [MDP_COMP_COLOR1] = { 431 {MDP_COMP_TYPE_COLOR, 1, MT8195_MDP_COMP_COLOR1, MDP_MM_SUBSYS_1}, 432 {1, 0, 0} 433 }, 434 [MDP_COMP_COLOR2] = { 435 {MDP_COMP_TYPE_COLOR, 2, MT8195_MDP_COMP_COLOR2, MDP_MM_SUBSYS_1}, 436 {1, 0, 0} 437 }, 438 [MDP_COMP_COLOR3] = { 439 {MDP_COMP_TYPE_COLOR, 3, MT8195_MDP_COMP_COLOR3, MDP_MM_SUBSYS_1}, 440 {1, 0, 0} 441 }, 442 [MDP_COMP_OVL0] = { 443 {MDP_COMP_TYPE_OVL, 0, MT8195_MDP_COMP_OVL0, MDP_MM_SUBSYS_0}, 444 {1, 0, 0} 445 }, 446 [MDP_COMP_OVL1] = { 447 {MDP_COMP_TYPE_OVL, 1, MT8195_MDP_COMP_OVL1, MDP_MM_SUBSYS_1}, 448 {1, 0, 0} 449 }, 450 [MDP_COMP_PAD0] = { 451 {MDP_COMP_TYPE_PAD, 0, MT8195_MDP_COMP_PAD0, MDP_MM_SUBSYS_0}, 452 {1, 0, 0} 453 }, 454 [MDP_COMP_PAD1] = { 455 {MDP_COMP_TYPE_PAD, 1, MT8195_MDP_COMP_PAD1, MDP_MM_SUBSYS_1}, 456 {1, 0, 0} 457 }, 458 [MDP_COMP_PAD2] = { 459 {MDP_COMP_TYPE_PAD, 2, MT8195_MDP_COMP_PAD2, MDP_MM_SUBSYS_1}, 460 {1, 0, 0} 461 }, 462 [MDP_COMP_PAD3] = { 463 {MDP_COMP_TYPE_PAD, 3, MT8195_MDP_COMP_PAD3, MDP_MM_SUBSYS_1}, 464 {1, 0, 0} 465 }, 466 [MDP_COMP_TCC0] = { 467 {MDP_COMP_TYPE_TCC, 0, MT8195_MDP_COMP_TCC0, MDP_MM_SUBSYS_0}, 468 {1, 0, 0} 469 }, 470 [MDP_COMP_TCC1] = { 471 {MDP_COMP_TYPE_TCC, 1, MT8195_MDP_COMP_TCC1, MDP_MM_SUBSYS_1}, 472 {1, 0, 0} 473 }, 474 [MDP_COMP_WROT0] = { 475 {MDP_COMP_TYPE_WROT, 0, MT8195_MDP_COMP_WROT0, MDP_MM_SUBSYS_0}, 476 {1, 0, 0} 477 }, 478 [MDP_COMP_WROT1] = { 479 {MDP_COMP_TYPE_WROT, 1, MT8195_MDP_COMP_WROT1, MDP_MM_SUBSYS_1}, 480 {1, 0, 0} 481 }, 482 [MDP_COMP_WROT2] = { 483 {MDP_COMP_TYPE_WROT, 2, MT8195_MDP_COMP_WROT2, MDP_MM_SUBSYS_1}, 484 {1, 0, 0} 485 }, 486 [MDP_COMP_WROT3] = { 487 {MDP_COMP_TYPE_WROT, 3, MT8195_MDP_COMP_WROT3, MDP_MM_SUBSYS_1}, 488 {1, 0, 0} 489 }, 490 [MDP_COMP_MERGE2] = { 491 {MDP_COMP_TYPE_MERGE, 0, MT8195_MDP_COMP_MERGE2, MDP_MM_SUBSYS_1}, 492 {1, 0, 0} 493 }, 494 [MDP_COMP_MERGE3] = { 495 {MDP_COMP_TYPE_MERGE, 1, MT8195_MDP_COMP_MERGE3, MDP_MM_SUBSYS_1}, 496 {1, 0, 0} 497 }, 498 [MDP_COMP_PQ0_SOUT] = { 499 {MDP_COMP_TYPE_DUMMY, 0, MT8195_MDP_COMP_PQ0_SOUT, MDP_MM_SUBSYS_0}, 500 {0, 0, 0} 501 }, 502 [MDP_COMP_PQ1_SOUT] = { 503 {MDP_COMP_TYPE_DUMMY, 1, MT8195_MDP_COMP_PQ1_SOUT, MDP_MM_SUBSYS_1}, 504 {0, 0, 0} 505 }, 506 [MDP_COMP_TO_WARP0MOUT] = { 507 {MDP_COMP_TYPE_DUMMY, 2, MT8195_MDP_COMP_TO_WARP0MOUT, MDP_MM_SUBSYS_0}, 508 {0, 0, 0} 509 }, 510 [MDP_COMP_TO_WARP1MOUT] = { 511 {MDP_COMP_TYPE_DUMMY, 3, MT8195_MDP_COMP_TO_WARP1MOUT, MDP_MM_SUBSYS_0}, 512 {0, 0, 0} 513 }, 514 [MDP_COMP_TO_SVPP2MOUT] = { 515 {MDP_COMP_TYPE_DUMMY, 4, MT8195_MDP_COMP_TO_SVPP2MOUT, MDP_MM_SUBSYS_1}, 516 {0, 0, 0} 517 }, 518 [MDP_COMP_TO_SVPP3MOUT] = { 519 {MDP_COMP_TYPE_DUMMY, 5, MT8195_MDP_COMP_TO_SVPP3MOUT, MDP_MM_SUBSYS_1}, 520 {0, 0, 0} 521 }, 522 [MDP_COMP_VPP0_SOUT] = { 523 {MDP_COMP_TYPE_PATH, 0, MT8195_MDP_COMP_VPP0_SOUT, MDP_MM_SUBSYS_1}, 524 {4, 9, 0} 525 }, 526 [MDP_COMP_VPP1_SOUT] = { 527 {MDP_COMP_TYPE_PATH, 1, MT8195_MDP_COMP_VPP1_SOUT, MDP_MM_SUBSYS_0}, 528 {2, 13, 0} 529 }, 530 [MDP_COMP_VDO0DL0] = { 531 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL0, MDP_MM_SUBSYS_1}, 532 {1, 15, 0} 533 }, 534 [MDP_COMP_VDO1DL0] = { 535 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL0, MDP_MM_SUBSYS_1}, 536 {1, 17, 0} 537 }, 538 [MDP_COMP_VDO0DL1] = { 539 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL1, MDP_MM_SUBSYS_1}, 540 {1, 18, 0} 541 }, 542 [MDP_COMP_VDO1DL1] = { 543 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL1, MDP_MM_SUBSYS_1}, 544 {1, 16, 0} 545 }, 546 }; 547 548 static const struct of_device_id mt8183_sub_comp_dt_ids[] = { 549 { 550 .compatible = "mediatek,mt8183-mdp3-wdma", 551 .data = (void *)MDP_COMP_TYPE_PATH, 552 }, { 553 .compatible = "mediatek,mt8183-mdp3-wrot", 554 .data = (void *)MDP_COMP_TYPE_PATH, 555 }, 556 {} 557 }; 558 559 static const struct of_device_id mt8195_sub_comp_dt_ids[] = { 560 {} 561 }; 562 563 /* 564 * All 10-bit related formats are not added in the basic format list, 565 * please add the corresponding format settings before use. 566 */ 567 static const struct mdp_format mt8183_formats[] = { 568 { 569 .pixelformat = V4L2_PIX_FMT_GREY, 570 .mdp_color = MDP_COLOR_GREY, 571 .depth = { 8 }, 572 .row_depth = { 8 }, 573 .num_planes = 1, 574 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 575 }, { 576 .pixelformat = V4L2_PIX_FMT_RGB565X, 577 .mdp_color = MDP_COLOR_BGR565, 578 .depth = { 16 }, 579 .row_depth = { 16 }, 580 .num_planes = 1, 581 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 582 }, { 583 .pixelformat = V4L2_PIX_FMT_RGB565, 584 .mdp_color = MDP_COLOR_RGB565, 585 .depth = { 16 }, 586 .row_depth = { 16 }, 587 .num_planes = 1, 588 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 589 }, { 590 .pixelformat = V4L2_PIX_FMT_RGB24, 591 .mdp_color = MDP_COLOR_RGB888, 592 .depth = { 24 }, 593 .row_depth = { 24 }, 594 .num_planes = 1, 595 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 596 }, { 597 .pixelformat = V4L2_PIX_FMT_BGR24, 598 .mdp_color = MDP_COLOR_BGR888, 599 .depth = { 24 }, 600 .row_depth = { 24 }, 601 .num_planes = 1, 602 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 603 }, { 604 .pixelformat = V4L2_PIX_FMT_ABGR32, 605 .mdp_color = MDP_COLOR_BGRA8888, 606 .depth = { 32 }, 607 .row_depth = { 32 }, 608 .num_planes = 1, 609 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 610 }, { 611 .pixelformat = V4L2_PIX_FMT_ARGB32, 612 .mdp_color = MDP_COLOR_ARGB8888, 613 .depth = { 32 }, 614 .row_depth = { 32 }, 615 .num_planes = 1, 616 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 617 }, { 618 .pixelformat = V4L2_PIX_FMT_UYVY, 619 .mdp_color = MDP_COLOR_UYVY, 620 .depth = { 16 }, 621 .row_depth = { 16 }, 622 .num_planes = 1, 623 .walign = 1, 624 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 625 }, { 626 .pixelformat = V4L2_PIX_FMT_VYUY, 627 .mdp_color = MDP_COLOR_VYUY, 628 .depth = { 16 }, 629 .row_depth = { 16 }, 630 .num_planes = 1, 631 .walign = 1, 632 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 633 }, { 634 .pixelformat = V4L2_PIX_FMT_YUYV, 635 .mdp_color = MDP_COLOR_YUYV, 636 .depth = { 16 }, 637 .row_depth = { 16 }, 638 .num_planes = 1, 639 .walign = 1, 640 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 641 }, { 642 .pixelformat = V4L2_PIX_FMT_YVYU, 643 .mdp_color = MDP_COLOR_YVYU, 644 .depth = { 16 }, 645 .row_depth = { 16 }, 646 .num_planes = 1, 647 .walign = 1, 648 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 649 }, { 650 .pixelformat = V4L2_PIX_FMT_YUV420, 651 .mdp_color = MDP_COLOR_I420, 652 .depth = { 12 }, 653 .row_depth = { 8 }, 654 .num_planes = 1, 655 .walign = 1, 656 .halign = 1, 657 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 658 }, { 659 .pixelformat = V4L2_PIX_FMT_YVU420, 660 .mdp_color = MDP_COLOR_YV12, 661 .depth = { 12 }, 662 .row_depth = { 8 }, 663 .num_planes = 1, 664 .walign = 1, 665 .halign = 1, 666 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 667 }, { 668 .pixelformat = V4L2_PIX_FMT_NV12, 669 .mdp_color = MDP_COLOR_NV12, 670 .depth = { 12 }, 671 .row_depth = { 8 }, 672 .num_planes = 1, 673 .walign = 1, 674 .halign = 1, 675 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 676 }, { 677 .pixelformat = V4L2_PIX_FMT_NV21, 678 .mdp_color = MDP_COLOR_NV21, 679 .depth = { 12 }, 680 .row_depth = { 8 }, 681 .num_planes = 1, 682 .walign = 1, 683 .halign = 1, 684 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 685 }, { 686 .pixelformat = V4L2_PIX_FMT_NV16, 687 .mdp_color = MDP_COLOR_NV16, 688 .depth = { 16 }, 689 .row_depth = { 8 }, 690 .num_planes = 1, 691 .walign = 1, 692 .flags = MDP_FMT_FLAG_OUTPUT, 693 }, { 694 .pixelformat = V4L2_PIX_FMT_NV61, 695 .mdp_color = MDP_COLOR_NV61, 696 .depth = { 16 }, 697 .row_depth = { 8 }, 698 .num_planes = 1, 699 .walign = 1, 700 .flags = MDP_FMT_FLAG_OUTPUT, 701 }, { 702 .pixelformat = V4L2_PIX_FMT_NV24, 703 .mdp_color = MDP_COLOR_NV24, 704 .depth = { 24 }, 705 .row_depth = { 8 }, 706 .num_planes = 1, 707 .flags = MDP_FMT_FLAG_OUTPUT, 708 }, { 709 .pixelformat = V4L2_PIX_FMT_NV42, 710 .mdp_color = MDP_COLOR_NV42, 711 .depth = { 24 }, 712 .row_depth = { 8 }, 713 .num_planes = 1, 714 .flags = MDP_FMT_FLAG_OUTPUT, 715 }, { 716 .pixelformat = V4L2_PIX_FMT_MT21C, 717 .mdp_color = MDP_COLOR_420_BLK_UFO, 718 .depth = { 8, 4 }, 719 .row_depth = { 8, 8 }, 720 .num_planes = 2, 721 .walign = 4, 722 .halign = 5, 723 .flags = MDP_FMT_FLAG_OUTPUT, 724 }, { 725 .pixelformat = V4L2_PIX_FMT_MM21, 726 .mdp_color = MDP_COLOR_420_BLK, 727 .depth = { 8, 4 }, 728 .row_depth = { 8, 8 }, 729 .num_planes = 2, 730 .walign = 4, 731 .halign = 5, 732 .flags = MDP_FMT_FLAG_OUTPUT, 733 }, { 734 .pixelformat = V4L2_PIX_FMT_NV12M, 735 .mdp_color = MDP_COLOR_NV12, 736 .depth = { 8, 4 }, 737 .row_depth = { 8, 8 }, 738 .num_planes = 2, 739 .walign = 1, 740 .halign = 1, 741 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 742 }, { 743 .pixelformat = V4L2_PIX_FMT_NV21M, 744 .mdp_color = MDP_COLOR_NV21, 745 .depth = { 8, 4 }, 746 .row_depth = { 8, 8 }, 747 .num_planes = 2, 748 .walign = 1, 749 .halign = 1, 750 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 751 }, { 752 .pixelformat = V4L2_PIX_FMT_NV16M, 753 .mdp_color = MDP_COLOR_NV16, 754 .depth = { 8, 8 }, 755 .row_depth = { 8, 8 }, 756 .num_planes = 2, 757 .walign = 1, 758 .flags = MDP_FMT_FLAG_OUTPUT, 759 }, { 760 .pixelformat = V4L2_PIX_FMT_NV61M, 761 .mdp_color = MDP_COLOR_NV61, 762 .depth = { 8, 8 }, 763 .row_depth = { 8, 8 }, 764 .num_planes = 2, 765 .walign = 1, 766 .flags = MDP_FMT_FLAG_OUTPUT, 767 }, { 768 .pixelformat = V4L2_PIX_FMT_YUV420M, 769 .mdp_color = MDP_COLOR_I420, 770 .depth = { 8, 2, 2 }, 771 .row_depth = { 8, 4, 4 }, 772 .num_planes = 3, 773 .walign = 1, 774 .halign = 1, 775 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 776 }, { 777 .pixelformat = V4L2_PIX_FMT_YVU420M, 778 .mdp_color = MDP_COLOR_YV12, 779 .depth = { 8, 2, 2 }, 780 .row_depth = { 8, 4, 4 }, 781 .num_planes = 3, 782 .walign = 1, 783 .halign = 1, 784 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 785 } 786 }; 787 788 static const struct mdp_format mt8195_formats[] = { 789 { 790 .pixelformat = V4L2_PIX_FMT_GREY, 791 .mdp_color = MDP_COLOR_GREY, 792 .depth = { 8 }, 793 .row_depth = { 8 }, 794 .num_planes = 1, 795 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 796 }, { 797 .pixelformat = V4L2_PIX_FMT_RGB565X, 798 .mdp_color = MDP_COLOR_BGR565, 799 .depth = { 16 }, 800 .row_depth = { 16 }, 801 .num_planes = 1, 802 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 803 }, { 804 .pixelformat = V4L2_PIX_FMT_RGB565, 805 .mdp_color = MDP_COLOR_RGB565, 806 .depth = { 16 }, 807 .row_depth = { 16 }, 808 .num_planes = 1, 809 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 810 }, { 811 .pixelformat = V4L2_PIX_FMT_RGB24, 812 .mdp_color = MDP_COLOR_RGB888, 813 .depth = { 24 }, 814 .row_depth = { 24 }, 815 .num_planes = 1, 816 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 817 }, { 818 .pixelformat = V4L2_PIX_FMT_BGR24, 819 .mdp_color = MDP_COLOR_BGR888, 820 .depth = { 24 }, 821 .row_depth = { 24 }, 822 .num_planes = 1, 823 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 824 }, { 825 .pixelformat = V4L2_PIX_FMT_ABGR32, 826 .mdp_color = MDP_COLOR_BGRA8888, 827 .depth = { 32 }, 828 .row_depth = { 32 }, 829 .num_planes = 1, 830 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 831 }, { 832 .pixelformat = V4L2_PIX_FMT_ARGB32, 833 .mdp_color = MDP_COLOR_ARGB8888, 834 .depth = { 32 }, 835 .row_depth = { 32 }, 836 .num_planes = 1, 837 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 838 }, { 839 .pixelformat = V4L2_PIX_FMT_UYVY, 840 .mdp_color = MDP_COLOR_UYVY, 841 .depth = { 16 }, 842 .row_depth = { 16 }, 843 .num_planes = 1, 844 .walign = 1, 845 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 846 }, { 847 .pixelformat = V4L2_PIX_FMT_VYUY, 848 .mdp_color = MDP_COLOR_VYUY, 849 .depth = { 16 }, 850 .row_depth = { 16 }, 851 .num_planes = 1, 852 .walign = 1, 853 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 854 }, { 855 .pixelformat = V4L2_PIX_FMT_YUYV, 856 .mdp_color = MDP_COLOR_YUYV, 857 .depth = { 16 }, 858 .row_depth = { 16 }, 859 .num_planes = 1, 860 .walign = 1, 861 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 862 }, { 863 .pixelformat = V4L2_PIX_FMT_YVYU, 864 .mdp_color = MDP_COLOR_YVYU, 865 .depth = { 16 }, 866 .row_depth = { 16 }, 867 .num_planes = 1, 868 .walign = 1, 869 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 870 }, { 871 .pixelformat = V4L2_PIX_FMT_YUV420, 872 .mdp_color = MDP_COLOR_I420, 873 .depth = { 12 }, 874 .row_depth = { 8 }, 875 .num_planes = 1, 876 .walign = 1, 877 .halign = 1, 878 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 879 }, { 880 .pixelformat = V4L2_PIX_FMT_YVU420, 881 .mdp_color = MDP_COLOR_YV12, 882 .depth = { 12 }, 883 .row_depth = { 8 }, 884 .num_planes = 1, 885 .walign = 1, 886 .halign = 1, 887 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 888 }, { 889 .pixelformat = V4L2_PIX_FMT_NV12, 890 .mdp_color = MDP_COLOR_NV12, 891 .depth = { 12 }, 892 .row_depth = { 8 }, 893 .num_planes = 1, 894 .walign = 1, 895 .halign = 1, 896 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 897 }, { 898 .pixelformat = V4L2_PIX_FMT_NV21, 899 .mdp_color = MDP_COLOR_NV21, 900 .depth = { 12 }, 901 .row_depth = { 8 }, 902 .num_planes = 1, 903 .walign = 1, 904 .halign = 1, 905 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 906 }, { 907 .pixelformat = V4L2_PIX_FMT_NV16, 908 .mdp_color = MDP_COLOR_NV16, 909 .depth = { 16 }, 910 .row_depth = { 8 }, 911 .num_planes = 1, 912 .walign = 1, 913 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 914 }, { 915 .pixelformat = V4L2_PIX_FMT_NV61, 916 .mdp_color = MDP_COLOR_NV61, 917 .depth = { 16 }, 918 .row_depth = { 8 }, 919 .num_planes = 1, 920 .walign = 1, 921 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 922 }, { 923 .pixelformat = V4L2_PIX_FMT_NV12M, 924 .mdp_color = MDP_COLOR_NV12, 925 .depth = { 8, 4 }, 926 .row_depth = { 8, 8 }, 927 .num_planes = 2, 928 .walign = 1, 929 .halign = 1, 930 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 931 }, { 932 .pixelformat = V4L2_PIX_FMT_MM21, 933 .mdp_color = MDP_COLOR_420_BLK, 934 .depth = { 8, 4 }, 935 .row_depth = { 8, 8 }, 936 .num_planes = 2, 937 .walign = 6, 938 .halign = 6, 939 .flags = MDP_FMT_FLAG_OUTPUT, 940 }, { 941 .pixelformat = V4L2_PIX_FMT_NV21M, 942 .mdp_color = MDP_COLOR_NV21, 943 .depth = { 8, 4 }, 944 .row_depth = { 8, 8 }, 945 .num_planes = 2, 946 .walign = 1, 947 .halign = 1, 948 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 949 }, { 950 .pixelformat = V4L2_PIX_FMT_NV16M, 951 .mdp_color = MDP_COLOR_NV16, 952 .depth = { 8, 8 }, 953 .row_depth = { 8, 8 }, 954 .num_planes = 2, 955 .walign = 1, 956 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 957 }, { 958 .pixelformat = V4L2_PIX_FMT_NV61M, 959 .mdp_color = MDP_COLOR_NV61, 960 .depth = { 8, 8 }, 961 .row_depth = { 8, 8 }, 962 .num_planes = 2, 963 .walign = 1, 964 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 965 }, { 966 .pixelformat = V4L2_PIX_FMT_YUV420M, 967 .mdp_color = MDP_COLOR_I420, 968 .depth = { 8, 2, 2 }, 969 .row_depth = { 8, 4, 4 }, 970 .num_planes = 3, 971 .walign = 1, 972 .halign = 1, 973 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 974 }, { 975 .pixelformat = V4L2_PIX_FMT_YVU420M, 976 .mdp_color = MDP_COLOR_YV12, 977 .depth = { 8, 2, 2 }, 978 .row_depth = { 8, 4, 4 }, 979 .num_planes = 3, 980 .walign = 1, 981 .halign = 1, 982 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 983 }, { 984 .pixelformat = V4L2_PIX_FMT_YUV422M, 985 .mdp_color = MDP_COLOR_I422, 986 .depth = { 8, 4, 4 }, 987 .row_depth = { 8, 4, 4 }, 988 .num_planes = 3, 989 .walign = 1, 990 .halign = 1, 991 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 992 }, { 993 .pixelformat = V4L2_PIX_FMT_YVU422M, 994 .mdp_color = MDP_COLOR_YV16, 995 .depth = { 8, 4, 4 }, 996 .row_depth = { 8, 4, 4 }, 997 .num_planes = 3, 998 .walign = 1, 999 .halign = 1, 1000 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, 1001 } 1002 }; 1003 1004 static const struct mdp_limit mt8183_mdp_def_limit = { 1005 .out_limit = { 1006 .wmin = 16, 1007 .hmin = 16, 1008 .wmax = 8176, 1009 .hmax = 8176, 1010 }, 1011 .cap_limit = { 1012 .wmin = 2, 1013 .hmin = 2, 1014 .wmax = 8176, 1015 .hmax = 8176, 1016 }, 1017 .h_scale_up_max = 32, 1018 .v_scale_up_max = 32, 1019 .h_scale_down_max = 20, 1020 .v_scale_down_max = 128, 1021 }; 1022 1023 static const struct mdp_limit mt8195_mdp_def_limit = { 1024 .out_limit = { 1025 .wmin = 64, 1026 .hmin = 64, 1027 .wmax = 8192, 1028 .hmax = 8192, 1029 }, 1030 .cap_limit = { 1031 .wmin = 64, 1032 .hmin = 64, 1033 .wmax = 8192, 1034 .hmax = 8192, 1035 }, 1036 .h_scale_up_max = 64, 1037 .v_scale_up_max = 64, 1038 .h_scale_down_max = 128, 1039 .v_scale_down_max = 128, 1040 }; 1041 1042 static const struct mdp_pipe_info mt8183_pipe_info[] = { 1043 [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0}, 1044 [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1}, 1045 [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2}, 1046 [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3} 1047 }; 1048 1049 static const struct mdp_pipe_info mt8195_pipe_info[] = { 1050 [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0}, 1051 [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1}, 1052 [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2}, 1053 [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3}, 1054 [MDP_PIPE_RDMA1] = {MDP_PIPE_RDMA1, MDP_MM_SUBSYS_1, 0}, 1055 [MDP_PIPE_RDMA2] = {MDP_PIPE_RDMA2, MDP_MM_SUBSYS_1, 1}, 1056 [MDP_PIPE_RDMA3] = {MDP_PIPE_RDMA3, MDP_MM_SUBSYS_1, 2}, 1057 [MDP_PIPE_SPLIT] = {MDP_PIPE_SPLIT, MDP_MM_SUBSYS_1, 3}, 1058 [MDP_PIPE_SPLIT2] = {MDP_PIPE_SPLIT2, MDP_MM_SUBSYS_1, 4}, 1059 [MDP_PIPE_VPP1_SOUT] = {MDP_PIPE_VPP1_SOUT, MDP_MM_SUBSYS_0, 4}, 1060 [MDP_PIPE_VPP0_SOUT] = {MDP_PIPE_VPP0_SOUT, MDP_MM_SUBSYS_1, 5}, 1061 }; 1062 1063 static const struct v4l2_rect mt8195_mdp_pp_criteria = { 1064 .width = 1920, 1065 .height = 1080, 1066 }; 1067 1068 const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { 1069 .mdp_plat_id = MT8183, 1070 .mdp_con_res = 0x14001000, 1071 .mdp_probe_infra = mt8183_mdp_probe_infra, 1072 .mdp_cfg = &mt8183_plat_cfg, 1073 .mdp_mutex_table_idx = mt8183_mutex_idx, 1074 .comp_data = mt8183_mdp_comp_data, 1075 .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data), 1076 .mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids, 1077 .format = mt8183_formats, 1078 .format_len = ARRAY_SIZE(mt8183_formats), 1079 .def_limit = &mt8183_mdp_def_limit, 1080 .pipe_info = mt8183_pipe_info, 1081 .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info), 1082 .pp_used = MDP_PP_USED_1, 1083 }; 1084 1085 const struct mtk_mdp_driver_data mt8195_mdp_driver_data = { 1086 .mdp_plat_id = MT8195, 1087 .mdp_con_res = 0x14001000, 1088 .mdp_probe_infra = mt8195_mdp_probe_infra, 1089 .mdp_sub_comp_dt_ids = mt8195_sub_comp_dt_ids, 1090 .mdp_cfg = &mt8195_plat_cfg, 1091 .mdp_mutex_table_idx = mt8195_mutex_idx, 1092 .comp_data = mt8195_mdp_comp_data, 1093 .comp_data_len = ARRAY_SIZE(mt8195_mdp_comp_data), 1094 .format = mt8195_formats, 1095 .format_len = ARRAY_SIZE(mt8195_formats), 1096 .def_limit = &mt8195_mdp_def_limit, 1097 .pipe_info = mt8195_pipe_info, 1098 .pipe_info_len = ARRAY_SIZE(mt8195_pipe_info), 1099 .pp_criteria = &mt8195_mdp_pp_criteria, 1100 .pp_used = MDP_PP_USED_2, 1101 }; 1102 1103 s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) 1104 { 1105 if (!mdp_dev) 1106 return MDP_COMP_NONE; 1107 if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT) 1108 return MDP_COMP_NONE; 1109 1110 return mdp_dev->mdp_data->comp_data[id].match.inner_id; 1111 } 1112 1113 enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 inner_id) 1114 { 1115 enum mtk_mdp_comp_id public_id = MDP_COMP_NONE; 1116 u32 i; 1117 1118 if (IS_ERR(mdp_dev) || !inner_id) 1119 goto err_public_id; 1120 1121 for (i = 0; i < MDP_MAX_COMP_COUNT; i++) { 1122 if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) { 1123 public_id = i; 1124 return public_id; 1125 } 1126 } 1127 1128 err_public_id: 1129 return public_id; 1130 } 1131 1132 bool mdp_cfg_comp_is_dummy(struct mdp_dev *mdp_dev, s32 inner_id) 1133 { 1134 enum mtk_mdp_comp_id id = mdp_cfg_get_id_public(mdp_dev, inner_id); 1135 enum mdp_comp_type type = mdp_dev->mdp_data->comp_data[id].match.type; 1136 1137 return (type == MDP_COMP_TYPE_DUMMY); 1138 } 1139