1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Marvell camera core structures. 4 * 5 * Copyright 2011 Jonathan Corbet corbet@lwn.net 6 */ 7 #ifndef _MCAM_CORE_H 8 #define _MCAM_CORE_H 9 10 #include <linux/list.h> 11 #include <linux/clk-provider.h> 12 #include <linux/workqueue.h> 13 #include <media/v4l2-common.h> 14 #include <media/v4l2-ctrls.h> 15 #include <media/v4l2-dev.h> 16 #include <media/videobuf2-v4l2.h> 17 18 /* 19 * Create our own symbols for the supported buffer modes, but, for now, 20 * base them entirely on which videobuf2 options have been selected. 21 */ 22 #if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC) 23 #define MCAM_MODE_VMALLOC 1 24 #endif 25 26 #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG) 27 #define MCAM_MODE_DMA_CONTIG 1 28 #endif 29 30 #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG) 31 #define MCAM_MODE_DMA_SG 1 32 #endif 33 34 #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \ 35 !defined(MCAM_MODE_DMA_SG) 36 #error One of the vb2 buffer modes must be selected in the config 37 #endif 38 39 40 enum mcam_state { 41 S_NOTREADY, /* Not yet initialized */ 42 S_IDLE, /* Just hanging around */ 43 S_FLAKED, /* Some sort of problem */ 44 S_STREAMING, /* Streaming data */ 45 S_BUFWAIT /* streaming requested but no buffers yet */ 46 }; 47 #define MAX_DMA_BUFS 3 48 49 /* 50 * Different platforms work best with different buffer modes, so we 51 * let the platform pick. 52 */ 53 enum mcam_buffer_mode { 54 B_vmalloc = 0, 55 B_DMA_contig = 1, 56 B_DMA_sg = 2 57 }; 58 59 enum mcam_chip_id { 60 MCAM_CAFE, 61 MCAM_ARMADA610, 62 }; 63 64 /* 65 * Is a given buffer mode supported by the current kernel configuration? 66 */ 67 static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode) 68 { 69 switch (mode) { 70 #ifdef MCAM_MODE_VMALLOC 71 case B_vmalloc: 72 #endif 73 #ifdef MCAM_MODE_DMA_CONTIG 74 case B_DMA_contig: 75 #endif 76 #ifdef MCAM_MODE_DMA_SG 77 case B_DMA_sg: 78 #endif 79 return 1; 80 default: 81 return 0; 82 } 83 } 84 85 /* 86 * Basic frame states 87 */ 88 struct mcam_frame_state { 89 unsigned int frames; 90 unsigned int singles; 91 unsigned int delivered; 92 }; 93 94 #define NR_MCAM_CLK 3 95 96 /* 97 * A description of one of our devices. 98 * Locking: controlled by s_mutex. Certain fields, however, require 99 * the dev_lock spinlock; they are marked as such by comments. 100 * dev_lock is also required for access to device registers. 101 */ 102 struct mcam_camera { 103 /* 104 * These fields should be set by the platform code prior to 105 * calling mcam_register(). 106 */ 107 unsigned char __iomem *regs; 108 unsigned regs_size; /* size in bytes of the register space */ 109 spinlock_t dev_lock; 110 struct device *dev; /* For messages, dma alloc */ 111 enum mcam_chip_id chip_id; 112 enum mcam_buffer_mode buffer_mode; 113 114 int mclk_src; /* which clock source the mclk derives from */ 115 int mclk_div; /* Clock Divider Value for MCLK */ 116 117 enum v4l2_mbus_type bus_type; 118 /* MIPI support */ 119 /* The dphy config value, allocated in board file 120 * dphy[0]: DPHY3 121 * dphy[1]: DPHY5 122 * dphy[2]: DPHY6 123 */ 124 int *dphy; 125 bool mipi_enabled; /* flag whether mipi is enabled already */ 126 int lane; /* lane number */ 127 128 /* clock tree support */ 129 struct clk *clk[NR_MCAM_CLK]; 130 struct clk_hw mclk_hw; 131 struct clk *mclk; 132 133 /* 134 * Callbacks from the core to the platform code. 135 */ 136 int (*plat_power_up) (struct mcam_camera *cam); 137 void (*plat_power_down) (struct mcam_camera *cam); 138 void (*calc_dphy) (struct mcam_camera *cam); 139 140 /* 141 * Everything below here is private to the mcam core and 142 * should not be touched by the platform code. 143 */ 144 struct v4l2_device v4l2_dev; 145 struct v4l2_ctrl_handler ctrl_handler; 146 enum mcam_state state; 147 unsigned long flags; /* Buffer status, mainly (dev_lock) */ 148 149 struct mcam_frame_state frame_state; /* Frame state counter */ 150 /* 151 * Subsystem structures. 152 */ 153 struct video_device vdev; 154 struct v4l2_async_notifier notifier; 155 struct v4l2_subdev *sensor; 156 157 /* Videobuf2 stuff */ 158 struct vb2_queue vb_queue; 159 struct list_head buffers; /* Available frames */ 160 161 unsigned int nbufs; /* How many are alloc'd */ 162 int next_buf; /* Next to consume (dev_lock) */ 163 164 char bus_info[32]; /* querycap bus_info */ 165 166 /* DMA buffers - vmalloc mode */ 167 #ifdef MCAM_MODE_VMALLOC 168 unsigned int dma_buf_size; /* allocated size */ 169 void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */ 170 dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */ 171 struct work_struct s_bh_work; 172 #endif 173 unsigned int sequence; /* Frame sequence number */ 174 unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */ 175 176 /* DMA buffers - DMA modes */ 177 struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS]; 178 179 /* Mode-specific ops, set at open time */ 180 void (*dma_setup)(struct mcam_camera *cam); 181 void (*frame_complete)(struct mcam_camera *cam, int frame); 182 183 /* Current operating parameters */ 184 struct v4l2_pix_format pix_format; 185 u32 mbus_code; 186 187 /* Locks */ 188 struct mutex s_mutex; /* Access to this structure */ 189 }; 190 191 192 /* 193 * Register I/O functions. These are here because the platform code 194 * may legitimately need to mess with the register space. 195 */ 196 /* 197 * Device register I/O 198 */ 199 static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg, 200 unsigned int val) 201 { 202 iowrite32(val, cam->regs + reg); 203 } 204 205 static inline unsigned int mcam_reg_read(struct mcam_camera *cam, 206 unsigned int reg) 207 { 208 return ioread32(cam->regs + reg); 209 } 210 211 212 static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg, 213 unsigned int val, unsigned int mask) 214 { 215 unsigned int v = mcam_reg_read(cam, reg); 216 217 v = (v & ~mask) | (val & mask); 218 mcam_reg_write(cam, reg, v); 219 } 220 221 static inline void mcam_reg_clear_bit(struct mcam_camera *cam, 222 unsigned int reg, unsigned int val) 223 { 224 mcam_reg_write_mask(cam, reg, 0, val); 225 } 226 227 static inline void mcam_reg_set_bit(struct mcam_camera *cam, 228 unsigned int reg, unsigned int val) 229 { 230 mcam_reg_write_mask(cam, reg, val, val); 231 } 232 233 /* 234 * Functions for use by platform code. 235 */ 236 int mccic_register(struct mcam_camera *cam); 237 int mccic_irq(struct mcam_camera *cam, unsigned int irqs); 238 void mccic_shutdown(struct mcam_camera *cam); 239 void mccic_suspend(struct mcam_camera *cam); 240 int mccic_resume(struct mcam_camera *cam); 241 242 /* 243 * Register definitions for the m88alp01 camera interface. Offsets in bytes 244 * as given in the spec. 245 */ 246 #define REG_Y0BAR 0x00 247 #define REG_Y1BAR 0x04 248 #define REG_Y2BAR 0x08 249 #define REG_U0BAR 0x0c 250 #define REG_U1BAR 0x10 251 #define REG_U2BAR 0x14 252 #define REG_V0BAR 0x18 253 #define REG_V1BAR 0x1C 254 #define REG_V2BAR 0x20 255 256 /* 257 * register definitions for MIPI support 258 */ 259 #define REG_CSI2_CTRL0 0x100 260 #define CSI2_C0_MIPI_EN (0x1 << 0) 261 #define CSI2_C0_ACT_LANE(n) ((n-1) << 1) 262 #define REG_CSI2_DPHY3 0x12c 263 #define REG_CSI2_DPHY5 0x134 264 #define REG_CSI2_DPHY6 0x138 265 266 /* ... */ 267 268 #define REG_IMGPITCH 0x24 /* Image pitch register */ 269 #define IMGP_YP_SHFT 2 /* Y pitch params */ 270 #define IMGP_YP_MASK 0x00003ffc /* Y pitch field */ 271 #define IMGP_UVP_SHFT 18 /* UV pitch (planar) */ 272 #define IMGP_UVP_MASK 0x3ffc0000 273 #define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */ 274 #define IRQ_EOF0 0x00000001 /* End of frame 0 */ 275 #define IRQ_EOF1 0x00000002 /* End of frame 1 */ 276 #define IRQ_EOF2 0x00000004 /* End of frame 2 */ 277 #define IRQ_SOF0 0x00000008 /* Start of frame 0 */ 278 #define IRQ_SOF1 0x00000010 /* Start of frame 1 */ 279 #define IRQ_SOF2 0x00000020 /* Start of frame 2 */ 280 #define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */ 281 #define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */ 282 #define IRQ_TWSIR 0x00020000 /* TWSI read */ 283 #define IRQ_TWSIE 0x00040000 /* TWSI error */ 284 #define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE) 285 #define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2) 286 #define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW) 287 #define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */ 288 #define REG_IRQSTAT 0x30 /* IRQ status / clear */ 289 290 #define REG_IMGSIZE 0x34 /* Image size */ 291 #define IMGSZ_V_MASK 0x1fff0000 292 #define IMGSZ_V_SHIFT 16 293 #define IMGSZ_H_MASK 0x00003fff 294 #define REG_IMGOFFSET 0x38 /* IMage offset */ 295 296 #define REG_CTRL0 0x3c /* Control 0 */ 297 #define C0_ENABLE 0x00000001 /* Makes the whole thing go */ 298 299 /* Mask for all the format bits */ 300 #define C0_DF_MASK 0x00fffffc /* Bits 2-23 */ 301 302 /* RGB ordering */ 303 #define C0_RGB4_RGBX 0x00000000 304 #define C0_RGB4_XRGB 0x00000004 305 #define C0_RGB4_BGRX 0x00000008 306 #define C0_RGB4_XBGR 0x0000000c 307 #define C0_RGB5_RGGB 0x00000000 308 #define C0_RGB5_GRBG 0x00000004 309 #define C0_RGB5_GBRG 0x00000008 310 #define C0_RGB5_BGGR 0x0000000c 311 312 /* Spec has two fields for DIN and DOUT, but they must match, so 313 combine them here. */ 314 #define C0_DF_YUV 0x00000000 /* Data is YUV */ 315 #define C0_DF_RGB 0x000000a0 /* ... RGB */ 316 #define C0_DF_BAYER 0x00000140 /* ... Bayer */ 317 /* 8-8-8 must be missing from the below - ask */ 318 #define C0_RGBF_565 0x00000000 319 #define C0_RGBF_444 0x00000800 320 #define C0_RGB_BGR 0x00001000 /* Blue comes first */ 321 #define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */ 322 #define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */ 323 #define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */ 324 /* Think that 420 packed must be 111 - ask */ 325 #define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */ 326 #define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */ 327 #define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */ 328 #define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */ 329 #define C0_YUVE_NOSWAP 0x00000000 /* no bytes swapping */ 330 #define C0_YUVE_SWAP13 0x00010000 /* swap byte 1 and 3 */ 331 #define C0_YUVE_SWAP24 0x00020000 /* swap byte 2 and 4 */ 332 #define C0_YUVE_SWAP1324 0x00030000 /* swap bytes 1&3 and 2&4 */ 333 /* Bayer bits 18,19 if needed */ 334 #define C0_EOF_VSYNC 0x00400000 /* Generate EOF by VSYNC */ 335 #define C0_VEDGE_CTRL 0x00800000 /* Detect falling edge of VSYNC */ 336 #define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */ 337 #define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */ 338 #define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */ 339 #define C0_DOWNSCALE 0x08000000 /* Enable downscaler */ 340 /* SIFMODE */ 341 #define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */ 342 #define C0_SOF_NOSYNC 0x40000000 /* Use inband active signaling */ 343 #define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */ 344 345 /* Bits below C1_444ALPHA are not present in Cafe */ 346 #define REG_CTRL1 0x40 /* Control 1 */ 347 #define C1_CLKGATE 0x00000001 /* Sensor clock gate */ 348 #define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */ 349 #define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */ 350 #define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */ 351 #define C1_ALPHA_SHFT 20 352 #define C1_DMAB32 0x00000000 /* 32-byte DMA burst */ 353 #define C1_DMAB16 0x02000000 /* 16-byte DMA burst */ 354 #define C1_DMAB64 0x04000000 /* 64-byte DMA burst */ 355 #define C1_DMAB_MASK 0x06000000 356 #define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */ 357 #define C1_PWRDWN 0x10000000 /* Power down */ 358 359 #define REG_CLKCTRL 0x88 /* Clock control */ 360 #define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */ 361 362 /* This appears to be a Cafe-only register */ 363 #define REG_UBAR 0xc4 /* Upper base address register */ 364 365 /* Armada 610 DMA descriptor registers */ 366 #define REG_DMA_DESC_Y 0x200 367 #define REG_DMA_DESC_U 0x204 368 #define REG_DMA_DESC_V 0x208 369 #define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */ 370 #define REG_DESC_LEN_U 0x210 371 #define REG_DESC_LEN_V 0x214 372 373 /* 374 * Useful stuff that probably belongs somewhere global. 375 */ 376 #define VGA_WIDTH 640 377 #define VGA_HEIGHT 480 378 379 #endif /* _MCAM_CORE_H */ 380