1*a1e29404SDevarsh Thakkar /* SPDX-License-Identifier: GPL-2.0 */ 2*a1e29404SDevarsh Thakkar /* 3*a1e29404SDevarsh Thakkar * Imagination E5010 JPEG Encoder driver. 4*a1e29404SDevarsh Thakkar * 5*a1e29404SDevarsh Thakkar * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6*a1e29404SDevarsh Thakkar * 7*a1e29404SDevarsh Thakkar * Author: David Huang <d-huang@ti.com> 8*a1e29404SDevarsh Thakkar * Author: Devarsh Thakkar <devarsht@ti.com> 9*a1e29404SDevarsh Thakkar */ 10*a1e29404SDevarsh Thakkar 11*a1e29404SDevarsh Thakkar #include <media/v4l2-ctrls.h> 12*a1e29404SDevarsh Thakkar #include <media/v4l2-device.h> 13*a1e29404SDevarsh Thakkar #include <media/v4l2-fh.h> 14*a1e29404SDevarsh Thakkar 15*a1e29404SDevarsh Thakkar #ifndef _E5010_JPEG_ENC_H 16*a1e29404SDevarsh Thakkar #define _E5010_JPEG_ENC_H 17*a1e29404SDevarsh Thakkar 18*a1e29404SDevarsh Thakkar #define MAX_PLANES 2 19*a1e29404SDevarsh Thakkar #define HEADER_SIZE 0x025D 20*a1e29404SDevarsh Thakkar #define MIN_DIMENSION 64 21*a1e29404SDevarsh Thakkar #define MAX_DIMENSION 8192 22*a1e29404SDevarsh Thakkar #define DEFAULT_WIDTH 640 23*a1e29404SDevarsh Thakkar #define DEFAULT_HEIGHT 480 24*a1e29404SDevarsh Thakkar #define E5010_MODULE_NAME "e5010" 25*a1e29404SDevarsh Thakkar #define JPEG_MAX_BYTES_PER_PIXEL 2 26*a1e29404SDevarsh Thakkar 27*a1e29404SDevarsh Thakkar /* JPEG marker definitions */ 28*a1e29404SDevarsh Thakkar #define START_OF_IMAGE 0xFFD8 29*a1e29404SDevarsh Thakkar #define SOF_BASELINE_DCT 0xFFC0 30*a1e29404SDevarsh Thakkar #define END_OF_IMAGE 0xFFD9 31*a1e29404SDevarsh Thakkar #define START_OF_SCAN 0xFFDA 32*a1e29404SDevarsh Thakkar 33*a1e29404SDevarsh Thakkar /* Definitions for the huffman table specification in the Marker segment */ 34*a1e29404SDevarsh Thakkar #define DHT_MARKER 0xFFC4 35*a1e29404SDevarsh Thakkar #define LH_DC 0x001F 36*a1e29404SDevarsh Thakkar #define LH_AC 0x00B5 37*a1e29404SDevarsh Thakkar 38*a1e29404SDevarsh Thakkar /* Definitions for the quantization table specification in the Marker segment */ 39*a1e29404SDevarsh Thakkar #define DQT_MARKER 0xFFDB 40*a1e29404SDevarsh Thakkar #define ACMAX 0x03FF 41*a1e29404SDevarsh Thakkar #define DCMAX 0x07FF 42*a1e29404SDevarsh Thakkar 43*a1e29404SDevarsh Thakkar /* Length and precision of the quantization table parameters */ 44*a1e29404SDevarsh Thakkar #define LQPQ 0x00430 45*a1e29404SDevarsh Thakkar #define QMAX 255 46*a1e29404SDevarsh Thakkar 47*a1e29404SDevarsh Thakkar /* Misc JPEG header definitions */ 48*a1e29404SDevarsh Thakkar #define UC_NUM_COMP 3 49*a1e29404SDevarsh Thakkar #define PRECISION 8 50*a1e29404SDevarsh Thakkar #define HORZ_SAMPLING_FACTOR (2 << 4) 51*a1e29404SDevarsh Thakkar #define VERT_SAMPLING_FACTOR_422 1 52*a1e29404SDevarsh Thakkar #define VERT_SAMPLING_FACTOR_420 2 53*a1e29404SDevarsh Thakkar #define COMPONENTS_IN_SCAN 3 54*a1e29404SDevarsh Thakkar #define PELS_IN_BLOCK 64 55*a1e29404SDevarsh Thakkar 56*a1e29404SDevarsh Thakkar /* Used for Qp table generation */ 57*a1e29404SDevarsh Thakkar #define LUMINOSITY 10 58*a1e29404SDevarsh Thakkar #define CONTRAST 1 59*a1e29404SDevarsh Thakkar #define INCREASE 2 60*a1e29404SDevarsh Thakkar #define QP_TABLE_SIZE (8 * 8) 61*a1e29404SDevarsh Thakkar #define QP_TABLE_FIELD_OFFSET 0x04 62*a1e29404SDevarsh Thakkar 63*a1e29404SDevarsh Thakkar /* 64*a1e29404SDevarsh Thakkar * vb2 queue structure 65*a1e29404SDevarsh Thakkar * contains queue data information 66*a1e29404SDevarsh Thakkar * 67*a1e29404SDevarsh Thakkar * @fmt: format info 68*a1e29404SDevarsh Thakkar * @width: frame width 69*a1e29404SDevarsh Thakkar * @height: frame height 70*a1e29404SDevarsh Thakkar * @bytesperline: bytes per line in memory 71*a1e29404SDevarsh Thakkar * @size_image: image size in memory 72*a1e29404SDevarsh Thakkar */ 73*a1e29404SDevarsh Thakkar struct e5010_q_data { 74*a1e29404SDevarsh Thakkar struct e5010_fmt *fmt; 75*a1e29404SDevarsh Thakkar u32 width; 76*a1e29404SDevarsh Thakkar u32 height; 77*a1e29404SDevarsh Thakkar u32 width_adjusted; 78*a1e29404SDevarsh Thakkar u32 height_adjusted; 79*a1e29404SDevarsh Thakkar u32 sizeimage[MAX_PLANES]; 80*a1e29404SDevarsh Thakkar u32 bytesperline[MAX_PLANES]; 81*a1e29404SDevarsh Thakkar u32 sequence; 82*a1e29404SDevarsh Thakkar struct v4l2_rect crop; 83*a1e29404SDevarsh Thakkar bool crop_set; 84*a1e29404SDevarsh Thakkar }; 85*a1e29404SDevarsh Thakkar 86*a1e29404SDevarsh Thakkar /* 87*a1e29404SDevarsh Thakkar * Driver device structure 88*a1e29404SDevarsh Thakkar * Holds all memory handles and global parameters 89*a1e29404SDevarsh Thakkar * Shared by all instances 90*a1e29404SDevarsh Thakkar */ 91*a1e29404SDevarsh Thakkar struct e5010_dev { 92*a1e29404SDevarsh Thakkar struct device *dev; 93*a1e29404SDevarsh Thakkar struct v4l2_device v4l2_dev; 94*a1e29404SDevarsh Thakkar struct v4l2_m2m_dev *m2m_dev; 95*a1e29404SDevarsh Thakkar struct video_device *vdev; 96*a1e29404SDevarsh Thakkar void __iomem *core_base; 97*a1e29404SDevarsh Thakkar void __iomem *mmu_base; 98*a1e29404SDevarsh Thakkar struct clk *clk; 99*a1e29404SDevarsh Thakkar struct e5010_context *last_context_run; 100*a1e29404SDevarsh Thakkar /* Protect access to device data */ 101*a1e29404SDevarsh Thakkar struct mutex mutex; 102*a1e29404SDevarsh Thakkar /* Protect access to hardware*/ 103*a1e29404SDevarsh Thakkar spinlock_t hw_lock; 104*a1e29404SDevarsh Thakkar }; 105*a1e29404SDevarsh Thakkar 106*a1e29404SDevarsh Thakkar /* 107*a1e29404SDevarsh Thakkar * Driver context structure 108*a1e29404SDevarsh Thakkar * One of these exists for every m2m context 109*a1e29404SDevarsh Thakkar * Holds context specific data 110*a1e29404SDevarsh Thakkar */ 111*a1e29404SDevarsh Thakkar struct e5010_context { 112*a1e29404SDevarsh Thakkar struct v4l2_fh fh; 113*a1e29404SDevarsh Thakkar struct e5010_dev *e5010; 114*a1e29404SDevarsh Thakkar struct e5010_q_data out_queue; 115*a1e29404SDevarsh Thakkar struct e5010_q_data cap_queue; 116*a1e29404SDevarsh Thakkar int quality; 117*a1e29404SDevarsh Thakkar bool update_qp; 118*a1e29404SDevarsh Thakkar struct v4l2_ctrl_handler ctrl_handler; 119*a1e29404SDevarsh Thakkar u8 luma_qp[QP_TABLE_SIZE]; 120*a1e29404SDevarsh Thakkar u8 chroma_qp[QP_TABLE_SIZE]; 121*a1e29404SDevarsh Thakkar }; 122*a1e29404SDevarsh Thakkar 123*a1e29404SDevarsh Thakkar /* 124*a1e29404SDevarsh Thakkar * Buffer structure 125*a1e29404SDevarsh Thakkar * Contains info for all buffers 126*a1e29404SDevarsh Thakkar */ 127*a1e29404SDevarsh Thakkar struct e5010_buffer { 128*a1e29404SDevarsh Thakkar struct v4l2_m2m_buffer buffer; 129*a1e29404SDevarsh Thakkar }; 130*a1e29404SDevarsh Thakkar 131*a1e29404SDevarsh Thakkar enum { 132*a1e29404SDevarsh Thakkar CHROMA_ORDER_CB_CR = 0, //UV ordering 133*a1e29404SDevarsh Thakkar CHROMA_ORDER_CR_CB = 1, //VU ordering 134*a1e29404SDevarsh Thakkar }; 135*a1e29404SDevarsh Thakkar 136*a1e29404SDevarsh Thakkar enum { 137*a1e29404SDevarsh Thakkar SUBSAMPLING_420 = 1, 138*a1e29404SDevarsh Thakkar SUBSAMPLING_422 = 2, 139*a1e29404SDevarsh Thakkar }; 140*a1e29404SDevarsh Thakkar 141*a1e29404SDevarsh Thakkar /* 142*a1e29404SDevarsh Thakkar * e5010 format structure 143*a1e29404SDevarsh Thakkar * contains format information 144*a1e29404SDevarsh Thakkar */ 145*a1e29404SDevarsh Thakkar struct e5010_fmt { 146*a1e29404SDevarsh Thakkar u32 fourcc; 147*a1e29404SDevarsh Thakkar unsigned int num_planes; 148*a1e29404SDevarsh Thakkar unsigned int type; 149*a1e29404SDevarsh Thakkar u32 subsampling; 150*a1e29404SDevarsh Thakkar u32 chroma_order; 151*a1e29404SDevarsh Thakkar const struct v4l2_frmsize_stepwise frmsize; 152*a1e29404SDevarsh Thakkar }; 153*a1e29404SDevarsh Thakkar 154*a1e29404SDevarsh Thakkar /* 155*a1e29404SDevarsh Thakkar * struct e5010_ctrl - contains info for each supported v4l2 control 156*a1e29404SDevarsh Thakkar */ 157*a1e29404SDevarsh Thakkar struct e5010_ctrl { 158*a1e29404SDevarsh Thakkar unsigned int cid; 159*a1e29404SDevarsh Thakkar enum v4l2_ctrl_type type; 160*a1e29404SDevarsh Thakkar unsigned char name[32]; 161*a1e29404SDevarsh Thakkar int minimum; 162*a1e29404SDevarsh Thakkar int maximum; 163*a1e29404SDevarsh Thakkar int step; 164*a1e29404SDevarsh Thakkar int default_value; 165*a1e29404SDevarsh Thakkar unsigned char compound; 166*a1e29404SDevarsh Thakkar }; 167*a1e29404SDevarsh Thakkar 168*a1e29404SDevarsh Thakkar #endif 169